spi-intel.c 37 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel PCH/PCU SPI flash driver.
  4. *
  5. * Copyright (C) 2016 - 2022, Intel Corporation
  6. * Author: Mika Westerberg <[email protected]>
  7. */
  8. #include <linux/iopoll.h>
  9. #include <linux/module.h>
  10. #include <linux/mtd/partitions.h>
  11. #include <linux/mtd/spi-nor.h>
  12. #include <linux/spi/flash.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/spi-mem.h>
  15. #include "spi-intel.h"
  16. /* Offsets are from @ispi->base */
  17. #define BFPREG 0x00
  18. #define HSFSTS_CTL 0x04
  19. #define HSFSTS_CTL_FSMIE BIT(31)
  20. #define HSFSTS_CTL_FDBC_SHIFT 24
  21. #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
  22. #define HSFSTS_CTL_FCYCLE_SHIFT 17
  23. #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
  24. /* HW sequencer opcodes */
  25. #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
  26. #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
  27. #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
  28. #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
  29. #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
  30. #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
  31. #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
  32. #define HSFSTS_CTL_FGO BIT(16)
  33. #define HSFSTS_CTL_FLOCKDN BIT(15)
  34. #define HSFSTS_CTL_FDV BIT(14)
  35. #define HSFSTS_CTL_SCIP BIT(5)
  36. #define HSFSTS_CTL_AEL BIT(2)
  37. #define HSFSTS_CTL_FCERR BIT(1)
  38. #define HSFSTS_CTL_FDONE BIT(0)
  39. #define FADDR 0x08
  40. #define DLOCK 0x0c
  41. #define FDATA(n) (0x10 + ((n) * 4))
  42. #define FRACC 0x50
  43. #define FREG(n) (0x54 + ((n) * 4))
  44. #define FREG_BASE_MASK GENMASK(14, 0)
  45. #define FREG_LIMIT_SHIFT 16
  46. #define FREG_LIMIT_MASK GENMASK(30, 16)
  47. /* Offset is from @ispi->pregs */
  48. #define PR(n) ((n) * 4)
  49. #define PR_WPE BIT(31)
  50. #define PR_LIMIT_SHIFT 16
  51. #define PR_LIMIT_MASK GENMASK(30, 16)
  52. #define PR_RPE BIT(15)
  53. #define PR_BASE_MASK GENMASK(14, 0)
  54. /* Offsets are from @ispi->sregs */
  55. #define SSFSTS_CTL 0x00
  56. #define SSFSTS_CTL_FSMIE BIT(23)
  57. #define SSFSTS_CTL_DS BIT(22)
  58. #define SSFSTS_CTL_DBC_SHIFT 16
  59. #define SSFSTS_CTL_SPOP BIT(11)
  60. #define SSFSTS_CTL_ACS BIT(10)
  61. #define SSFSTS_CTL_SCGO BIT(9)
  62. #define SSFSTS_CTL_COP_SHIFT 12
  63. #define SSFSTS_CTL_FRS BIT(7)
  64. #define SSFSTS_CTL_DOFRS BIT(6)
  65. #define SSFSTS_CTL_AEL BIT(4)
  66. #define SSFSTS_CTL_FCERR BIT(3)
  67. #define SSFSTS_CTL_FDONE BIT(2)
  68. #define SSFSTS_CTL_SCIP BIT(0)
  69. #define PREOP_OPTYPE 0x04
  70. #define OPMENU0 0x08
  71. #define OPMENU1 0x0c
  72. #define OPTYPE_READ_NO_ADDR 0
  73. #define OPTYPE_WRITE_NO_ADDR 1
  74. #define OPTYPE_READ_WITH_ADDR 2
  75. #define OPTYPE_WRITE_WITH_ADDR 3
  76. /* CPU specifics */
  77. #define BYT_PR 0x74
  78. #define BYT_SSFSTS_CTL 0x90
  79. #define BYT_FREG_NUM 5
  80. #define BYT_PR_NUM 5
  81. #define LPT_PR 0x74
  82. #define LPT_SSFSTS_CTL 0x90
  83. #define LPT_FREG_NUM 5
  84. #define LPT_PR_NUM 5
  85. #define BXT_PR 0x84
  86. #define BXT_SSFSTS_CTL 0xa0
  87. #define BXT_FREG_NUM 12
  88. #define BXT_PR_NUM 6
  89. #define CNL_PR 0x84
  90. #define CNL_FREG_NUM 6
  91. #define CNL_PR_NUM 5
  92. #define LVSCC 0xc4
  93. #define UVSCC 0xc8
  94. #define ERASE_OPCODE_SHIFT 8
  95. #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
  96. #define ERASE_64K_OPCODE_SHIFT 16
  97. #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
  98. /* Flash descriptor fields */
  99. #define FLVALSIG_MAGIC 0x0ff0a55a
  100. #define FLMAP0_NC_MASK GENMASK(9, 8)
  101. #define FLMAP0_NC_SHIFT 8
  102. #define FLMAP0_FCBA_MASK GENMASK(7, 0)
  103. #define FLCOMP_C0DEN_MASK GENMASK(3, 0)
  104. #define FLCOMP_C0DEN_512K 0x00
  105. #define FLCOMP_C0DEN_1M 0x01
  106. #define FLCOMP_C0DEN_2M 0x02
  107. #define FLCOMP_C0DEN_4M 0x03
  108. #define FLCOMP_C0DEN_8M 0x04
  109. #define FLCOMP_C0DEN_16M 0x05
  110. #define FLCOMP_C0DEN_32M 0x06
  111. #define FLCOMP_C0DEN_64M 0x07
  112. #define INTEL_SPI_TIMEOUT 5000 /* ms */
  113. #define INTEL_SPI_FIFO_SZ 64
  114. /**
  115. * struct intel_spi - Driver private data
  116. * @dev: Device pointer
  117. * @info: Pointer to board specific info
  118. * @base: Beginning of MMIO space
  119. * @pregs: Start of protection registers
  120. * @sregs: Start of software sequencer registers
  121. * @master: Pointer to the SPI controller structure
  122. * @nregions: Maximum number of regions
  123. * @pr_num: Maximum number of protected range registers
  124. * @chip0_size: Size of the first flash chip in bytes
  125. * @locked: Is SPI setting locked
  126. * @swseq_reg: Use SW sequencer in register reads/writes
  127. * @swseq_erase: Use SW sequencer in erase operation
  128. * @atomic_preopcode: Holds preopcode when atomic sequence is requested
  129. * @opcodes: Opcodes which are supported. This are programmed by BIOS
  130. * before it locks down the controller.
  131. * @mem_ops: Pointer to SPI MEM ops supported by the controller
  132. */
  133. struct intel_spi {
  134. struct device *dev;
  135. const struct intel_spi_boardinfo *info;
  136. void __iomem *base;
  137. void __iomem *pregs;
  138. void __iomem *sregs;
  139. struct spi_controller *master;
  140. size_t nregions;
  141. size_t pr_num;
  142. size_t chip0_size;
  143. bool locked;
  144. bool swseq_reg;
  145. bool swseq_erase;
  146. u8 atomic_preopcode;
  147. u8 opcodes[8];
  148. const struct intel_spi_mem_op *mem_ops;
  149. };
  150. struct intel_spi_mem_op {
  151. struct spi_mem_op mem_op;
  152. u32 replacement_op;
  153. int (*exec_op)(struct intel_spi *ispi,
  154. const struct spi_mem *mem,
  155. const struct intel_spi_mem_op *iop,
  156. const struct spi_mem_op *op);
  157. };
  158. static bool writeable;
  159. module_param(writeable, bool, 0);
  160. MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
  161. static void intel_spi_dump_regs(struct intel_spi *ispi)
  162. {
  163. u32 value;
  164. int i;
  165. dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
  166. value = readl(ispi->base + HSFSTS_CTL);
  167. dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
  168. if (value & HSFSTS_CTL_FLOCKDN)
  169. dev_dbg(ispi->dev, "-> Locked\n");
  170. dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
  171. dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
  172. for (i = 0; i < 16; i++)
  173. dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
  174. i, readl(ispi->base + FDATA(i)));
  175. dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
  176. for (i = 0; i < ispi->nregions; i++)
  177. dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
  178. readl(ispi->base + FREG(i)));
  179. for (i = 0; i < ispi->pr_num; i++)
  180. dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
  181. readl(ispi->pregs + PR(i)));
  182. if (ispi->sregs) {
  183. value = readl(ispi->sregs + SSFSTS_CTL);
  184. dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
  185. dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
  186. readl(ispi->sregs + PREOP_OPTYPE));
  187. dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
  188. readl(ispi->sregs + OPMENU0));
  189. dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
  190. readl(ispi->sregs + OPMENU1));
  191. }
  192. dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
  193. dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
  194. dev_dbg(ispi->dev, "Protected regions:\n");
  195. for (i = 0; i < ispi->pr_num; i++) {
  196. u32 base, limit;
  197. value = readl(ispi->pregs + PR(i));
  198. if (!(value & (PR_WPE | PR_RPE)))
  199. continue;
  200. limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
  201. base = value & PR_BASE_MASK;
  202. dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
  203. i, base << 12, (limit << 12) | 0xfff,
  204. value & PR_WPE ? 'W' : '.', value & PR_RPE ? 'R' : '.');
  205. }
  206. dev_dbg(ispi->dev, "Flash regions:\n");
  207. for (i = 0; i < ispi->nregions; i++) {
  208. u32 region, base, limit;
  209. region = readl(ispi->base + FREG(i));
  210. base = region & FREG_BASE_MASK;
  211. limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
  212. if (base >= limit || (i > 0 && limit == 0))
  213. dev_dbg(ispi->dev, " %02d disabled\n", i);
  214. else
  215. dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
  216. i, base << 12, (limit << 12) | 0xfff);
  217. }
  218. dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
  219. ispi->swseq_reg ? 'S' : 'H');
  220. dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
  221. ispi->swseq_erase ? 'S' : 'H');
  222. }
  223. /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
  224. static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
  225. {
  226. size_t bytes;
  227. int i = 0;
  228. if (size > INTEL_SPI_FIFO_SZ)
  229. return -EINVAL;
  230. while (size > 0) {
  231. bytes = min_t(size_t, size, 4);
  232. memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
  233. size -= bytes;
  234. buf += bytes;
  235. i++;
  236. }
  237. return 0;
  238. }
  239. /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
  240. static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
  241. size_t size)
  242. {
  243. size_t bytes;
  244. int i = 0;
  245. if (size > INTEL_SPI_FIFO_SZ)
  246. return -EINVAL;
  247. while (size > 0) {
  248. bytes = min_t(size_t, size, 4);
  249. memcpy_toio(ispi->base + FDATA(i), buf, bytes);
  250. size -= bytes;
  251. buf += bytes;
  252. i++;
  253. }
  254. return 0;
  255. }
  256. static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
  257. {
  258. u32 val;
  259. return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
  260. !(val & HSFSTS_CTL_SCIP), 0,
  261. INTEL_SPI_TIMEOUT * 1000);
  262. }
  263. static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
  264. {
  265. u32 val;
  266. return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
  267. !(val & SSFSTS_CTL_SCIP), 0,
  268. INTEL_SPI_TIMEOUT * 1000);
  269. }
  270. static bool intel_spi_set_writeable(struct intel_spi *ispi)
  271. {
  272. if (!ispi->info->set_writeable)
  273. return false;
  274. return ispi->info->set_writeable(ispi->base, ispi->info->data);
  275. }
  276. static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
  277. {
  278. int i;
  279. int preop;
  280. if (ispi->locked) {
  281. for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
  282. if (ispi->opcodes[i] == opcode)
  283. return i;
  284. return -EINVAL;
  285. }
  286. /* The lock is off, so just use index 0 */
  287. writel(opcode, ispi->sregs + OPMENU0);
  288. preop = readw(ispi->sregs + PREOP_OPTYPE);
  289. writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
  290. return 0;
  291. }
  292. static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
  293. {
  294. u32 val, status;
  295. int ret;
  296. val = readl(ispi->base + HSFSTS_CTL);
  297. val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
  298. switch (opcode) {
  299. case SPINOR_OP_RDID:
  300. val |= HSFSTS_CTL_FCYCLE_RDID;
  301. break;
  302. case SPINOR_OP_WRSR:
  303. val |= HSFSTS_CTL_FCYCLE_WRSR;
  304. break;
  305. case SPINOR_OP_RDSR:
  306. val |= HSFSTS_CTL_FCYCLE_RDSR;
  307. break;
  308. default:
  309. return -EINVAL;
  310. }
  311. if (len > INTEL_SPI_FIFO_SZ)
  312. return -EINVAL;
  313. val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
  314. val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
  315. val |= HSFSTS_CTL_FGO;
  316. writel(val, ispi->base + HSFSTS_CTL);
  317. ret = intel_spi_wait_hw_busy(ispi);
  318. if (ret)
  319. return ret;
  320. status = readl(ispi->base + HSFSTS_CTL);
  321. if (status & HSFSTS_CTL_FCERR)
  322. return -EIO;
  323. else if (status & HSFSTS_CTL_AEL)
  324. return -EACCES;
  325. return 0;
  326. }
  327. static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
  328. int optype)
  329. {
  330. u32 val = 0, status;
  331. u8 atomic_preopcode;
  332. int ret;
  333. ret = intel_spi_opcode_index(ispi, opcode, optype);
  334. if (ret < 0)
  335. return ret;
  336. if (len > INTEL_SPI_FIFO_SZ)
  337. return -EINVAL;
  338. /*
  339. * Always clear it after each SW sequencer operation regardless
  340. * of whether it is successful or not.
  341. */
  342. atomic_preopcode = ispi->atomic_preopcode;
  343. ispi->atomic_preopcode = 0;
  344. /* Only mark 'Data Cycle' bit when there is data to be transferred */
  345. if (len > 0)
  346. val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
  347. val |= ret << SSFSTS_CTL_COP_SHIFT;
  348. val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
  349. val |= SSFSTS_CTL_SCGO;
  350. if (atomic_preopcode) {
  351. u16 preop;
  352. switch (optype) {
  353. case OPTYPE_WRITE_NO_ADDR:
  354. case OPTYPE_WRITE_WITH_ADDR:
  355. /* Pick matching preopcode for the atomic sequence */
  356. preop = readw(ispi->sregs + PREOP_OPTYPE);
  357. if ((preop & 0xff) == atomic_preopcode)
  358. ; /* Do nothing */
  359. else if ((preop >> 8) == atomic_preopcode)
  360. val |= SSFSTS_CTL_SPOP;
  361. else
  362. return -EINVAL;
  363. /* Enable atomic sequence */
  364. val |= SSFSTS_CTL_ACS;
  365. break;
  366. default:
  367. return -EINVAL;
  368. }
  369. }
  370. writel(val, ispi->sregs + SSFSTS_CTL);
  371. ret = intel_spi_wait_sw_busy(ispi);
  372. if (ret)
  373. return ret;
  374. status = readl(ispi->sregs + SSFSTS_CTL);
  375. if (status & SSFSTS_CTL_FCERR)
  376. return -EIO;
  377. else if (status & SSFSTS_CTL_AEL)
  378. return -EACCES;
  379. return 0;
  380. }
  381. static u32 intel_spi_chip_addr(const struct intel_spi *ispi,
  382. const struct spi_mem *mem)
  383. {
  384. /* Pick up the correct start address */
  385. if (!mem)
  386. return 0;
  387. return mem->spi->chip_select == 1 ? ispi->chip0_size : 0;
  388. }
  389. static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,
  390. const struct intel_spi_mem_op *iop,
  391. const struct spi_mem_op *op)
  392. {
  393. size_t nbytes = op->data.nbytes;
  394. u8 opcode = op->cmd.opcode;
  395. int ret;
  396. writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR);
  397. if (ispi->swseq_reg)
  398. ret = intel_spi_sw_cycle(ispi, opcode, nbytes,
  399. OPTYPE_READ_NO_ADDR);
  400. else
  401. ret = intel_spi_hw_cycle(ispi, opcode, nbytes);
  402. if (ret)
  403. return ret;
  404. return intel_spi_read_block(ispi, op->data.buf.in, nbytes);
  405. }
  406. static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem,
  407. const struct intel_spi_mem_op *iop,
  408. const struct spi_mem_op *op)
  409. {
  410. size_t nbytes = op->data.nbytes;
  411. u8 opcode = op->cmd.opcode;
  412. int ret;
  413. /*
  414. * This is handled with atomic operation and preop code in Intel
  415. * controller so we only verify that it is available. If the
  416. * controller is not locked, program the opcode to the PREOP
  417. * register for later use.
  418. *
  419. * When hardware sequencer is used there is no need to program
  420. * any opcodes (it handles them automatically as part of a command).
  421. */
  422. if (opcode == SPINOR_OP_WREN) {
  423. u16 preop;
  424. if (!ispi->swseq_reg)
  425. return 0;
  426. preop = readw(ispi->sregs + PREOP_OPTYPE);
  427. if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {
  428. if (ispi->locked)
  429. return -EINVAL;
  430. writel(opcode, ispi->sregs + PREOP_OPTYPE);
  431. }
  432. /*
  433. * This enables atomic sequence on next SW sycle. Will
  434. * be cleared after next operation.
  435. */
  436. ispi->atomic_preopcode = opcode;
  437. return 0;
  438. }
  439. /*
  440. * We hope that HW sequencer will do the right thing automatically and
  441. * with the SW sequencer we cannot use preopcode anyway, so just ignore
  442. * the Write Disable operation and pretend it was completed
  443. * successfully.
  444. */
  445. if (opcode == SPINOR_OP_WRDI)
  446. return 0;
  447. writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR);
  448. /* Write the value beforehand */
  449. ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);
  450. if (ret)
  451. return ret;
  452. if (ispi->swseq_reg)
  453. return intel_spi_sw_cycle(ispi, opcode, nbytes,
  454. OPTYPE_WRITE_NO_ADDR);
  455. return intel_spi_hw_cycle(ispi, opcode, nbytes);
  456. }
  457. static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,
  458. const struct intel_spi_mem_op *iop,
  459. const struct spi_mem_op *op)
  460. {
  461. u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
  462. size_t block_size, nbytes = op->data.nbytes;
  463. void *read_buf = op->data.buf.in;
  464. u32 val, status;
  465. int ret;
  466. /*
  467. * Atomic sequence is not expected with HW sequencer reads. Make
  468. * sure it is cleared regardless.
  469. */
  470. if (WARN_ON_ONCE(ispi->atomic_preopcode))
  471. ispi->atomic_preopcode = 0;
  472. while (nbytes > 0) {
  473. block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ);
  474. /* Read cannot cross 4K boundary */
  475. block_size = min_t(loff_t, addr + block_size,
  476. round_up(addr + 1, SZ_4K)) - addr;
  477. writel(addr, ispi->base + FADDR);
  478. val = readl(ispi->base + HSFSTS_CTL);
  479. val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
  480. val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
  481. val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
  482. val |= HSFSTS_CTL_FCYCLE_READ;
  483. val |= HSFSTS_CTL_FGO;
  484. writel(val, ispi->base + HSFSTS_CTL);
  485. ret = intel_spi_wait_hw_busy(ispi);
  486. if (ret)
  487. return ret;
  488. status = readl(ispi->base + HSFSTS_CTL);
  489. if (status & HSFSTS_CTL_FCERR)
  490. ret = -EIO;
  491. else if (status & HSFSTS_CTL_AEL)
  492. ret = -EACCES;
  493. if (ret < 0) {
  494. dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);
  495. return ret;
  496. }
  497. ret = intel_spi_read_block(ispi, read_buf, block_size);
  498. if (ret)
  499. return ret;
  500. nbytes -= block_size;
  501. addr += block_size;
  502. read_buf += block_size;
  503. }
  504. return 0;
  505. }
  506. static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem,
  507. const struct intel_spi_mem_op *iop,
  508. const struct spi_mem_op *op)
  509. {
  510. u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
  511. size_t block_size, nbytes = op->data.nbytes;
  512. const void *write_buf = op->data.buf.out;
  513. u32 val, status;
  514. int ret;
  515. /* Not needed with HW sequencer write, make sure it is cleared */
  516. ispi->atomic_preopcode = 0;
  517. while (nbytes > 0) {
  518. block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ);
  519. /* Write cannot cross 4K boundary */
  520. block_size = min_t(loff_t, addr + block_size,
  521. round_up(addr + 1, SZ_4K)) - addr;
  522. writel(addr, ispi->base + FADDR);
  523. val = readl(ispi->base + HSFSTS_CTL);
  524. val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
  525. val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
  526. val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
  527. val |= HSFSTS_CTL_FCYCLE_WRITE;
  528. ret = intel_spi_write_block(ispi, write_buf, block_size);
  529. if (ret) {
  530. dev_err(ispi->dev, "failed to write block\n");
  531. return ret;
  532. }
  533. /* Start the write now */
  534. val |= HSFSTS_CTL_FGO;
  535. writel(val, ispi->base + HSFSTS_CTL);
  536. ret = intel_spi_wait_hw_busy(ispi);
  537. if (ret) {
  538. dev_err(ispi->dev, "timeout\n");
  539. return ret;
  540. }
  541. status = readl(ispi->base + HSFSTS_CTL);
  542. if (status & HSFSTS_CTL_FCERR)
  543. ret = -EIO;
  544. else if (status & HSFSTS_CTL_AEL)
  545. ret = -EACCES;
  546. if (ret < 0) {
  547. dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);
  548. return ret;
  549. }
  550. nbytes -= block_size;
  551. addr += block_size;
  552. write_buf += block_size;
  553. }
  554. return 0;
  555. }
  556. static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem,
  557. const struct intel_spi_mem_op *iop,
  558. const struct spi_mem_op *op)
  559. {
  560. u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
  561. u8 opcode = op->cmd.opcode;
  562. u32 val, status;
  563. int ret;
  564. writel(addr, ispi->base + FADDR);
  565. if (ispi->swseq_erase)
  566. return intel_spi_sw_cycle(ispi, opcode, 0,
  567. OPTYPE_WRITE_WITH_ADDR);
  568. /* Not needed with HW sequencer erase, make sure it is cleared */
  569. ispi->atomic_preopcode = 0;
  570. val = readl(ispi->base + HSFSTS_CTL);
  571. val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
  572. val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
  573. val |= HSFSTS_CTL_FGO;
  574. val |= iop->replacement_op;
  575. writel(val, ispi->base + HSFSTS_CTL);
  576. ret = intel_spi_wait_hw_busy(ispi);
  577. if (ret)
  578. return ret;
  579. status = readl(ispi->base + HSFSTS_CTL);
  580. if (status & HSFSTS_CTL_FCERR)
  581. return -EIO;
  582. if (status & HSFSTS_CTL_AEL)
  583. return -EACCES;
  584. return 0;
  585. }
  586. static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop,
  587. const struct spi_mem_op *op)
  588. {
  589. if (iop->mem_op.cmd.nbytes != op->cmd.nbytes ||
  590. iop->mem_op.cmd.buswidth != op->cmd.buswidth ||
  591. iop->mem_op.cmd.dtr != op->cmd.dtr ||
  592. iop->mem_op.cmd.opcode != op->cmd.opcode)
  593. return false;
  594. if (iop->mem_op.addr.nbytes != op->addr.nbytes ||
  595. iop->mem_op.addr.dtr != op->addr.dtr)
  596. return false;
  597. if (iop->mem_op.data.dir != op->data.dir ||
  598. iop->mem_op.data.dtr != op->data.dtr)
  599. return false;
  600. if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) {
  601. if (iop->mem_op.data.buswidth != op->data.buswidth)
  602. return false;
  603. }
  604. return true;
  605. }
  606. static const struct intel_spi_mem_op *
  607. intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op)
  608. {
  609. const struct intel_spi_mem_op *iop;
  610. for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {
  611. if (intel_spi_cmp_mem_op(iop, op))
  612. break;
  613. }
  614. return iop->mem_op.cmd.opcode ? iop : NULL;
  615. }
  616. static bool intel_spi_supports_mem_op(struct spi_mem *mem,
  617. const struct spi_mem_op *op)
  618. {
  619. struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);
  620. const struct intel_spi_mem_op *iop;
  621. iop = intel_spi_match_mem_op(ispi, op);
  622. if (!iop) {
  623. dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);
  624. return false;
  625. }
  626. /*
  627. * For software sequencer check that the opcode is actually
  628. * present in the opmenu if it is locked.
  629. */
  630. if (ispi->swseq_reg && ispi->locked) {
  631. int i;
  632. /* Check if it is in the locked opcodes list */
  633. for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {
  634. if (ispi->opcodes[i] == op->cmd.opcode)
  635. return true;
  636. }
  637. dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);
  638. return false;
  639. }
  640. return true;
  641. }
  642. static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
  643. {
  644. struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);
  645. const struct intel_spi_mem_op *iop;
  646. iop = intel_spi_match_mem_op(ispi, op);
  647. if (!iop)
  648. return -EOPNOTSUPP;
  649. return iop->exec_op(ispi, mem, iop, op);
  650. }
  651. static const char *intel_spi_get_name(struct spi_mem *mem)
  652. {
  653. const struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);
  654. /*
  655. * Return name of the flash controller device to be compatible
  656. * with the MTD version.
  657. */
  658. return dev_name(ispi->dev);
  659. }
  660. static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
  661. {
  662. struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master);
  663. const struct intel_spi_mem_op *iop;
  664. iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);
  665. if (!iop)
  666. return -EOPNOTSUPP;
  667. desc->priv = (void *)iop;
  668. return 0;
  669. }
  670. static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs,
  671. size_t len, void *buf)
  672. {
  673. struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master);
  674. const struct intel_spi_mem_op *iop = desc->priv;
  675. struct spi_mem_op op = desc->info.op_tmpl;
  676. int ret;
  677. /* Fill in the gaps */
  678. op.addr.val = offs;
  679. op.data.nbytes = len;
  680. op.data.buf.in = buf;
  681. ret = iop->exec_op(ispi, desc->mem, iop, &op);
  682. return ret ? ret : len;
  683. }
  684. static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs,
  685. size_t len, const void *buf)
  686. {
  687. struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master);
  688. const struct intel_spi_mem_op *iop = desc->priv;
  689. struct spi_mem_op op = desc->info.op_tmpl;
  690. int ret;
  691. op.addr.val = offs;
  692. op.data.nbytes = len;
  693. op.data.buf.out = buf;
  694. ret = iop->exec_op(ispi, desc->mem, iop, &op);
  695. return ret ? ret : len;
  696. }
  697. static const struct spi_controller_mem_ops intel_spi_mem_ops = {
  698. .supports_op = intel_spi_supports_mem_op,
  699. .exec_op = intel_spi_exec_mem_op,
  700. .get_name = intel_spi_get_name,
  701. .dirmap_create = intel_spi_dirmap_create,
  702. .dirmap_read = intel_spi_dirmap_read,
  703. .dirmap_write = intel_spi_dirmap_write,
  704. };
  705. #define INTEL_SPI_OP_ADDR(__nbytes) \
  706. { \
  707. .nbytes = __nbytes, \
  708. }
  709. #define INTEL_SPI_OP_NO_DATA \
  710. { \
  711. .dir = SPI_MEM_NO_DATA, \
  712. }
  713. #define INTEL_SPI_OP_DATA_IN(__buswidth) \
  714. { \
  715. .dir = SPI_MEM_DATA_IN, \
  716. .buswidth = __buswidth, \
  717. }
  718. #define INTEL_SPI_OP_DATA_OUT(__buswidth) \
  719. { \
  720. .dir = SPI_MEM_DATA_OUT, \
  721. .buswidth = __buswidth, \
  722. }
  723. #define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) \
  724. { \
  725. .mem_op = { \
  726. .cmd = __cmd, \
  727. .addr = __addr, \
  728. .data = __data, \
  729. }, \
  730. .exec_op = __exec_op, \
  731. }
  732. #define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) \
  733. { \
  734. .mem_op = { \
  735. .cmd = __cmd, \
  736. .addr = __addr, \
  737. .data = __data, \
  738. }, \
  739. .exec_op = __exec_op, \
  740. .replacement_op = __repl, \
  741. }
  742. /*
  743. * The controller handles pretty much everything internally based on the
  744. * SFDP data but we want to make sure we only support the operations
  745. * actually possible. Only check buswidth and transfer direction, the
  746. * core validates data.
  747. */
  748. #define INTEL_SPI_GENERIC_OPS \
  749. /* Status register operations */ \
  750. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \
  751. SPI_MEM_OP_NO_ADDR, \
  752. INTEL_SPI_OP_DATA_IN(1), \
  753. intel_spi_read_reg), \
  754. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \
  755. SPI_MEM_OP_NO_ADDR, \
  756. INTEL_SPI_OP_DATA_IN(1), \
  757. intel_spi_read_reg), \
  758. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \
  759. SPI_MEM_OP_NO_ADDR, \
  760. INTEL_SPI_OP_DATA_OUT(1), \
  761. intel_spi_write_reg), \
  762. /* Normal read */ \
  763. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
  764. INTEL_SPI_OP_ADDR(3), \
  765. INTEL_SPI_OP_DATA_IN(1), \
  766. intel_spi_read), \
  767. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
  768. INTEL_SPI_OP_ADDR(3), \
  769. INTEL_SPI_OP_DATA_IN(2), \
  770. intel_spi_read), \
  771. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
  772. INTEL_SPI_OP_ADDR(3), \
  773. INTEL_SPI_OP_DATA_IN(4), \
  774. intel_spi_read), \
  775. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
  776. INTEL_SPI_OP_ADDR(4), \
  777. INTEL_SPI_OP_DATA_IN(1), \
  778. intel_spi_read), \
  779. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
  780. INTEL_SPI_OP_ADDR(4), \
  781. INTEL_SPI_OP_DATA_IN(2), \
  782. intel_spi_read), \
  783. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
  784. INTEL_SPI_OP_ADDR(4), \
  785. INTEL_SPI_OP_DATA_IN(4), \
  786. intel_spi_read), \
  787. /* Fast read */ \
  788. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
  789. INTEL_SPI_OP_ADDR(3), \
  790. INTEL_SPI_OP_DATA_IN(1), \
  791. intel_spi_read), \
  792. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
  793. INTEL_SPI_OP_ADDR(3), \
  794. INTEL_SPI_OP_DATA_IN(2), \
  795. intel_spi_read), \
  796. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
  797. INTEL_SPI_OP_ADDR(3), \
  798. INTEL_SPI_OP_DATA_IN(4), \
  799. intel_spi_read), \
  800. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
  801. INTEL_SPI_OP_ADDR(4), \
  802. INTEL_SPI_OP_DATA_IN(1), \
  803. intel_spi_read), \
  804. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
  805. INTEL_SPI_OP_ADDR(4), \
  806. INTEL_SPI_OP_DATA_IN(2), \
  807. intel_spi_read), \
  808. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
  809. INTEL_SPI_OP_ADDR(4), \
  810. INTEL_SPI_OP_DATA_IN(4), \
  811. intel_spi_read), \
  812. /* Read with 4-byte address opcode */ \
  813. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \
  814. INTEL_SPI_OP_ADDR(4), \
  815. INTEL_SPI_OP_DATA_IN(1), \
  816. intel_spi_read), \
  817. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \
  818. INTEL_SPI_OP_ADDR(4), \
  819. INTEL_SPI_OP_DATA_IN(2), \
  820. intel_spi_read), \
  821. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \
  822. INTEL_SPI_OP_ADDR(4), \
  823. INTEL_SPI_OP_DATA_IN(4), \
  824. intel_spi_read), \
  825. /* Fast read with 4-byte address opcode */ \
  826. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \
  827. INTEL_SPI_OP_ADDR(4), \
  828. INTEL_SPI_OP_DATA_IN(1), \
  829. intel_spi_read), \
  830. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \
  831. INTEL_SPI_OP_ADDR(4), \
  832. INTEL_SPI_OP_DATA_IN(2), \
  833. intel_spi_read), \
  834. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \
  835. INTEL_SPI_OP_ADDR(4), \
  836. INTEL_SPI_OP_DATA_IN(4), \
  837. intel_spi_read), \
  838. /* Write operations */ \
  839. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \
  840. INTEL_SPI_OP_ADDR(3), \
  841. INTEL_SPI_OP_DATA_OUT(1), \
  842. intel_spi_write), \
  843. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \
  844. INTEL_SPI_OP_ADDR(4), \
  845. INTEL_SPI_OP_DATA_OUT(1), \
  846. intel_spi_write), \
  847. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP_4B, 1), \
  848. INTEL_SPI_OP_ADDR(4), \
  849. INTEL_SPI_OP_DATA_OUT(1), \
  850. intel_spi_write), \
  851. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), \
  852. SPI_MEM_OP_NO_ADDR, \
  853. SPI_MEM_OP_NO_DATA, \
  854. intel_spi_write_reg), \
  855. INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), \
  856. SPI_MEM_OP_NO_ADDR, \
  857. SPI_MEM_OP_NO_DATA, \
  858. intel_spi_write_reg), \
  859. /* Erase operations */ \
  860. INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \
  861. INTEL_SPI_OP_ADDR(3), \
  862. SPI_MEM_OP_NO_DATA, \
  863. intel_spi_erase, \
  864. HSFSTS_CTL_FCYCLE_ERASE), \
  865. INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \
  866. INTEL_SPI_OP_ADDR(4), \
  867. SPI_MEM_OP_NO_DATA, \
  868. intel_spi_erase, \
  869. HSFSTS_CTL_FCYCLE_ERASE), \
  870. INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K_4B, 1), \
  871. INTEL_SPI_OP_ADDR(4), \
  872. SPI_MEM_OP_NO_DATA, \
  873. intel_spi_erase, \
  874. HSFSTS_CTL_FCYCLE_ERASE) \
  875. static const struct intel_spi_mem_op generic_mem_ops[] = {
  876. INTEL_SPI_GENERIC_OPS,
  877. { },
  878. };
  879. static const struct intel_spi_mem_op erase_64k_mem_ops[] = {
  880. INTEL_SPI_GENERIC_OPS,
  881. /* 64k sector erase operations */
  882. INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1),
  883. INTEL_SPI_OP_ADDR(3),
  884. SPI_MEM_OP_NO_DATA,
  885. intel_spi_erase,
  886. HSFSTS_CTL_FCYCLE_ERASE_64K),
  887. INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1),
  888. INTEL_SPI_OP_ADDR(4),
  889. SPI_MEM_OP_NO_DATA,
  890. intel_spi_erase,
  891. HSFSTS_CTL_FCYCLE_ERASE_64K),
  892. INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE_4B, 1),
  893. INTEL_SPI_OP_ADDR(4),
  894. SPI_MEM_OP_NO_DATA,
  895. intel_spi_erase,
  896. HSFSTS_CTL_FCYCLE_ERASE_64K),
  897. { },
  898. };
  899. static int intel_spi_init(struct intel_spi *ispi)
  900. {
  901. u32 opmenu0, opmenu1, lvscc, uvscc, val;
  902. bool erase_64k = false;
  903. int i;
  904. switch (ispi->info->type) {
  905. case INTEL_SPI_BYT:
  906. ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
  907. ispi->pregs = ispi->base + BYT_PR;
  908. ispi->nregions = BYT_FREG_NUM;
  909. ispi->pr_num = BYT_PR_NUM;
  910. ispi->swseq_reg = true;
  911. break;
  912. case INTEL_SPI_LPT:
  913. ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
  914. ispi->pregs = ispi->base + LPT_PR;
  915. ispi->nregions = LPT_FREG_NUM;
  916. ispi->pr_num = LPT_PR_NUM;
  917. ispi->swseq_reg = true;
  918. break;
  919. case INTEL_SPI_BXT:
  920. ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
  921. ispi->pregs = ispi->base + BXT_PR;
  922. ispi->nregions = BXT_FREG_NUM;
  923. ispi->pr_num = BXT_PR_NUM;
  924. erase_64k = true;
  925. break;
  926. case INTEL_SPI_CNL:
  927. ispi->sregs = NULL;
  928. ispi->pregs = ispi->base + CNL_PR;
  929. ispi->nregions = CNL_FREG_NUM;
  930. ispi->pr_num = CNL_PR_NUM;
  931. erase_64k = true;
  932. break;
  933. default:
  934. return -EINVAL;
  935. }
  936. /* Try to disable write protection if user asked to do so */
  937. if (writeable && !intel_spi_set_writeable(ispi)) {
  938. dev_warn(ispi->dev, "can't disable chip write protection\n");
  939. writeable = false;
  940. }
  941. /* Disable #SMI generation from HW sequencer */
  942. val = readl(ispi->base + HSFSTS_CTL);
  943. val &= ~HSFSTS_CTL_FSMIE;
  944. writel(val, ispi->base + HSFSTS_CTL);
  945. /*
  946. * Determine whether erase operation should use HW or SW sequencer.
  947. *
  948. * The HW sequencer has a predefined list of opcodes, with only the
  949. * erase opcode being programmable in LVSCC and UVSCC registers.
  950. * If these registers don't contain a valid erase opcode, erase
  951. * cannot be done using HW sequencer.
  952. */
  953. lvscc = readl(ispi->base + LVSCC);
  954. uvscc = readl(ispi->base + UVSCC);
  955. if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
  956. ispi->swseq_erase = true;
  957. /* SPI controller on Intel BXT supports 64K erase opcode */
  958. if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
  959. if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
  960. !(uvscc & ERASE_64K_OPCODE_MASK))
  961. erase_64k = false;
  962. if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {
  963. dev_err(ispi->dev, "software sequencer not supported, but required\n");
  964. return -EINVAL;
  965. }
  966. /*
  967. * Some controllers can only do basic operations using hardware
  968. * sequencer. All other operations are supposed to be carried out
  969. * using software sequencer.
  970. */
  971. if (ispi->swseq_reg) {
  972. /* Disable #SMI generation from SW sequencer */
  973. val = readl(ispi->sregs + SSFSTS_CTL);
  974. val &= ~SSFSTS_CTL_FSMIE;
  975. writel(val, ispi->sregs + SSFSTS_CTL);
  976. }
  977. /* Check controller's lock status */
  978. val = readl(ispi->base + HSFSTS_CTL);
  979. ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
  980. if (ispi->locked && ispi->sregs) {
  981. /*
  982. * BIOS programs allowed opcodes and then locks down the
  983. * register. So read back what opcodes it decided to support.
  984. * That's the set we are going to support as well.
  985. */
  986. opmenu0 = readl(ispi->sregs + OPMENU0);
  987. opmenu1 = readl(ispi->sregs + OPMENU1);
  988. if (opmenu0 && opmenu1) {
  989. for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
  990. ispi->opcodes[i] = opmenu0 >> i * 8;
  991. ispi->opcodes[i + 4] = opmenu1 >> i * 8;
  992. }
  993. }
  994. }
  995. if (erase_64k) {
  996. dev_dbg(ispi->dev, "Using erase_64k memory operations");
  997. ispi->mem_ops = erase_64k_mem_ops;
  998. } else {
  999. dev_dbg(ispi->dev, "Using generic memory operations");
  1000. ispi->mem_ops = generic_mem_ops;
  1001. }
  1002. intel_spi_dump_regs(ispi);
  1003. return 0;
  1004. }
  1005. static bool intel_spi_is_protected(const struct intel_spi *ispi,
  1006. unsigned int base, unsigned int limit)
  1007. {
  1008. int i;
  1009. for (i = 0; i < ispi->pr_num; i++) {
  1010. u32 pr_base, pr_limit, pr_value;
  1011. pr_value = readl(ispi->pregs + PR(i));
  1012. if (!(pr_value & (PR_WPE | PR_RPE)))
  1013. continue;
  1014. pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
  1015. pr_base = pr_value & PR_BASE_MASK;
  1016. if (pr_base >= base && pr_limit <= limit)
  1017. return true;
  1018. }
  1019. return false;
  1020. }
  1021. /*
  1022. * There will be a single partition holding all enabled flash regions. We
  1023. * call this "BIOS".
  1024. */
  1025. static void intel_spi_fill_partition(struct intel_spi *ispi,
  1026. struct mtd_partition *part)
  1027. {
  1028. u64 end;
  1029. int i;
  1030. memset(part, 0, sizeof(*part));
  1031. /* Start from the mandatory descriptor region */
  1032. part->size = 4096;
  1033. part->name = "BIOS";
  1034. /*
  1035. * Now try to find where this partition ends based on the flash
  1036. * region registers.
  1037. */
  1038. for (i = 1; i < ispi->nregions; i++) {
  1039. u32 region, base, limit;
  1040. region = readl(ispi->base + FREG(i));
  1041. base = region & FREG_BASE_MASK;
  1042. limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
  1043. if (base >= limit || limit == 0)
  1044. continue;
  1045. /*
  1046. * If any of the regions have protection bits set, make the
  1047. * whole partition read-only to be on the safe side.
  1048. *
  1049. * Also if the user did not ask the chip to be writeable
  1050. * mask the bit too.
  1051. */
  1052. if (!writeable || intel_spi_is_protected(ispi, base, limit))
  1053. part->mask_flags |= MTD_WRITEABLE;
  1054. end = (limit << 12) + 4096;
  1055. if (end > part->size)
  1056. part->size = end;
  1057. }
  1058. }
  1059. static int intel_spi_read_desc(struct intel_spi *ispi)
  1060. {
  1061. struct spi_mem_op op =
  1062. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 0),
  1063. SPI_MEM_OP_ADDR(3, 0, 0),
  1064. SPI_MEM_OP_NO_DUMMY,
  1065. SPI_MEM_OP_DATA_IN(0, NULL, 0));
  1066. u32 buf[2], nc, fcba, flcomp;
  1067. ssize_t ret;
  1068. op.addr.val = 0x10;
  1069. op.data.buf.in = buf;
  1070. op.data.nbytes = sizeof(buf);
  1071. ret = intel_spi_read(ispi, NULL, NULL, &op);
  1072. if (ret) {
  1073. dev_warn(ispi->dev, "failed to read descriptor\n");
  1074. return ret;
  1075. }
  1076. dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);
  1077. dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);
  1078. if (buf[0] != FLVALSIG_MAGIC) {
  1079. dev_warn(ispi->dev, "descriptor signature not valid\n");
  1080. return -ENODEV;
  1081. }
  1082. fcba = (buf[1] & FLMAP0_FCBA_MASK) << 4;
  1083. dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);
  1084. op.addr.val = fcba;
  1085. op.data.buf.in = &flcomp;
  1086. op.data.nbytes = sizeof(flcomp);
  1087. ret = intel_spi_read(ispi, NULL, NULL, &op);
  1088. if (ret) {
  1089. dev_warn(ispi->dev, "failed to read FLCOMP\n");
  1090. return -ENODEV;
  1091. }
  1092. dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);
  1093. switch (flcomp & FLCOMP_C0DEN_MASK) {
  1094. case FLCOMP_C0DEN_512K:
  1095. ispi->chip0_size = SZ_512K;
  1096. break;
  1097. case FLCOMP_C0DEN_1M:
  1098. ispi->chip0_size = SZ_1M;
  1099. break;
  1100. case FLCOMP_C0DEN_2M:
  1101. ispi->chip0_size = SZ_2M;
  1102. break;
  1103. case FLCOMP_C0DEN_4M:
  1104. ispi->chip0_size = SZ_4M;
  1105. break;
  1106. case FLCOMP_C0DEN_8M:
  1107. ispi->chip0_size = SZ_8M;
  1108. break;
  1109. case FLCOMP_C0DEN_16M:
  1110. ispi->chip0_size = SZ_16M;
  1111. break;
  1112. case FLCOMP_C0DEN_32M:
  1113. ispi->chip0_size = SZ_32M;
  1114. break;
  1115. case FLCOMP_C0DEN_64M:
  1116. ispi->chip0_size = SZ_64M;
  1117. break;
  1118. default:
  1119. return -EINVAL;
  1120. }
  1121. dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);
  1122. nc = (buf[1] & FLMAP0_NC_MASK) >> FLMAP0_NC_SHIFT;
  1123. if (!nc)
  1124. ispi->master->num_chipselect = 1;
  1125. else if (nc == 1)
  1126. ispi->master->num_chipselect = 2;
  1127. else
  1128. return -EINVAL;
  1129. dev_dbg(ispi->dev, "%u flash components found\n",
  1130. ispi->master->num_chipselect);
  1131. return 0;
  1132. }
  1133. static int intel_spi_populate_chip(struct intel_spi *ispi)
  1134. {
  1135. struct flash_platform_data *pdata;
  1136. struct spi_board_info chip;
  1137. int ret;
  1138. pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);
  1139. if (!pdata)
  1140. return -ENOMEM;
  1141. pdata->nr_parts = 1;
  1142. pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,
  1143. sizeof(*pdata->parts), GFP_KERNEL);
  1144. if (!pdata->parts)
  1145. return -ENOMEM;
  1146. intel_spi_fill_partition(ispi, pdata->parts);
  1147. memset(&chip, 0, sizeof(chip));
  1148. snprintf(chip.modalias, 8, "spi-nor");
  1149. chip.platform_data = pdata;
  1150. if (!spi_new_device(ispi->master, &chip))
  1151. return -ENODEV;
  1152. ret = intel_spi_read_desc(ispi);
  1153. if (ret)
  1154. return ret;
  1155. /* Add the second chip if present */
  1156. if (ispi->master->num_chipselect < 2)
  1157. return 0;
  1158. chip.platform_data = NULL;
  1159. chip.chip_select = 1;
  1160. if (!spi_new_device(ispi->master, &chip))
  1161. return -ENODEV;
  1162. return 0;
  1163. }
  1164. /**
  1165. * intel_spi_probe() - Probe the Intel SPI flash controller
  1166. * @dev: Pointer to the parent device
  1167. * @mem: MMIO resource
  1168. * @info: Platform specific information
  1169. *
  1170. * Probes Intel SPI flash controller and creates the flash chip device.
  1171. * Returns %0 on success and negative errno in case of failure.
  1172. */
  1173. int intel_spi_probe(struct device *dev, struct resource *mem,
  1174. const struct intel_spi_boardinfo *info)
  1175. {
  1176. struct spi_controller *master;
  1177. struct intel_spi *ispi;
  1178. int ret;
  1179. master = devm_spi_alloc_master(dev, sizeof(*ispi));
  1180. if (!master)
  1181. return -ENOMEM;
  1182. master->mem_ops = &intel_spi_mem_ops;
  1183. ispi = spi_master_get_devdata(master);
  1184. ispi->base = devm_ioremap_resource(dev, mem);
  1185. if (IS_ERR(ispi->base))
  1186. return PTR_ERR(ispi->base);
  1187. ispi->dev = dev;
  1188. ispi->master = master;
  1189. ispi->info = info;
  1190. ret = intel_spi_init(ispi);
  1191. if (ret)
  1192. return ret;
  1193. ret = devm_spi_register_master(dev, master);
  1194. if (ret)
  1195. return ret;
  1196. return intel_spi_populate_chip(ispi);
  1197. }
  1198. EXPORT_SYMBOL_GPL(intel_spi_probe);
  1199. MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
  1200. MODULE_AUTHOR("Mika Westerberg <[email protected]>");
  1201. MODULE_LICENSE("GPL v2");