spi-ingenic.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SPI bus driver for the Ingenic SoCs
  4. * Copyright (c) 2017-2021 Artur Rojek <[email protected]>
  5. * Copyright (c) 2017-2021 Paul Cercueil <[email protected]>
  6. * Copyright (c) 2022 周琰杰 (Zhou Yanjie) <[email protected]>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. #include <linux/spi/spi.h>
  18. #define REG_SSIDR 0x0
  19. #define REG_SSICR0 0x4
  20. #define REG_SSICR1 0x8
  21. #define REG_SSISR 0xc
  22. #define REG_SSIGR 0x18
  23. #define REG_SSICR0_TENDIAN_LSB BIT(19)
  24. #define REG_SSICR0_RENDIAN_LSB BIT(17)
  25. #define REG_SSICR0_SSIE BIT(15)
  26. #define REG_SSICR0_LOOP BIT(10)
  27. #define REG_SSICR0_EACLRUN BIT(7)
  28. #define REG_SSICR0_FSEL BIT(6)
  29. #define REG_SSICR0_TFLUSH BIT(2)
  30. #define REG_SSICR0_RFLUSH BIT(1)
  31. #define REG_SSICR1_FRMHL_MASK (BIT(31) | BIT(30))
  32. #define REG_SSICR1_FRMHL BIT(30)
  33. #define REG_SSICR1_LFST BIT(25)
  34. #define REG_SSICR1_UNFIN BIT(23)
  35. #define REG_SSICR1_PHA BIT(1)
  36. #define REG_SSICR1_POL BIT(0)
  37. #define REG_SSISR_END BIT(7)
  38. #define REG_SSISR_BUSY BIT(6)
  39. #define REG_SSISR_TFF BIT(5)
  40. #define REG_SSISR_RFE BIT(4)
  41. #define REG_SSISR_RFHF BIT(2)
  42. #define REG_SSISR_UNDR BIT(1)
  43. #define REG_SSISR_OVER BIT(0)
  44. #define SPI_INGENIC_FIFO_SIZE 128u
  45. struct jz_soc_info {
  46. u32 bits_per_word_mask;
  47. struct reg_field flen_field;
  48. bool has_trendian;
  49. unsigned int max_speed_hz;
  50. unsigned int max_native_cs;
  51. };
  52. struct ingenic_spi {
  53. const struct jz_soc_info *soc_info;
  54. struct clk *clk;
  55. struct resource *mem_res;
  56. struct regmap *map;
  57. struct regmap_field *flen_field;
  58. };
  59. static int spi_ingenic_wait(struct ingenic_spi *priv,
  60. unsigned long mask,
  61. bool condition)
  62. {
  63. unsigned int val;
  64. return regmap_read_poll_timeout(priv->map, REG_SSISR, val,
  65. !!(val & mask) == condition,
  66. 100, 10000);
  67. }
  68. static void spi_ingenic_set_cs(struct spi_device *spi, bool disable)
  69. {
  70. struct ingenic_spi *priv = spi_controller_get_devdata(spi->controller);
  71. if (disable) {
  72. regmap_clear_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
  73. regmap_clear_bits(priv->map, REG_SSISR,
  74. REG_SSISR_UNDR | REG_SSISR_OVER);
  75. spi_ingenic_wait(priv, REG_SSISR_END, true);
  76. } else {
  77. regmap_set_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
  78. }
  79. regmap_set_bits(priv->map, REG_SSICR0,
  80. REG_SSICR0_RFLUSH | REG_SSICR0_TFLUSH);
  81. }
  82. static void spi_ingenic_prepare_transfer(struct ingenic_spi *priv,
  83. struct spi_device *spi,
  84. struct spi_transfer *xfer)
  85. {
  86. unsigned long clk_hz = clk_get_rate(priv->clk);
  87. u32 cdiv, speed_hz = xfer->speed_hz ?: spi->max_speed_hz,
  88. bits_per_word = xfer->bits_per_word ?: spi->bits_per_word;
  89. cdiv = clk_hz / (speed_hz * 2);
  90. cdiv = clamp(cdiv, 1u, 0x100u) - 1;
  91. regmap_write(priv->map, REG_SSIGR, cdiv);
  92. regmap_field_write(priv->flen_field, bits_per_word - 2);
  93. }
  94. static void spi_ingenic_finalize_transfer(void *controller)
  95. {
  96. spi_finalize_current_transfer(controller);
  97. }
  98. static struct dma_async_tx_descriptor *
  99. spi_ingenic_prepare_dma(struct spi_controller *ctlr, struct dma_chan *chan,
  100. struct sg_table *sg, enum dma_transfer_direction dir,
  101. unsigned int bits)
  102. {
  103. struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
  104. struct dma_slave_config cfg = {
  105. .direction = dir,
  106. .src_addr = priv->mem_res->start + REG_SSIDR,
  107. .dst_addr = priv->mem_res->start + REG_SSIDR,
  108. };
  109. struct dma_async_tx_descriptor *desc;
  110. dma_cookie_t cookie;
  111. int ret;
  112. if (bits > 16) {
  113. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  114. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  115. cfg.src_maxburst = cfg.dst_maxburst = 4;
  116. } else if (bits > 8) {
  117. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  118. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  119. cfg.src_maxburst = cfg.dst_maxburst = 2;
  120. } else {
  121. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  122. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  123. cfg.src_maxburst = cfg.dst_maxburst = 1;
  124. }
  125. ret = dmaengine_slave_config(chan, &cfg);
  126. if (ret)
  127. return ERR_PTR(ret);
  128. desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, dir,
  129. DMA_PREP_INTERRUPT);
  130. if (!desc)
  131. return ERR_PTR(-ENOMEM);
  132. if (dir == DMA_DEV_TO_MEM) {
  133. desc->callback = spi_ingenic_finalize_transfer;
  134. desc->callback_param = ctlr;
  135. }
  136. cookie = dmaengine_submit(desc);
  137. ret = dma_submit_error(cookie);
  138. if (ret) {
  139. dmaengine_desc_free(desc);
  140. return ERR_PTR(ret);
  141. }
  142. return desc;
  143. }
  144. static int spi_ingenic_dma_tx(struct spi_controller *ctlr,
  145. struct spi_transfer *xfer, unsigned int bits)
  146. {
  147. struct dma_async_tx_descriptor *rx_desc, *tx_desc;
  148. rx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_rx,
  149. &xfer->rx_sg, DMA_DEV_TO_MEM, bits);
  150. if (IS_ERR(rx_desc))
  151. return PTR_ERR(rx_desc);
  152. tx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_tx,
  153. &xfer->tx_sg, DMA_MEM_TO_DEV, bits);
  154. if (IS_ERR(tx_desc)) {
  155. dmaengine_terminate_async(ctlr->dma_rx);
  156. dmaengine_desc_free(rx_desc);
  157. return PTR_ERR(tx_desc);
  158. }
  159. dma_async_issue_pending(ctlr->dma_rx);
  160. dma_async_issue_pending(ctlr->dma_tx);
  161. return 1;
  162. }
  163. #define SPI_INGENIC_TX(x) \
  164. static int spi_ingenic_tx##x(struct ingenic_spi *priv, \
  165. struct spi_transfer *xfer) \
  166. { \
  167. unsigned int count = xfer->len / (x / 8); \
  168. unsigned int prefill = min(count, SPI_INGENIC_FIFO_SIZE); \
  169. const u##x *tx_buf = xfer->tx_buf; \
  170. u##x *rx_buf = xfer->rx_buf; \
  171. unsigned int i, val; \
  172. int err; \
  173. \
  174. /* Fill up the TX fifo */ \
  175. for (i = 0; i < prefill; i++) { \
  176. val = tx_buf ? tx_buf[i] : 0; \
  177. \
  178. regmap_write(priv->map, REG_SSIDR, val); \
  179. } \
  180. \
  181. for (i = 0; i < count; i++) { \
  182. err = spi_ingenic_wait(priv, REG_SSISR_RFE, false); \
  183. if (err) \
  184. return err; \
  185. \
  186. regmap_read(priv->map, REG_SSIDR, &val); \
  187. if (rx_buf) \
  188. rx_buf[i] = val; \
  189. \
  190. if (i < count - prefill) { \
  191. val = tx_buf ? tx_buf[i + prefill] : 0; \
  192. \
  193. regmap_write(priv->map, REG_SSIDR, val); \
  194. } \
  195. } \
  196. \
  197. return 0; \
  198. }
  199. SPI_INGENIC_TX(8)
  200. SPI_INGENIC_TX(16)
  201. SPI_INGENIC_TX(32)
  202. #undef SPI_INGENIC_TX
  203. static int spi_ingenic_transfer_one(struct spi_controller *ctlr,
  204. struct spi_device *spi,
  205. struct spi_transfer *xfer)
  206. {
  207. struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
  208. unsigned int bits = xfer->bits_per_word ?: spi->bits_per_word;
  209. bool can_dma = ctlr->can_dma && ctlr->can_dma(ctlr, spi, xfer);
  210. spi_ingenic_prepare_transfer(priv, spi, xfer);
  211. if (ctlr->cur_msg_mapped && can_dma)
  212. return spi_ingenic_dma_tx(ctlr, xfer, bits);
  213. if (bits > 16)
  214. return spi_ingenic_tx32(priv, xfer);
  215. if (bits > 8)
  216. return spi_ingenic_tx16(priv, xfer);
  217. return spi_ingenic_tx8(priv, xfer);
  218. }
  219. static int spi_ingenic_prepare_message(struct spi_controller *ctlr,
  220. struct spi_message *message)
  221. {
  222. struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
  223. struct spi_device *spi = message->spi;
  224. unsigned int cs = REG_SSICR1_FRMHL << spi->chip_select;
  225. unsigned int ssicr0_mask = REG_SSICR0_LOOP | REG_SSICR0_FSEL;
  226. unsigned int ssicr1_mask = REG_SSICR1_PHA | REG_SSICR1_POL | cs;
  227. unsigned int ssicr0 = 0, ssicr1 = 0;
  228. if (priv->soc_info->has_trendian) {
  229. ssicr0_mask |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
  230. if (spi->mode & SPI_LSB_FIRST)
  231. ssicr0 |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
  232. } else {
  233. ssicr1_mask |= REG_SSICR1_LFST;
  234. if (spi->mode & SPI_LSB_FIRST)
  235. ssicr1 |= REG_SSICR1_LFST;
  236. }
  237. if (spi->mode & SPI_LOOP)
  238. ssicr0 |= REG_SSICR0_LOOP;
  239. if (spi->chip_select)
  240. ssicr0 |= REG_SSICR0_FSEL;
  241. if (spi->mode & SPI_CPHA)
  242. ssicr1 |= REG_SSICR1_PHA;
  243. if (spi->mode & SPI_CPOL)
  244. ssicr1 |= REG_SSICR1_POL;
  245. if (spi->mode & SPI_CS_HIGH)
  246. ssicr1 |= cs;
  247. regmap_update_bits(priv->map, REG_SSICR0, ssicr0_mask, ssicr0);
  248. regmap_update_bits(priv->map, REG_SSICR1, ssicr1_mask, ssicr1);
  249. return 0;
  250. }
  251. static int spi_ingenic_prepare_hardware(struct spi_controller *ctlr)
  252. {
  253. struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
  254. int ret;
  255. ret = clk_prepare_enable(priv->clk);
  256. if (ret)
  257. return ret;
  258. regmap_write(priv->map, REG_SSICR0, REG_SSICR0_EACLRUN);
  259. regmap_write(priv->map, REG_SSICR1, 0);
  260. regmap_write(priv->map, REG_SSISR, 0);
  261. regmap_set_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
  262. return 0;
  263. }
  264. static int spi_ingenic_unprepare_hardware(struct spi_controller *ctlr)
  265. {
  266. struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
  267. regmap_clear_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
  268. clk_disable_unprepare(priv->clk);
  269. return 0;
  270. }
  271. static bool spi_ingenic_can_dma(struct spi_controller *ctlr,
  272. struct spi_device *spi,
  273. struct spi_transfer *xfer)
  274. {
  275. struct dma_slave_caps caps;
  276. int ret;
  277. ret = dma_get_slave_caps(ctlr->dma_tx, &caps);
  278. if (ret) {
  279. dev_err(&spi->dev, "Unable to get slave caps: %d\n", ret);
  280. return false;
  281. }
  282. return !caps.max_sg_burst ||
  283. xfer->len <= caps.max_sg_burst * SPI_INGENIC_FIFO_SIZE;
  284. }
  285. static int spi_ingenic_request_dma(struct spi_controller *ctlr,
  286. struct device *dev)
  287. {
  288. ctlr->dma_tx = dma_request_slave_channel(dev, "tx");
  289. if (!ctlr->dma_tx)
  290. return -ENODEV;
  291. ctlr->dma_rx = dma_request_slave_channel(dev, "rx");
  292. if (!ctlr->dma_rx)
  293. return -ENODEV;
  294. ctlr->can_dma = spi_ingenic_can_dma;
  295. return 0;
  296. }
  297. static void spi_ingenic_release_dma(void *data)
  298. {
  299. struct spi_controller *ctlr = data;
  300. if (ctlr->dma_tx)
  301. dma_release_channel(ctlr->dma_tx);
  302. if (ctlr->dma_rx)
  303. dma_release_channel(ctlr->dma_rx);
  304. }
  305. static const struct regmap_config spi_ingenic_regmap_config = {
  306. .reg_bits = 32,
  307. .val_bits = 32,
  308. .reg_stride = 4,
  309. .max_register = REG_SSIGR,
  310. };
  311. static int spi_ingenic_probe(struct platform_device *pdev)
  312. {
  313. const struct jz_soc_info *pdata;
  314. struct device *dev = &pdev->dev;
  315. struct spi_controller *ctlr;
  316. struct ingenic_spi *priv;
  317. void __iomem *base;
  318. int num_cs, ret;
  319. pdata = of_device_get_match_data(dev);
  320. if (!pdata) {
  321. dev_err(dev, "Missing platform data.\n");
  322. return -EINVAL;
  323. }
  324. ctlr = devm_spi_alloc_master(dev, sizeof(*priv));
  325. if (!ctlr) {
  326. dev_err(dev, "Unable to allocate SPI controller.\n");
  327. return -ENOMEM;
  328. }
  329. priv = spi_controller_get_devdata(ctlr);
  330. priv->soc_info = pdata;
  331. priv->clk = devm_clk_get(dev, NULL);
  332. if (IS_ERR(priv->clk)) {
  333. return dev_err_probe(dev, PTR_ERR(priv->clk),
  334. "Unable to get clock.\n");
  335. }
  336. base = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->mem_res);
  337. if (IS_ERR(base))
  338. return PTR_ERR(base);
  339. priv->map = devm_regmap_init_mmio(dev, base, &spi_ingenic_regmap_config);
  340. if (IS_ERR(priv->map))
  341. return PTR_ERR(priv->map);
  342. priv->flen_field = devm_regmap_field_alloc(dev, priv->map,
  343. pdata->flen_field);
  344. if (IS_ERR(priv->flen_field))
  345. return PTR_ERR(priv->flen_field);
  346. if (device_property_read_u32(dev, "num-cs", &num_cs))
  347. num_cs = pdata->max_native_cs;
  348. platform_set_drvdata(pdev, ctlr);
  349. ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware;
  350. ctlr->unprepare_transfer_hardware = spi_ingenic_unprepare_hardware;
  351. ctlr->prepare_message = spi_ingenic_prepare_message;
  352. ctlr->set_cs = spi_ingenic_set_cs;
  353. ctlr->transfer_one = spi_ingenic_transfer_one;
  354. ctlr->mode_bits = SPI_MODE_3 | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH;
  355. ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
  356. ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE;
  357. ctlr->bits_per_word_mask = pdata->bits_per_word_mask;
  358. ctlr->min_speed_hz = 7200;
  359. ctlr->max_speed_hz = pdata->max_speed_hz;
  360. ctlr->use_gpio_descriptors = true;
  361. ctlr->max_native_cs = pdata->max_native_cs;
  362. ctlr->num_chipselect = num_cs;
  363. ctlr->dev.of_node = pdev->dev.of_node;
  364. if (spi_ingenic_request_dma(ctlr, dev))
  365. dev_warn(dev, "DMA not available.\n");
  366. ret = devm_add_action_or_reset(dev, spi_ingenic_release_dma, ctlr);
  367. if (ret) {
  368. dev_err(dev, "Unable to add action.\n");
  369. return ret;
  370. }
  371. ret = devm_spi_register_controller(dev, ctlr);
  372. if (ret)
  373. dev_err(dev, "Unable to register SPI controller.\n");
  374. return ret;
  375. }
  376. static const struct jz_soc_info jz4750_soc_info = {
  377. .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17),
  378. .flen_field = REG_FIELD(REG_SSICR1, 4, 7),
  379. .has_trendian = false,
  380. .max_speed_hz = 54000000,
  381. .max_native_cs = 2,
  382. };
  383. static const struct jz_soc_info jz4780_soc_info = {
  384. .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
  385. .flen_field = REG_FIELD(REG_SSICR1, 3, 7),
  386. .has_trendian = true,
  387. .max_speed_hz = 54000000,
  388. .max_native_cs = 2,
  389. };
  390. static const struct jz_soc_info x1000_soc_info = {
  391. .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
  392. .flen_field = REG_FIELD(REG_SSICR1, 3, 7),
  393. .has_trendian = true,
  394. .max_speed_hz = 50000000,
  395. .max_native_cs = 2,
  396. };
  397. static const struct jz_soc_info x2000_soc_info = {
  398. .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
  399. .flen_field = REG_FIELD(REG_SSICR1, 3, 7),
  400. .has_trendian = true,
  401. .max_speed_hz = 50000000,
  402. .max_native_cs = 1,
  403. };
  404. static const struct of_device_id spi_ingenic_of_match[] = {
  405. { .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info },
  406. { .compatible = "ingenic,jz4775-spi", .data = &jz4780_soc_info },
  407. { .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info },
  408. { .compatible = "ingenic,x1000-spi", .data = &x1000_soc_info },
  409. { .compatible = "ingenic,x2000-spi", .data = &x2000_soc_info },
  410. {}
  411. };
  412. MODULE_DEVICE_TABLE(of, spi_ingenic_of_match);
  413. static struct platform_driver spi_ingenic_driver = {
  414. .driver = {
  415. .name = "spi-ingenic",
  416. .of_match_table = spi_ingenic_of_match,
  417. },
  418. .probe = spi_ingenic_probe,
  419. };
  420. module_platform_driver(spi_ingenic_driver);
  421. MODULE_DESCRIPTION("SPI bus driver for the Ingenic SoCs");
  422. MODULE_AUTHOR("Artur Rojek <[email protected]>");
  423. MODULE_AUTHOR("Paul Cercueil <[email protected]>");
  424. MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <[email protected]>");
  425. MODULE_LICENSE("GPL");