spi-fsl-spi.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale SPI controller driver.
  4. *
  5. * Maintainer: Kumar Gala
  6. *
  7. * Copyright (C) 2006 Polycom, Inc.
  8. * Copyright 2010 Freescale Semiconductor, Inc.
  9. *
  10. * CPM SPI and QE buffer descriptors mode support:
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. * Author: Anton Vorontsov <[email protected]>
  13. *
  14. * GRLIB support:
  15. * Copyright (c) 2012 Aeroflex Gaisler AB.
  16. * Author: Andreas Larsson <[email protected]>
  17. */
  18. #include <linux/delay.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/gpio/consumer.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/kernel.h>
  25. #include <linux/mm.h>
  26. #include <linux/module.h>
  27. #include <linux/mutex.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/of_platform.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/spi_bitbang.h>
  35. #include <linux/types.h>
  36. #ifdef CONFIG_FSL_SOC
  37. #include <sysdev/fsl_soc.h>
  38. #endif
  39. /* Specific to the MPC8306/MPC8309 */
  40. #define IMMR_SPI_CS_OFFSET 0x14c
  41. #define SPI_BOOT_SEL_BIT 0x80000000
  42. #include "spi-fsl-lib.h"
  43. #include "spi-fsl-cpm.h"
  44. #include "spi-fsl-spi.h"
  45. #define TYPE_FSL 0
  46. #define TYPE_GRLIB 1
  47. struct fsl_spi_match_data {
  48. int type;
  49. };
  50. static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  51. .type = TYPE_FSL,
  52. };
  53. static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  54. .type = TYPE_GRLIB,
  55. };
  56. static const struct of_device_id of_fsl_spi_match[] = {
  57. {
  58. .compatible = "fsl,spi",
  59. .data = &of_fsl_spi_fsl_config,
  60. },
  61. {
  62. .compatible = "aeroflexgaisler,spictrl",
  63. .data = &of_fsl_spi_grlib_config,
  64. },
  65. {}
  66. };
  67. MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  68. static int fsl_spi_get_type(struct device *dev)
  69. {
  70. const struct of_device_id *match;
  71. if (dev->of_node) {
  72. match = of_match_node(of_fsl_spi_match, dev->of_node);
  73. if (match && match->data)
  74. return ((struct fsl_spi_match_data *)match->data)->type;
  75. }
  76. return TYPE_FSL;
  77. }
  78. static void fsl_spi_change_mode(struct spi_device *spi)
  79. {
  80. struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  81. struct spi_mpc8xxx_cs *cs = spi->controller_state;
  82. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  83. __be32 __iomem *mode = &reg_base->mode;
  84. unsigned long flags;
  85. if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  86. return;
  87. /* Turn off IRQs locally to minimize time that SPI is disabled. */
  88. local_irq_save(flags);
  89. /* Turn off SPI unit prior changing mode */
  90. mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
  91. /* When in CPM mode, we need to reinit tx and rx. */
  92. if (mspi->flags & SPI_CPM_MODE) {
  93. fsl_spi_cpm_reinit_txrx(mspi);
  94. }
  95. mpc8xxx_spi_write_reg(mode, cs->hw_mode);
  96. local_irq_restore(flags);
  97. }
  98. static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
  99. int bits_per_word, int msb_first)
  100. {
  101. *rx_shift = 0;
  102. *tx_shift = 0;
  103. if (msb_first) {
  104. if (bits_per_word <= 8) {
  105. *rx_shift = 16;
  106. *tx_shift = 24;
  107. } else if (bits_per_word <= 16) {
  108. *rx_shift = 16;
  109. *tx_shift = 16;
  110. }
  111. } else {
  112. if (bits_per_word <= 8)
  113. *rx_shift = 8;
  114. }
  115. }
  116. static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
  117. int bits_per_word, int msb_first)
  118. {
  119. *rx_shift = 0;
  120. *tx_shift = 0;
  121. if (bits_per_word <= 16) {
  122. if (msb_first) {
  123. *rx_shift = 16; /* LSB in bit 16 */
  124. *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
  125. } else {
  126. *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
  127. }
  128. }
  129. }
  130. static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
  131. struct spi_device *spi,
  132. struct mpc8xxx_spi *mpc8xxx_spi,
  133. int bits_per_word)
  134. {
  135. cs->rx_shift = 0;
  136. cs->tx_shift = 0;
  137. if (bits_per_word <= 8) {
  138. cs->get_rx = mpc8xxx_spi_rx_buf_u8;
  139. cs->get_tx = mpc8xxx_spi_tx_buf_u8;
  140. } else if (bits_per_word <= 16) {
  141. cs->get_rx = mpc8xxx_spi_rx_buf_u16;
  142. cs->get_tx = mpc8xxx_spi_tx_buf_u16;
  143. } else if (bits_per_word <= 32) {
  144. cs->get_rx = mpc8xxx_spi_rx_buf_u32;
  145. cs->get_tx = mpc8xxx_spi_tx_buf_u32;
  146. } else
  147. return -EINVAL;
  148. if (mpc8xxx_spi->set_shifts)
  149. mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
  150. bits_per_word,
  151. !(spi->mode & SPI_LSB_FIRST));
  152. mpc8xxx_spi->rx_shift = cs->rx_shift;
  153. mpc8xxx_spi->tx_shift = cs->tx_shift;
  154. mpc8xxx_spi->get_rx = cs->get_rx;
  155. mpc8xxx_spi->get_tx = cs->get_tx;
  156. return bits_per_word;
  157. }
  158. static int fsl_spi_setup_transfer(struct spi_device *spi,
  159. struct spi_transfer *t)
  160. {
  161. struct mpc8xxx_spi *mpc8xxx_spi;
  162. int bits_per_word = 0;
  163. u8 pm;
  164. u32 hz = 0;
  165. struct spi_mpc8xxx_cs *cs = spi->controller_state;
  166. mpc8xxx_spi = spi_master_get_devdata(spi->master);
  167. if (t) {
  168. bits_per_word = t->bits_per_word;
  169. hz = t->speed_hz;
  170. }
  171. /* spi_transfer level calls that work per-word */
  172. if (!bits_per_word)
  173. bits_per_word = spi->bits_per_word;
  174. if (!hz)
  175. hz = spi->max_speed_hz;
  176. if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
  177. bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
  178. mpc8xxx_spi,
  179. bits_per_word);
  180. if (bits_per_word < 0)
  181. return bits_per_word;
  182. if (bits_per_word == 32)
  183. bits_per_word = 0;
  184. else
  185. bits_per_word = bits_per_word - 1;
  186. /* mask out bits we are going to set */
  187. cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
  188. | SPMODE_PM(0xF));
  189. cs->hw_mode |= SPMODE_LEN(bits_per_word);
  190. if ((mpc8xxx_spi->spibrg / hz) > 64) {
  191. cs->hw_mode |= SPMODE_DIV16;
  192. pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
  193. WARN_ONCE(pm > 16,
  194. "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
  195. dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
  196. if (pm > 16)
  197. pm = 16;
  198. } else {
  199. pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
  200. }
  201. if (pm)
  202. pm--;
  203. cs->hw_mode |= SPMODE_PM(pm);
  204. fsl_spi_change_mode(spi);
  205. return 0;
  206. }
  207. static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
  208. struct spi_transfer *t, unsigned int len)
  209. {
  210. u32 word;
  211. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  212. mspi->count = len;
  213. /* enable rx ints */
  214. mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
  215. /* transmit word */
  216. word = mspi->get_tx(mspi);
  217. mpc8xxx_spi_write_reg(&reg_base->transmit, word);
  218. return 0;
  219. }
  220. static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
  221. bool is_dma_mapped)
  222. {
  223. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
  224. struct fsl_spi_reg __iomem *reg_base;
  225. unsigned int len = t->len;
  226. u8 bits_per_word;
  227. int ret;
  228. reg_base = mpc8xxx_spi->reg_base;
  229. bits_per_word = spi->bits_per_word;
  230. if (t->bits_per_word)
  231. bits_per_word = t->bits_per_word;
  232. if (bits_per_word > 8) {
  233. /* invalid length? */
  234. if (len & 1)
  235. return -EINVAL;
  236. len /= 2;
  237. }
  238. if (bits_per_word > 16) {
  239. /* invalid length? */
  240. if (len & 1)
  241. return -EINVAL;
  242. len /= 2;
  243. }
  244. mpc8xxx_spi->tx = t->tx_buf;
  245. mpc8xxx_spi->rx = t->rx_buf;
  246. reinit_completion(&mpc8xxx_spi->done);
  247. if (mpc8xxx_spi->flags & SPI_CPM_MODE)
  248. ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
  249. else
  250. ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
  251. if (ret)
  252. return ret;
  253. wait_for_completion(&mpc8xxx_spi->done);
  254. /* disable rx ints */
  255. mpc8xxx_spi_write_reg(&reg_base->mask, 0);
  256. if (mpc8xxx_spi->flags & SPI_CPM_MODE)
  257. fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
  258. return mpc8xxx_spi->count;
  259. }
  260. static int fsl_spi_prepare_message(struct spi_controller *ctlr,
  261. struct spi_message *m)
  262. {
  263. struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
  264. struct spi_transfer *t;
  265. struct spi_transfer *first;
  266. first = list_first_entry(&m->transfers, struct spi_transfer,
  267. transfer_list);
  268. /*
  269. * In CPU mode, optimize large byte transfers to use larger
  270. * bits_per_word values to reduce number of interrupts taken.
  271. *
  272. * Some glitches can appear on the SPI clock when the mode changes.
  273. * Check that there is no speed change during the transfer and set it up
  274. * now to change the mode without having a chip-select asserted.
  275. */
  276. list_for_each_entry(t, &m->transfers, transfer_list) {
  277. if (t->speed_hz != first->speed_hz) {
  278. dev_err(&m->spi->dev,
  279. "speed_hz cannot change during message.\n");
  280. return -EINVAL;
  281. }
  282. if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
  283. if (t->len < 256 || t->bits_per_word != 8)
  284. continue;
  285. if ((t->len & 3) == 0)
  286. t->bits_per_word = 32;
  287. else if ((t->len & 1) == 0)
  288. t->bits_per_word = 16;
  289. } else {
  290. /*
  291. * CPM/QE uses Little Endian for words > 8
  292. * so transform 16 and 32 bits words into 8 bits
  293. * Unfortnatly that doesn't work for LSB so
  294. * reject these for now
  295. * Note: 32 bits word, LSB works iff
  296. * tfcr/rfcr is set to CPMFCR_GBL
  297. */
  298. if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)
  299. return -EINVAL;
  300. if (t->bits_per_word == 16 || t->bits_per_word == 32)
  301. t->bits_per_word = 8; /* pretend its 8 bits */
  302. if (t->bits_per_word == 8 && t->len >= 256 &&
  303. (mpc8xxx_spi->flags & SPI_CPM1))
  304. t->bits_per_word = 16;
  305. }
  306. }
  307. return fsl_spi_setup_transfer(m->spi, first);
  308. }
  309. static int fsl_spi_transfer_one(struct spi_controller *controller,
  310. struct spi_device *spi,
  311. struct spi_transfer *t)
  312. {
  313. int status;
  314. status = fsl_spi_setup_transfer(spi, t);
  315. if (status < 0)
  316. return status;
  317. if (t->len)
  318. status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma);
  319. if (status > 0)
  320. return -EMSGSIZE;
  321. return status;
  322. }
  323. static int fsl_spi_unprepare_message(struct spi_controller *controller,
  324. struct spi_message *msg)
  325. {
  326. return fsl_spi_setup_transfer(msg->spi, NULL);
  327. }
  328. static int fsl_spi_setup(struct spi_device *spi)
  329. {
  330. struct mpc8xxx_spi *mpc8xxx_spi;
  331. struct fsl_spi_reg __iomem *reg_base;
  332. bool initial_setup = false;
  333. int retval;
  334. u32 hw_mode;
  335. struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
  336. if (!spi->max_speed_hz)
  337. return -EINVAL;
  338. if (!cs) {
  339. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  340. if (!cs)
  341. return -ENOMEM;
  342. spi_set_ctldata(spi, cs);
  343. initial_setup = true;
  344. }
  345. mpc8xxx_spi = spi_master_get_devdata(spi->master);
  346. reg_base = mpc8xxx_spi->reg_base;
  347. hw_mode = cs->hw_mode; /* Save original settings */
  348. cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
  349. /* mask out bits we are going to set */
  350. cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
  351. | SPMODE_REV | SPMODE_LOOP);
  352. if (spi->mode & SPI_CPHA)
  353. cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
  354. if (spi->mode & SPI_CPOL)
  355. cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
  356. if (!(spi->mode & SPI_LSB_FIRST))
  357. cs->hw_mode |= SPMODE_REV;
  358. if (spi->mode & SPI_LOOP)
  359. cs->hw_mode |= SPMODE_LOOP;
  360. retval = fsl_spi_setup_transfer(spi, NULL);
  361. if (retval < 0) {
  362. cs->hw_mode = hw_mode; /* Restore settings */
  363. if (initial_setup)
  364. kfree(cs);
  365. return retval;
  366. }
  367. return 0;
  368. }
  369. static void fsl_spi_cleanup(struct spi_device *spi)
  370. {
  371. struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
  372. kfree(cs);
  373. spi_set_ctldata(spi, NULL);
  374. }
  375. static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
  376. {
  377. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  378. /* We need handle RX first */
  379. if (events & SPIE_NE) {
  380. u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
  381. if (mspi->rx)
  382. mspi->get_rx(rx_data, mspi);
  383. }
  384. if ((events & SPIE_NF) == 0)
  385. /* spin until TX is done */
  386. while (((events =
  387. mpc8xxx_spi_read_reg(&reg_base->event)) &
  388. SPIE_NF) == 0)
  389. cpu_relax();
  390. /* Clear the events */
  391. mpc8xxx_spi_write_reg(&reg_base->event, events);
  392. mspi->count -= 1;
  393. if (mspi->count) {
  394. u32 word = mspi->get_tx(mspi);
  395. mpc8xxx_spi_write_reg(&reg_base->transmit, word);
  396. } else {
  397. complete(&mspi->done);
  398. }
  399. }
  400. static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
  401. {
  402. struct mpc8xxx_spi *mspi = context_data;
  403. irqreturn_t ret = IRQ_NONE;
  404. u32 events;
  405. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  406. /* Get interrupt events(tx/rx) */
  407. events = mpc8xxx_spi_read_reg(&reg_base->event);
  408. if (events)
  409. ret = IRQ_HANDLED;
  410. dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
  411. if (mspi->flags & SPI_CPM_MODE)
  412. fsl_spi_cpm_irq(mspi, events);
  413. else
  414. fsl_spi_cpu_irq(mspi, events);
  415. return ret;
  416. }
  417. static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
  418. {
  419. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
  420. struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
  421. u32 slvsel;
  422. u16 cs = spi->chip_select;
  423. if (cs < mpc8xxx_spi->native_chipselects) {
  424. slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
  425. slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
  426. mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
  427. }
  428. }
  429. static void fsl_spi_grlib_probe(struct device *dev)
  430. {
  431. struct spi_master *master = dev_get_drvdata(dev);
  432. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  433. struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
  434. int mbits;
  435. u32 capabilities;
  436. capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
  437. mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
  438. mbits = SPCAP_MAXWLEN(capabilities);
  439. if (mbits)
  440. mpc8xxx_spi->max_bits_per_word = mbits + 1;
  441. mpc8xxx_spi->native_chipselects = 0;
  442. if (SPCAP_SSEN(capabilities)) {
  443. mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
  444. mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
  445. }
  446. master->num_chipselect = mpc8xxx_spi->native_chipselects;
  447. master->set_cs = fsl_spi_grlib_cs_control;
  448. }
  449. static void fsl_spi_cs_control(struct spi_device *spi, bool on)
  450. {
  451. struct device *dev = spi->dev.parent->parent;
  452. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  453. struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
  454. if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
  455. return;
  456. iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
  457. }
  458. static struct spi_master *fsl_spi_probe(struct device *dev,
  459. struct resource *mem, unsigned int irq)
  460. {
  461. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  462. struct spi_master *master;
  463. struct mpc8xxx_spi *mpc8xxx_spi;
  464. struct fsl_spi_reg __iomem *reg_base;
  465. u32 regval;
  466. int ret = 0;
  467. master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
  468. if (master == NULL) {
  469. ret = -ENOMEM;
  470. goto err;
  471. }
  472. dev_set_drvdata(dev, master);
  473. mpc8xxx_spi_probe(dev, mem, irq);
  474. master->setup = fsl_spi_setup;
  475. master->cleanup = fsl_spi_cleanup;
  476. master->prepare_message = fsl_spi_prepare_message;
  477. master->transfer_one = fsl_spi_transfer_one;
  478. master->unprepare_message = fsl_spi_unprepare_message;
  479. master->use_gpio_descriptors = true;
  480. master->set_cs = fsl_spi_cs_control;
  481. mpc8xxx_spi = spi_master_get_devdata(master);
  482. mpc8xxx_spi->max_bits_per_word = 32;
  483. mpc8xxx_spi->type = fsl_spi_get_type(dev);
  484. ret = fsl_spi_cpm_init(mpc8xxx_spi);
  485. if (ret)
  486. goto err_cpm_init;
  487. mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
  488. if (IS_ERR(mpc8xxx_spi->reg_base)) {
  489. ret = PTR_ERR(mpc8xxx_spi->reg_base);
  490. goto err_probe;
  491. }
  492. if (mpc8xxx_spi->type == TYPE_GRLIB)
  493. fsl_spi_grlib_probe(dev);
  494. if (mpc8xxx_spi->flags & SPI_CPM_MODE)
  495. master->bits_per_word_mask =
  496. (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));
  497. else
  498. master->bits_per_word_mask =
  499. (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));
  500. master->bits_per_word_mask &=
  501. SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
  502. if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
  503. mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
  504. if (mpc8xxx_spi->set_shifts)
  505. /* 8 bits per word and MSB first */
  506. mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
  507. &mpc8xxx_spi->tx_shift, 8, 1);
  508. /* Register for SPI Interrupt */
  509. ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
  510. 0, "fsl_spi", mpc8xxx_spi);
  511. if (ret != 0)
  512. goto err_probe;
  513. reg_base = mpc8xxx_spi->reg_base;
  514. /* SPI controller initializations */
  515. mpc8xxx_spi_write_reg(&reg_base->mode, 0);
  516. mpc8xxx_spi_write_reg(&reg_base->mask, 0);
  517. mpc8xxx_spi_write_reg(&reg_base->command, 0);
  518. mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
  519. /* Enable SPI interface */
  520. regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
  521. if (mpc8xxx_spi->max_bits_per_word < 8) {
  522. regval &= ~SPMODE_LEN(0xF);
  523. regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
  524. }
  525. if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
  526. regval |= SPMODE_OP;
  527. mpc8xxx_spi_write_reg(&reg_base->mode, regval);
  528. ret = devm_spi_register_master(dev, master);
  529. if (ret < 0)
  530. goto err_probe;
  531. dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
  532. mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
  533. return master;
  534. err_probe:
  535. fsl_spi_cpm_free(mpc8xxx_spi);
  536. err_cpm_init:
  537. spi_master_put(master);
  538. err:
  539. return ERR_PTR(ret);
  540. }
  541. static int of_fsl_spi_probe(struct platform_device *ofdev)
  542. {
  543. struct device *dev = &ofdev->dev;
  544. struct device_node *np = ofdev->dev.of_node;
  545. struct spi_master *master;
  546. struct resource mem;
  547. int irq, type;
  548. int ret;
  549. bool spisel_boot = false;
  550. #if IS_ENABLED(CONFIG_FSL_SOC)
  551. struct mpc8xxx_spi_probe_info *pinfo = NULL;
  552. #endif
  553. ret = of_mpc8xxx_spi_probe(ofdev);
  554. if (ret)
  555. return ret;
  556. type = fsl_spi_get_type(&ofdev->dev);
  557. if (type == TYPE_FSL) {
  558. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  559. #if IS_ENABLED(CONFIG_FSL_SOC)
  560. pinfo = to_of_pinfo(pdata);
  561. spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
  562. if (spisel_boot) {
  563. pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
  564. if (!pinfo->immr_spi_cs)
  565. return -ENOMEM;
  566. }
  567. #endif
  568. /*
  569. * Handle the case where we have one hardwired (always selected)
  570. * device on the first "chipselect". Else we let the core code
  571. * handle any GPIOs or native chip selects and assign the
  572. * appropriate callback for dealing with the CS lines. This isn't
  573. * supported on the GRLIB variant.
  574. */
  575. ret = gpiod_count(dev, "cs");
  576. if (ret < 0)
  577. ret = 0;
  578. if (ret == 0 && !spisel_boot)
  579. pdata->max_chipselect = 1;
  580. else
  581. pdata->max_chipselect = ret + spisel_boot;
  582. }
  583. ret = of_address_to_resource(np, 0, &mem);
  584. if (ret)
  585. goto unmap_out;
  586. irq = platform_get_irq(ofdev, 0);
  587. if (irq < 0) {
  588. ret = irq;
  589. goto unmap_out;
  590. }
  591. master = fsl_spi_probe(dev, &mem, irq);
  592. return PTR_ERR_OR_ZERO(master);
  593. unmap_out:
  594. #if IS_ENABLED(CONFIG_FSL_SOC)
  595. if (spisel_boot)
  596. iounmap(pinfo->immr_spi_cs);
  597. #endif
  598. return ret;
  599. }
  600. static int of_fsl_spi_remove(struct platform_device *ofdev)
  601. {
  602. struct spi_master *master = platform_get_drvdata(ofdev);
  603. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  604. fsl_spi_cpm_free(mpc8xxx_spi);
  605. return 0;
  606. }
  607. static struct platform_driver of_fsl_spi_driver = {
  608. .driver = {
  609. .name = "fsl_spi",
  610. .of_match_table = of_fsl_spi_match,
  611. },
  612. .probe = of_fsl_spi_probe,
  613. .remove = of_fsl_spi_remove,
  614. };
  615. #ifdef CONFIG_MPC832x_RDB
  616. /*
  617. * XXX XXX XXX
  618. * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
  619. * only. The driver should go away soon, since newer MPC8323E-RDB's device
  620. * tree can work with OpenFirmware driver. But for now we support old trees
  621. * as well.
  622. */
  623. static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
  624. {
  625. struct resource *mem;
  626. int irq;
  627. struct spi_master *master;
  628. if (!dev_get_platdata(&pdev->dev))
  629. return -EINVAL;
  630. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  631. if (!mem)
  632. return -EINVAL;
  633. irq = platform_get_irq(pdev, 0);
  634. if (irq <= 0)
  635. return -EINVAL;
  636. master = fsl_spi_probe(&pdev->dev, mem, irq);
  637. return PTR_ERR_OR_ZERO(master);
  638. }
  639. static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
  640. {
  641. struct spi_master *master = platform_get_drvdata(pdev);
  642. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  643. fsl_spi_cpm_free(mpc8xxx_spi);
  644. return 0;
  645. }
  646. MODULE_ALIAS("platform:mpc8xxx_spi");
  647. static struct platform_driver mpc8xxx_spi_driver = {
  648. .probe = plat_mpc8xxx_spi_probe,
  649. .remove = plat_mpc8xxx_spi_remove,
  650. .driver = {
  651. .name = "mpc8xxx_spi",
  652. },
  653. };
  654. static bool legacy_driver_failed;
  655. static void __init legacy_driver_register(void)
  656. {
  657. legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
  658. }
  659. static void __exit legacy_driver_unregister(void)
  660. {
  661. if (legacy_driver_failed)
  662. return;
  663. platform_driver_unregister(&mpc8xxx_spi_driver);
  664. }
  665. #else
  666. static void __init legacy_driver_register(void) {}
  667. static void __exit legacy_driver_unregister(void) {}
  668. #endif /* CONFIG_MPC832x_RDB */
  669. static int __init fsl_spi_init(void)
  670. {
  671. legacy_driver_register();
  672. return platform_driver_register(&of_fsl_spi_driver);
  673. }
  674. module_init(fsl_spi_init);
  675. static void __exit fsl_spi_exit(void)
  676. {
  677. platform_driver_unregister(&of_fsl_spi_driver);
  678. legacy_driver_unregister();
  679. }
  680. module_exit(fsl_spi_exit);
  681. MODULE_AUTHOR("Kumar Gala");
  682. MODULE_DESCRIPTION("Simple Freescale SPI Driver");
  683. MODULE_LICENSE("GPL");