spi-dw-mmio.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Memory-mapped interface driver for DW SPI Core
  4. *
  5. * Copyright (c) 2010, Octasic semiconductor.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/slab.h>
  12. #include <linux/spi/spi.h>
  13. #include <linux/scatterlist.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/acpi.h>
  19. #include <linux/property.h>
  20. #include <linux/regmap.h>
  21. #include <linux/reset.h>
  22. #include "spi-dw.h"
  23. #define DRIVER_NAME "dw_spi_mmio"
  24. struct dw_spi_mmio {
  25. struct dw_spi dws;
  26. struct clk *clk;
  27. struct clk *pclk;
  28. void *priv;
  29. struct reset_control *rstc;
  30. };
  31. #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
  32. #define OCELOT_IF_SI_OWNER_OFFSET 4
  33. #define JAGUAR2_IF_SI_OWNER_OFFSET 6
  34. #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
  35. #define MSCC_IF_SI_OWNER_SISL 0
  36. #define MSCC_IF_SI_OWNER_SIBM 1
  37. #define MSCC_IF_SI_OWNER_SIMC 2
  38. #define MSCC_SPI_MST_SW_MODE 0x14
  39. #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
  40. #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
  41. #define SPARX5_FORCE_ENA 0xa4
  42. #define SPARX5_FORCE_VAL 0xa8
  43. struct dw_spi_mscc {
  44. struct regmap *syscon;
  45. void __iomem *spi_mst; /* Not sparx5 */
  46. };
  47. /*
  48. * The Designware SPI controller (referred to as master in the documentation)
  49. * automatically deasserts chip select when the tx fifo is empty. The chip
  50. * selects then needs to be either driven as GPIOs or, for the first 4 using
  51. * the SPI boot controller registers. the final chip select is an OR gate
  52. * between the Designware SPI controller and the SPI boot controller.
  53. */
  54. static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
  55. {
  56. struct dw_spi *dws = spi_master_get_devdata(spi->master);
  57. struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
  58. struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
  59. u32 cs = spi->chip_select;
  60. if (cs < 4) {
  61. u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
  62. if (!enable)
  63. sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
  64. writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
  65. }
  66. dw_spi_set_cs(spi, enable);
  67. }
  68. static int dw_spi_mscc_init(struct platform_device *pdev,
  69. struct dw_spi_mmio *dwsmmio,
  70. const char *cpu_syscon, u32 if_si_owner_offset)
  71. {
  72. struct dw_spi_mscc *dwsmscc;
  73. dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
  74. if (!dwsmscc)
  75. return -ENOMEM;
  76. dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
  77. if (IS_ERR(dwsmscc->spi_mst)) {
  78. dev_err(&pdev->dev, "SPI_MST region map failed\n");
  79. return PTR_ERR(dwsmscc->spi_mst);
  80. }
  81. dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
  82. if (IS_ERR(dwsmscc->syscon))
  83. return PTR_ERR(dwsmscc->syscon);
  84. /* Deassert all CS */
  85. writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
  86. /* Select the owner of the SI interface */
  87. regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
  88. MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
  89. MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
  90. dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
  91. dwsmmio->priv = dwsmscc;
  92. return 0;
  93. }
  94. static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
  95. struct dw_spi_mmio *dwsmmio)
  96. {
  97. return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
  98. OCELOT_IF_SI_OWNER_OFFSET);
  99. }
  100. static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
  101. struct dw_spi_mmio *dwsmmio)
  102. {
  103. return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
  104. JAGUAR2_IF_SI_OWNER_OFFSET);
  105. }
  106. /*
  107. * The Designware SPI controller (referred to as master in the
  108. * documentation) automatically deasserts chip select when the tx fifo
  109. * is empty. The chip selects then needs to be driven by a CS override
  110. * register. enable is an active low signal.
  111. */
  112. static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
  113. {
  114. struct dw_spi *dws = spi_master_get_devdata(spi->master);
  115. struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
  116. struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
  117. u8 cs = spi->chip_select;
  118. if (!enable) {
  119. /* CS override drive enable */
  120. regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
  121. /* Now set CSx enabled */
  122. regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
  123. /* Allow settle */
  124. usleep_range(1, 5);
  125. } else {
  126. /* CS value */
  127. regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
  128. /* Allow settle */
  129. usleep_range(1, 5);
  130. /* CS override drive disable */
  131. regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
  132. }
  133. dw_spi_set_cs(spi, enable);
  134. }
  135. static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
  136. struct dw_spi_mmio *dwsmmio)
  137. {
  138. const char *syscon_name = "microchip,sparx5-cpu-syscon";
  139. struct device *dev = &pdev->dev;
  140. struct dw_spi_mscc *dwsmscc;
  141. if (!IS_ENABLED(CONFIG_SPI_MUX)) {
  142. dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
  143. return -EOPNOTSUPP;
  144. }
  145. dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
  146. if (!dwsmscc)
  147. return -ENOMEM;
  148. dwsmscc->syscon =
  149. syscon_regmap_lookup_by_compatible(syscon_name);
  150. if (IS_ERR(dwsmscc->syscon)) {
  151. dev_err(dev, "No syscon map %s\n", syscon_name);
  152. return PTR_ERR(dwsmscc->syscon);
  153. }
  154. dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
  155. dwsmmio->priv = dwsmscc;
  156. return 0;
  157. }
  158. static int dw_spi_alpine_init(struct platform_device *pdev,
  159. struct dw_spi_mmio *dwsmmio)
  160. {
  161. dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;
  162. return 0;
  163. }
  164. static int dw_spi_pssi_init(struct platform_device *pdev,
  165. struct dw_spi_mmio *dwsmmio)
  166. {
  167. dw_spi_dma_setup_generic(&dwsmmio->dws);
  168. return 0;
  169. }
  170. static int dw_spi_hssi_init(struct platform_device *pdev,
  171. struct dw_spi_mmio *dwsmmio)
  172. {
  173. dwsmmio->dws.ip = DW_HSSI_ID;
  174. dw_spi_dma_setup_generic(&dwsmmio->dws);
  175. return 0;
  176. }
  177. static int dw_spi_intel_init(struct platform_device *pdev,
  178. struct dw_spi_mmio *dwsmmio)
  179. {
  180. dwsmmio->dws.ip = DW_HSSI_ID;
  181. return 0;
  182. }
  183. /*
  184. * DMA-based mem ops are not configured for this device and are not tested.
  185. */
  186. static int dw_spi_mountevans_imc_init(struct platform_device *pdev,
  187. struct dw_spi_mmio *dwsmmio)
  188. {
  189. /*
  190. * The Intel Mount Evans SoC's Integrated Management Complex DW
  191. * apb_ssi_v4.02a controller has an errata where a full TX FIFO can
  192. * result in data corruption. The suggested workaround is to never
  193. * completely fill the FIFO. The TX FIFO has a size of 32 so the
  194. * fifo_len is set to 31.
  195. */
  196. dwsmmio->dws.fifo_len = 31;
  197. return 0;
  198. }
  199. static int dw_spi_canaan_k210_init(struct platform_device *pdev,
  200. struct dw_spi_mmio *dwsmmio)
  201. {
  202. /*
  203. * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
  204. * documented to have a 32 word deep TX and RX FIFO, which
  205. * spi_hw_init() detects. However, when the RX FIFO is filled up to
  206. * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
  207. * problem by force setting fifo_len to 31.
  208. */
  209. dwsmmio->dws.fifo_len = 31;
  210. return 0;
  211. }
  212. static int dw_spi_mmio_probe(struct platform_device *pdev)
  213. {
  214. int (*init_func)(struct platform_device *pdev,
  215. struct dw_spi_mmio *dwsmmio);
  216. struct dw_spi_mmio *dwsmmio;
  217. struct resource *mem;
  218. struct dw_spi *dws;
  219. int ret;
  220. int num_cs;
  221. dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
  222. GFP_KERNEL);
  223. if (!dwsmmio)
  224. return -ENOMEM;
  225. dws = &dwsmmio->dws;
  226. /* Get basic io resource and map it */
  227. dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
  228. if (IS_ERR(dws->regs))
  229. return PTR_ERR(dws->regs);
  230. dws->paddr = mem->start;
  231. dws->irq = platform_get_irq(pdev, 0);
  232. if (dws->irq < 0)
  233. return dws->irq; /* -ENXIO */
  234. dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
  235. if (IS_ERR(dwsmmio->clk))
  236. return PTR_ERR(dwsmmio->clk);
  237. ret = clk_prepare_enable(dwsmmio->clk);
  238. if (ret)
  239. return ret;
  240. /* Optional clock needed to access the registers */
  241. dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
  242. if (IS_ERR(dwsmmio->pclk)) {
  243. ret = PTR_ERR(dwsmmio->pclk);
  244. goto out_clk;
  245. }
  246. ret = clk_prepare_enable(dwsmmio->pclk);
  247. if (ret)
  248. goto out_clk;
  249. /* find an optional reset controller */
  250. dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
  251. if (IS_ERR(dwsmmio->rstc)) {
  252. ret = PTR_ERR(dwsmmio->rstc);
  253. goto out_clk;
  254. }
  255. reset_control_deassert(dwsmmio->rstc);
  256. dws->bus_num = pdev->id;
  257. dws->max_freq = clk_get_rate(dwsmmio->clk);
  258. device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
  259. num_cs = 4;
  260. device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
  261. dws->num_cs = num_cs;
  262. init_func = device_get_match_data(&pdev->dev);
  263. if (init_func) {
  264. ret = init_func(pdev, dwsmmio);
  265. if (ret)
  266. goto out;
  267. }
  268. pm_runtime_enable(&pdev->dev);
  269. ret = dw_spi_add_host(&pdev->dev, dws);
  270. if (ret)
  271. goto out;
  272. platform_set_drvdata(pdev, dwsmmio);
  273. return 0;
  274. out:
  275. pm_runtime_disable(&pdev->dev);
  276. clk_disable_unprepare(dwsmmio->pclk);
  277. out_clk:
  278. clk_disable_unprepare(dwsmmio->clk);
  279. reset_control_assert(dwsmmio->rstc);
  280. return ret;
  281. }
  282. static int dw_spi_mmio_remove(struct platform_device *pdev)
  283. {
  284. struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
  285. dw_spi_remove_host(&dwsmmio->dws);
  286. pm_runtime_disable(&pdev->dev);
  287. clk_disable_unprepare(dwsmmio->pclk);
  288. clk_disable_unprepare(dwsmmio->clk);
  289. reset_control_assert(dwsmmio->rstc);
  290. return 0;
  291. }
  292. static const struct of_device_id dw_spi_mmio_of_match[] = {
  293. { .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
  294. { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
  295. { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
  296. { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
  297. { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
  298. { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
  299. { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
  300. { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
  301. {
  302. .compatible = "intel,mountevans-imc-ssi",
  303. .data = dw_spi_mountevans_imc_init,
  304. },
  305. { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
  306. { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
  307. { /* end of table */}
  308. };
  309. MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
  310. #ifdef CONFIG_ACPI
  311. static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
  312. {"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
  313. {},
  314. };
  315. MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
  316. #endif
  317. static struct platform_driver dw_spi_mmio_driver = {
  318. .probe = dw_spi_mmio_probe,
  319. .remove = dw_spi_mmio_remove,
  320. .driver = {
  321. .name = DRIVER_NAME,
  322. .of_match_table = dw_spi_mmio_of_match,
  323. .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
  324. },
  325. };
  326. module_platform_driver(dw_spi_mmio_driver);
  327. MODULE_AUTHOR("Jean-Hugues Deschenes <[email protected]>");
  328. MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
  329. MODULE_LICENSE("GPL v2");
  330. MODULE_IMPORT_NS(SPI_DW_CORE);