spi-bcm2835aux.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Broadcom BCM2835 auxiliary SPI Controllers
  4. *
  5. * the driver does not rely on the native chipselects at all
  6. * but only uses the gpio type chipselects
  7. *
  8. * Based on: spi-bcm2835.c
  9. *
  10. * Copyright (C) 2015 Martin Sperl
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/completion.h>
  14. #include <linux/debugfs.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_device.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/regmap.h>
  26. #include <linux/spi/spi.h>
  27. #include <linux/spinlock.h>
  28. /* define polling limits */
  29. static unsigned int polling_limit_us = 30;
  30. module_param(polling_limit_us, uint, 0664);
  31. MODULE_PARM_DESC(polling_limit_us,
  32. "time in us to run a transfer in polling mode - if zero no polling is used\n");
  33. /*
  34. * spi register defines
  35. *
  36. * note there is garbage in the "official" documentation,
  37. * so some data is taken from the file:
  38. * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
  39. * inside of:
  40. * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
  41. */
  42. /* SPI register offsets */
  43. #define BCM2835_AUX_SPI_CNTL0 0x00
  44. #define BCM2835_AUX_SPI_CNTL1 0x04
  45. #define BCM2835_AUX_SPI_STAT 0x08
  46. #define BCM2835_AUX_SPI_PEEK 0x0C
  47. #define BCM2835_AUX_SPI_IO 0x20
  48. #define BCM2835_AUX_SPI_TXHOLD 0x30
  49. /* Bitfields in CNTL0 */
  50. #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
  51. #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
  52. #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
  53. #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
  54. #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
  55. #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
  56. #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
  57. #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
  58. #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
  59. #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
  60. #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
  61. #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100
  62. #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
  63. #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
  64. #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
  65. /* Bitfields in CNTL1 */
  66. #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
  67. #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080
  68. #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040
  69. #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
  70. #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
  71. /* Bitfields in STAT */
  72. #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
  73. #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
  74. #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
  75. #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
  76. #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
  77. #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
  78. #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
  79. #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
  80. struct bcm2835aux_spi {
  81. void __iomem *regs;
  82. struct clk *clk;
  83. int irq;
  84. u32 cntl[2];
  85. const u8 *tx_buf;
  86. u8 *rx_buf;
  87. int tx_len;
  88. int rx_len;
  89. int pending;
  90. u64 count_transfer_polling;
  91. u64 count_transfer_irq;
  92. u64 count_transfer_irq_after_poll;
  93. struct dentry *debugfs_dir;
  94. };
  95. #if defined(CONFIG_DEBUG_FS)
  96. static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
  97. const char *dname)
  98. {
  99. char name[64];
  100. struct dentry *dir;
  101. /* get full name */
  102. snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
  103. /* the base directory */
  104. dir = debugfs_create_dir(name, NULL);
  105. bs->debugfs_dir = dir;
  106. /* the counters */
  107. debugfs_create_u64("count_transfer_polling", 0444, dir,
  108. &bs->count_transfer_polling);
  109. debugfs_create_u64("count_transfer_irq", 0444, dir,
  110. &bs->count_transfer_irq);
  111. debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
  112. &bs->count_transfer_irq_after_poll);
  113. }
  114. static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
  115. {
  116. debugfs_remove_recursive(bs->debugfs_dir);
  117. bs->debugfs_dir = NULL;
  118. }
  119. #else
  120. static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
  121. const char *dname)
  122. {
  123. }
  124. static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
  125. {
  126. }
  127. #endif /* CONFIG_DEBUG_FS */
  128. static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned int reg)
  129. {
  130. return readl(bs->regs + reg);
  131. }
  132. static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned int reg,
  133. u32 val)
  134. {
  135. writel(val, bs->regs + reg);
  136. }
  137. static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
  138. {
  139. u32 data;
  140. int count = min(bs->rx_len, 3);
  141. data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
  142. if (bs->rx_buf) {
  143. switch (count) {
  144. case 3:
  145. *bs->rx_buf++ = (data >> 16) & 0xff;
  146. fallthrough;
  147. case 2:
  148. *bs->rx_buf++ = (data >> 8) & 0xff;
  149. fallthrough;
  150. case 1:
  151. *bs->rx_buf++ = (data >> 0) & 0xff;
  152. /* fallthrough - no default */
  153. }
  154. }
  155. bs->rx_len -= count;
  156. bs->pending -= count;
  157. }
  158. static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
  159. {
  160. u32 data;
  161. u8 byte;
  162. int count;
  163. int i;
  164. /* gather up to 3 bytes to write to the FIFO */
  165. count = min(bs->tx_len, 3);
  166. data = 0;
  167. for (i = 0; i < count; i++) {
  168. byte = bs->tx_buf ? *bs->tx_buf++ : 0;
  169. data |= byte << (8 * (2 - i));
  170. }
  171. /* and set the variable bit-length */
  172. data |= (count * 8) << 24;
  173. /* and decrement length */
  174. bs->tx_len -= count;
  175. bs->pending += count;
  176. /* write to the correct TX-register */
  177. if (bs->tx_len)
  178. bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
  179. else
  180. bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
  181. }
  182. static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
  183. {
  184. /* disable spi clearing fifo and interrupts */
  185. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
  186. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
  187. BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
  188. }
  189. static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
  190. {
  191. u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
  192. /* check if we have data to read */
  193. for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
  194. stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
  195. bcm2835aux_rd_fifo(bs);
  196. /* check if we have data to write */
  197. while (bs->tx_len &&
  198. (bs->pending < 12) &&
  199. (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
  200. BCM2835_AUX_SPI_STAT_TX_FULL))) {
  201. bcm2835aux_wr_fifo(bs);
  202. }
  203. }
  204. static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
  205. {
  206. struct spi_master *master = dev_id;
  207. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  208. /* IRQ may be shared, so return if our interrupts are disabled */
  209. if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
  210. (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
  211. return IRQ_NONE;
  212. /* do common fifo handling */
  213. bcm2835aux_spi_transfer_helper(bs);
  214. if (!bs->tx_len) {
  215. /* disable tx fifo empty interrupt */
  216. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
  217. BCM2835_AUX_SPI_CNTL1_IDLE);
  218. }
  219. /* and if rx_len is 0 then disable interrupts and wake up completion */
  220. if (!bs->rx_len) {
  221. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
  222. spi_finalize_current_transfer(master);
  223. }
  224. return IRQ_HANDLED;
  225. }
  226. static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
  227. struct spi_device *spi,
  228. struct spi_transfer *tfr)
  229. {
  230. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  231. /* enable interrupts */
  232. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
  233. BCM2835_AUX_SPI_CNTL1_TXEMPTY |
  234. BCM2835_AUX_SPI_CNTL1_IDLE);
  235. /* and wait for finish... */
  236. return 1;
  237. }
  238. static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
  239. struct spi_device *spi,
  240. struct spi_transfer *tfr)
  241. {
  242. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  243. /* update statistics */
  244. bs->count_transfer_irq++;
  245. /* fill in registers and fifos before enabling interrupts */
  246. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
  247. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
  248. /* fill in tx fifo with data before enabling interrupts */
  249. while ((bs->tx_len) &&
  250. (bs->pending < 12) &&
  251. (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
  252. BCM2835_AUX_SPI_STAT_TX_FULL))) {
  253. bcm2835aux_wr_fifo(bs);
  254. }
  255. /* now run the interrupt mode */
  256. return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
  257. }
  258. static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
  259. struct spi_device *spi,
  260. struct spi_transfer *tfr)
  261. {
  262. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  263. unsigned long timeout;
  264. /* update statistics */
  265. bs->count_transfer_polling++;
  266. /* configure spi */
  267. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
  268. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
  269. /* set the timeout to at least 2 jiffies */
  270. timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
  271. /* loop until finished the transfer */
  272. while (bs->rx_len) {
  273. /* do common fifo handling */
  274. bcm2835aux_spi_transfer_helper(bs);
  275. /* there is still data pending to read check the timeout */
  276. if (bs->rx_len && time_after(jiffies, timeout)) {
  277. dev_dbg_ratelimited(&spi->dev,
  278. "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
  279. jiffies - timeout,
  280. bs->tx_len, bs->rx_len);
  281. /* forward to interrupt handler */
  282. bs->count_transfer_irq_after_poll++;
  283. return __bcm2835aux_spi_transfer_one_irq(master,
  284. spi, tfr);
  285. }
  286. }
  287. /* and return without waiting for completion */
  288. return 0;
  289. }
  290. static int bcm2835aux_spi_transfer_one(struct spi_master *master,
  291. struct spi_device *spi,
  292. struct spi_transfer *tfr)
  293. {
  294. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  295. unsigned long spi_hz, clk_hz, speed;
  296. unsigned long hz_per_byte, byte_limit;
  297. /* calculate the registers to handle
  298. *
  299. * note that we use the variable data mode, which
  300. * is not optimal for longer transfers as we waste registers
  301. * resulting (potentially) in more interrupts when transferring
  302. * more than 12 bytes
  303. */
  304. /* set clock */
  305. spi_hz = tfr->speed_hz;
  306. clk_hz = clk_get_rate(bs->clk);
  307. if (spi_hz >= clk_hz / 2) {
  308. speed = 0;
  309. } else if (spi_hz) {
  310. speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
  311. if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
  312. speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
  313. } else { /* the slowest we can go */
  314. speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
  315. }
  316. /* mask out old speed from previous spi_transfer */
  317. bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
  318. /* set the new speed */
  319. bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
  320. tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));
  321. /* set transmit buffers and length */
  322. bs->tx_buf = tfr->tx_buf;
  323. bs->rx_buf = tfr->rx_buf;
  324. bs->tx_len = tfr->len;
  325. bs->rx_len = tfr->len;
  326. bs->pending = 0;
  327. /* Calculate the estimated time in us the transfer runs. Note that
  328. * there are 2 idle clocks cycles after each chunk getting
  329. * transferred - in our case the chunk size is 3 bytes, so we
  330. * approximate this by 9 cycles/byte. This is used to find the number
  331. * of Hz per byte per polling limit. E.g., we can transfer 1 byte in
  332. * 30 µs per 300,000 Hz of bus clock.
  333. */
  334. hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
  335. byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
  336. /* run in polling mode for short transfers */
  337. if (tfr->len < byte_limit)
  338. return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
  339. /* run in interrupt mode for all others */
  340. return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
  341. }
  342. static int bcm2835aux_spi_prepare_message(struct spi_master *master,
  343. struct spi_message *msg)
  344. {
  345. struct spi_device *spi = msg->spi;
  346. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  347. bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
  348. BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
  349. BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
  350. bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
  351. /* handle all the modes */
  352. if (spi->mode & SPI_CPOL) {
  353. bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
  354. bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
  355. } else {
  356. bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
  357. }
  358. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
  359. bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
  360. return 0;
  361. }
  362. static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
  363. struct spi_message *msg)
  364. {
  365. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  366. bcm2835aux_spi_reset_hw(bs);
  367. return 0;
  368. }
  369. static void bcm2835aux_spi_handle_err(struct spi_master *master,
  370. struct spi_message *msg)
  371. {
  372. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  373. bcm2835aux_spi_reset_hw(bs);
  374. }
  375. static int bcm2835aux_spi_setup(struct spi_device *spi)
  376. {
  377. /* sanity check for native cs */
  378. if (spi->mode & SPI_NO_CS)
  379. return 0;
  380. if (spi->cs_gpiod)
  381. return 0;
  382. /* for dt-backwards compatibility: only support native on CS0
  383. * known things not supported with broken native CS:
  384. * * multiple chip-selects: cs0-cs2 are all
  385. * simultaniously asserted whenever there is a transfer
  386. * this even includes SPI_NO_CS
  387. * * SPI_CS_HIGH: cs are always asserted low
  388. * * cs_change: cs is deasserted after each spi_transfer
  389. * * cs_delay_usec: cs is always deasserted one SCK cycle
  390. * after the last transfer
  391. * probably more...
  392. */
  393. dev_warn(&spi->dev,
  394. "Native CS is not supported - please configure cs-gpio in device-tree\n");
  395. if (spi->chip_select == 0)
  396. return 0;
  397. dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
  398. return -EINVAL;
  399. }
  400. static int bcm2835aux_spi_probe(struct platform_device *pdev)
  401. {
  402. struct spi_master *master;
  403. struct bcm2835aux_spi *bs;
  404. unsigned long clk_hz;
  405. int err;
  406. master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
  407. if (!master)
  408. return -ENOMEM;
  409. platform_set_drvdata(pdev, master);
  410. master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
  411. master->bits_per_word_mask = SPI_BPW_MASK(8);
  412. /* even though the driver never officially supported native CS
  413. * allow a single native CS for legacy DT support purposes when
  414. * no cs-gpio is configured.
  415. * Known limitations for native cs are:
  416. * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
  417. * whenever there is a transfer - this even includes SPI_NO_CS
  418. * * SPI_CS_HIGH: is ignores - cs are always asserted low
  419. * * cs_change: cs is deasserted after each spi_transfer
  420. * * cs_delay_usec: cs is always deasserted one SCK cycle after
  421. * a spi_transfer
  422. */
  423. master->num_chipselect = 1;
  424. master->setup = bcm2835aux_spi_setup;
  425. master->transfer_one = bcm2835aux_spi_transfer_one;
  426. master->handle_err = bcm2835aux_spi_handle_err;
  427. master->prepare_message = bcm2835aux_spi_prepare_message;
  428. master->unprepare_message = bcm2835aux_spi_unprepare_message;
  429. master->dev.of_node = pdev->dev.of_node;
  430. master->use_gpio_descriptors = true;
  431. bs = spi_master_get_devdata(master);
  432. /* the main area */
  433. bs->regs = devm_platform_ioremap_resource(pdev, 0);
  434. if (IS_ERR(bs->regs))
  435. return PTR_ERR(bs->regs);
  436. bs->clk = devm_clk_get(&pdev->dev, NULL);
  437. if (IS_ERR(bs->clk)) {
  438. err = PTR_ERR(bs->clk);
  439. dev_err(&pdev->dev, "could not get clk: %d\n", err);
  440. return err;
  441. }
  442. bs->irq = platform_get_irq(pdev, 0);
  443. if (bs->irq <= 0)
  444. return bs->irq ? bs->irq : -ENODEV;
  445. /* this also enables the HW block */
  446. err = clk_prepare_enable(bs->clk);
  447. if (err) {
  448. dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
  449. return err;
  450. }
  451. /* just checking if the clock returns a sane value */
  452. clk_hz = clk_get_rate(bs->clk);
  453. if (!clk_hz) {
  454. dev_err(&pdev->dev, "clock returns 0 Hz\n");
  455. err = -ENODEV;
  456. goto out_clk_disable;
  457. }
  458. /* reset SPI-HW block */
  459. bcm2835aux_spi_reset_hw(bs);
  460. err = devm_request_irq(&pdev->dev, bs->irq,
  461. bcm2835aux_spi_interrupt,
  462. IRQF_SHARED,
  463. dev_name(&pdev->dev), master);
  464. if (err) {
  465. dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
  466. goto out_clk_disable;
  467. }
  468. err = spi_register_master(master);
  469. if (err) {
  470. dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
  471. goto out_clk_disable;
  472. }
  473. bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
  474. return 0;
  475. out_clk_disable:
  476. clk_disable_unprepare(bs->clk);
  477. return err;
  478. }
  479. static int bcm2835aux_spi_remove(struct platform_device *pdev)
  480. {
  481. struct spi_master *master = platform_get_drvdata(pdev);
  482. struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
  483. bcm2835aux_debugfs_remove(bs);
  484. spi_unregister_master(master);
  485. bcm2835aux_spi_reset_hw(bs);
  486. /* disable the HW block by releasing the clock */
  487. clk_disable_unprepare(bs->clk);
  488. return 0;
  489. }
  490. static const struct of_device_id bcm2835aux_spi_match[] = {
  491. { .compatible = "brcm,bcm2835-aux-spi", },
  492. {}
  493. };
  494. MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
  495. static struct platform_driver bcm2835aux_spi_driver = {
  496. .driver = {
  497. .name = "spi-bcm2835aux",
  498. .of_match_table = bcm2835aux_spi_match,
  499. },
  500. .probe = bcm2835aux_spi_probe,
  501. .remove = bcm2835aux_spi_remove,
  502. };
  503. module_platform_driver(bcm2835aux_spi_driver);
  504. MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
  505. MODULE_AUTHOR("Martin Sperl <[email protected]>");
  506. MODULE_LICENSE("GPL");