spi-altera-dfl.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // DFL bus driver for Altera SPI Master
  4. //
  5. // Copyright (C) 2020 Intel Corporation, Inc.
  6. //
  7. // Authors:
  8. // Matthew Gerlach <[email protected]>
  9. //
  10. #include <linux/types.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/stddef.h>
  14. #include <linux/errno.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <linux/bitfield.h>
  18. #include <linux/io-64-nonatomic-lo-hi.h>
  19. #include <linux/regmap.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/spi/altera.h>
  22. #include <linux/dfl.h>
  23. #define FME_FEATURE_ID_MAX10_SPI 0xe
  24. #define FME_FEATURE_REV_MAX10_SPI_N5010 0x1
  25. #define SPI_CORE_PARAMETER 0x8
  26. #define SHIFT_MODE BIT_ULL(1)
  27. #define SHIFT_MODE_MSB 0
  28. #define SHIFT_MODE_LSB 1
  29. #define DATA_WIDTH GENMASK_ULL(7, 2)
  30. #define NUM_CHIPSELECT GENMASK_ULL(13, 8)
  31. #define CLK_POLARITY BIT_ULL(14)
  32. #define CLK_PHASE BIT_ULL(15)
  33. #define PERIPHERAL_ID GENMASK_ULL(47, 32)
  34. #define SPI_CLK GENMASK_ULL(31, 22)
  35. #define SPI_INDIRECT_ACC_OFST 0x10
  36. #define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
  37. #define INDIRECT_WR BIT_ULL(8)
  38. #define INDIRECT_RD BIT_ULL(9)
  39. #define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
  40. #define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
  41. #define INDIRECT_DEBUG BIT_ULL(32)
  42. #define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
  43. #define INDIRECT_TIMEOUT 10000
  44. static int indirect_bus_reg_read(void *context, unsigned int reg,
  45. unsigned int *val)
  46. {
  47. void __iomem *base = context;
  48. int loops;
  49. u64 v;
  50. writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
  51. loops = 0;
  52. while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
  53. (loops++ < INDIRECT_TIMEOUT))
  54. cpu_relax();
  55. if (loops >= INDIRECT_TIMEOUT) {
  56. pr_err("%s timed out %d\n", __func__, loops);
  57. return -ETIME;
  58. }
  59. v = readq(base + INDIRECT_RD_DATA);
  60. *val = v & INDIRECT_DATA_MASK;
  61. return 0;
  62. }
  63. static int indirect_bus_reg_write(void *context, unsigned int reg,
  64. unsigned int val)
  65. {
  66. void __iomem *base = context;
  67. int loops;
  68. writeq(val, base + INDIRECT_WR_DATA);
  69. writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
  70. loops = 0;
  71. while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
  72. (loops++ < INDIRECT_TIMEOUT))
  73. cpu_relax();
  74. if (loops >= INDIRECT_TIMEOUT) {
  75. pr_err("%s timed out %d\n", __func__, loops);
  76. return -ETIME;
  77. }
  78. return 0;
  79. }
  80. static const struct regmap_config indirect_regbus_cfg = {
  81. .reg_bits = 32,
  82. .reg_stride = 4,
  83. .val_bits = 32,
  84. .fast_io = true,
  85. .max_register = 24,
  86. .reg_write = indirect_bus_reg_write,
  87. .reg_read = indirect_bus_reg_read,
  88. };
  89. static void config_spi_master(void __iomem *base, struct spi_master *master)
  90. {
  91. u64 v;
  92. v = readq(base + SPI_CORE_PARAMETER);
  93. master->mode_bits = SPI_CS_HIGH;
  94. if (FIELD_GET(CLK_POLARITY, v))
  95. master->mode_bits |= SPI_CPOL;
  96. if (FIELD_GET(CLK_PHASE, v))
  97. master->mode_bits |= SPI_CPHA;
  98. master->num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
  99. master->bits_per_word_mask =
  100. SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
  101. }
  102. static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
  103. {
  104. struct spi_board_info board_info = { 0 };
  105. struct device *dev = &dfl_dev->dev;
  106. struct spi_master *master;
  107. struct altera_spi *hw;
  108. void __iomem *base;
  109. int err;
  110. master = devm_spi_alloc_master(dev, sizeof(struct altera_spi));
  111. if (!master)
  112. return -ENOMEM;
  113. master->bus_num = -1;
  114. hw = spi_master_get_devdata(master);
  115. hw->dev = dev;
  116. base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
  117. if (IS_ERR(base))
  118. return PTR_ERR(base);
  119. config_spi_master(base, master);
  120. dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
  121. master->num_chipselect, master->bits_per_word_mask,
  122. master->mode_bits);
  123. hw->regmap = devm_regmap_init(dev, NULL, base, &indirect_regbus_cfg);
  124. if (IS_ERR(hw->regmap))
  125. return PTR_ERR(hw->regmap);
  126. hw->irq = -EINVAL;
  127. altera_spi_init_master(master);
  128. err = devm_spi_register_master(dev, master);
  129. if (err)
  130. return dev_err_probe(dev, err, "%s failed to register spi master\n",
  131. __func__);
  132. if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010)
  133. strscpy(board_info.modalias, "m10-n5010", SPI_NAME_SIZE);
  134. else
  135. strscpy(board_info.modalias, "m10-d5005", SPI_NAME_SIZE);
  136. board_info.max_speed_hz = 12500000;
  137. board_info.bus_num = 0;
  138. board_info.chip_select = 0;
  139. if (!spi_new_device(master, &board_info)) {
  140. dev_err(dev, "%s failed to create SPI device: %s\n",
  141. __func__, board_info.modalias);
  142. }
  143. return 0;
  144. }
  145. static const struct dfl_device_id dfl_spi_altera_ids[] = {
  146. { FME_ID, FME_FEATURE_ID_MAX10_SPI },
  147. { }
  148. };
  149. static struct dfl_driver dfl_spi_altera_driver = {
  150. .drv = {
  151. .name = "dfl-spi-altera",
  152. },
  153. .id_table = dfl_spi_altera_ids,
  154. .probe = dfl_spi_altera_probe,
  155. };
  156. module_dfl_driver(dfl_spi_altera_driver);
  157. MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids);
  158. MODULE_DESCRIPTION("DFL spi altera driver");
  159. MODULE_AUTHOR("Intel Corporation");
  160. MODULE_LICENSE("GPL v2");