smartpqi.h 46 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * driver for Microchip PQI-based storage controllers
  4. * Copyright (c) 2019-2022 Microchip Technology Inc. and its subsidiaries
  5. * Copyright (c) 2016-2018 Microsemi Corporation
  6. * Copyright (c) 2016 PMC-Sierra, Inc.
  7. *
  8. * Questions/Comments/Bugfixes to [email protected]
  9. *
  10. */
  11. #include <linux/io-64-nonatomic-lo-hi.h>
  12. #if !defined(_SMARTPQI_H)
  13. #define _SMARTPQI_H
  14. #include <scsi/scsi_host.h>
  15. #include <linux/bsg-lib.h>
  16. #pragma pack(1)
  17. #define PQI_DEVICE_SIGNATURE "PQI DREG"
  18. /* This structure is defined by the PQI specification. */
  19. struct pqi_device_registers {
  20. __le64 signature;
  21. u8 function_and_status_code;
  22. u8 reserved[7];
  23. u8 max_admin_iq_elements;
  24. u8 max_admin_oq_elements;
  25. u8 admin_iq_element_length; /* in 16-byte units */
  26. u8 admin_oq_element_length; /* in 16-byte units */
  27. __le16 max_reset_timeout; /* in 100-millisecond units */
  28. u8 reserved1[2];
  29. __le32 legacy_intx_status;
  30. __le32 legacy_intx_mask_set;
  31. __le32 legacy_intx_mask_clear;
  32. u8 reserved2[28];
  33. __le32 device_status;
  34. u8 reserved3[4];
  35. __le64 admin_iq_pi_offset;
  36. __le64 admin_oq_ci_offset;
  37. __le64 admin_iq_element_array_addr;
  38. __le64 admin_oq_element_array_addr;
  39. __le64 admin_iq_ci_addr;
  40. __le64 admin_oq_pi_addr;
  41. u8 admin_iq_num_elements;
  42. u8 admin_oq_num_elements;
  43. __le16 admin_queue_int_msg_num;
  44. u8 reserved4[4];
  45. __le32 device_error;
  46. u8 reserved5[4];
  47. __le64 error_details;
  48. __le32 device_reset;
  49. __le32 power_action;
  50. u8 reserved6[104];
  51. };
  52. /*
  53. * controller registers
  54. *
  55. * These are defined by the Microchip implementation.
  56. *
  57. * Some registers (those named sis_*) are only used when in
  58. * legacy SIS mode before we transition the controller into
  59. * PQI mode. There are a number of other SIS mode registers,
  60. * but we don't use them, so only the SIS registers that we
  61. * care about are defined here. The offsets mentioned in the
  62. * comments are the offsets from the PCIe BAR 0.
  63. */
  64. struct pqi_ctrl_registers {
  65. u8 reserved[0x20];
  66. __le32 sis_host_to_ctrl_doorbell; /* 20h */
  67. u8 reserved1[0x34 - (0x20 + sizeof(__le32))];
  68. __le32 sis_interrupt_mask; /* 34h */
  69. u8 reserved2[0x9c - (0x34 + sizeof(__le32))];
  70. __le32 sis_ctrl_to_host_doorbell; /* 9Ch */
  71. u8 reserved3[0xa0 - (0x9c + sizeof(__le32))];
  72. __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */
  73. u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))];
  74. __le32 sis_driver_scratch; /* B0h */
  75. __le32 sis_product_identifier; /* B4h */
  76. u8 reserved5[0xbc - (0xb4 + sizeof(__le32))];
  77. __le32 sis_firmware_status; /* BCh */
  78. u8 reserved6[0xcc - (0xbc + sizeof(__le32))];
  79. __le32 sis_ctrl_shutdown_reason_code; /* CCh */
  80. u8 reserved7[0x1000 - (0xcc + sizeof(__le32))];
  81. __le32 sis_mailbox[8]; /* 1000h */
  82. u8 reserved8[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
  83. /*
  84. * The PQI spec states that the PQI registers should be at
  85. * offset 0 from the PCIe BAR 0. However, we can't map
  86. * them at offset 0 because that would break compatibility
  87. * with the SIS registers. So we map them at offset 4000h.
  88. */
  89. struct pqi_device_registers pqi_registers; /* 4000h */
  90. };
  91. #define PQI_DEVICE_REGISTERS_OFFSET 0x4000
  92. /* shutdown reasons for taking the controller offline */
  93. enum pqi_ctrl_shutdown_reason {
  94. PQI_IQ_NOT_DRAINED_TIMEOUT = 1,
  95. PQI_LUN_RESET_TIMEOUT = 2,
  96. PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT = 3,
  97. PQI_NO_HEARTBEAT = 4,
  98. PQI_FIRMWARE_KERNEL_NOT_UP = 5,
  99. PQI_OFA_RESPONSE_TIMEOUT = 6,
  100. PQI_INVALID_REQ_ID = 7,
  101. PQI_UNMATCHED_REQ_ID = 8,
  102. PQI_IO_PI_OUT_OF_RANGE = 9,
  103. PQI_EVENT_PI_OUT_OF_RANGE = 10,
  104. PQI_UNEXPECTED_IU_TYPE = 11
  105. };
  106. enum pqi_io_path {
  107. RAID_PATH = 0,
  108. AIO_PATH = 1
  109. };
  110. enum pqi_irq_mode {
  111. IRQ_MODE_NONE,
  112. IRQ_MODE_INTX,
  113. IRQ_MODE_MSIX
  114. };
  115. struct pqi_sg_descriptor {
  116. __le64 address;
  117. __le32 length;
  118. __le32 flags;
  119. };
  120. /* manifest constants for the flags field of pqi_sg_descriptor */
  121. #define CISS_SG_LAST 0x40000000
  122. #define CISS_SG_CHAIN 0x80000000
  123. struct pqi_iu_header {
  124. u8 iu_type;
  125. u8 reserved;
  126. __le16 iu_length; /* in bytes - does not include the length */
  127. /* of this header */
  128. __le16 response_queue_id; /* specifies the OQ where the */
  129. /* response IU is to be delivered */
  130. u16 driver_flags; /* reserved for driver use */
  131. };
  132. /* manifest constants for pqi_iu_header.driver_flags */
  133. #define PQI_DRIVER_NONBLOCKABLE_REQUEST 0x1
  134. /*
  135. * According to the PQI spec, the IU header is only the first 4 bytes of our
  136. * pqi_iu_header structure.
  137. */
  138. #define PQI_REQUEST_HEADER_LENGTH 4
  139. struct pqi_general_admin_request {
  140. struct pqi_iu_header header;
  141. __le16 request_id;
  142. u8 function_code;
  143. union {
  144. struct {
  145. u8 reserved[33];
  146. __le32 buffer_length;
  147. struct pqi_sg_descriptor sg_descriptor;
  148. } report_device_capability;
  149. struct {
  150. u8 reserved;
  151. __le16 queue_id;
  152. u8 reserved1[2];
  153. __le64 element_array_addr;
  154. __le64 ci_addr;
  155. __le16 num_elements;
  156. __le16 element_length;
  157. u8 queue_protocol;
  158. u8 reserved2[23];
  159. __le32 vendor_specific;
  160. } create_operational_iq;
  161. struct {
  162. u8 reserved;
  163. __le16 queue_id;
  164. u8 reserved1[2];
  165. __le64 element_array_addr;
  166. __le64 pi_addr;
  167. __le16 num_elements;
  168. __le16 element_length;
  169. u8 queue_protocol;
  170. u8 reserved2[3];
  171. __le16 int_msg_num;
  172. __le16 coalescing_count;
  173. __le32 min_coalescing_time;
  174. __le32 max_coalescing_time;
  175. u8 reserved3[8];
  176. __le32 vendor_specific;
  177. } create_operational_oq;
  178. struct {
  179. u8 reserved;
  180. __le16 queue_id;
  181. u8 reserved1[50];
  182. } delete_operational_queue;
  183. struct {
  184. u8 reserved;
  185. __le16 queue_id;
  186. u8 reserved1[46];
  187. __le32 vendor_specific;
  188. } change_operational_iq_properties;
  189. } data;
  190. };
  191. struct pqi_general_admin_response {
  192. struct pqi_iu_header header;
  193. __le16 request_id;
  194. u8 function_code;
  195. u8 status;
  196. union {
  197. struct {
  198. u8 status_descriptor[4];
  199. __le64 iq_pi_offset;
  200. u8 reserved[40];
  201. } create_operational_iq;
  202. struct {
  203. u8 status_descriptor[4];
  204. __le64 oq_ci_offset;
  205. u8 reserved[40];
  206. } create_operational_oq;
  207. } data;
  208. };
  209. struct pqi_iu_layer_descriptor {
  210. u8 inbound_spanning_supported : 1;
  211. u8 reserved : 7;
  212. u8 reserved1[5];
  213. __le16 max_inbound_iu_length;
  214. u8 outbound_spanning_supported : 1;
  215. u8 reserved2 : 7;
  216. u8 reserved3[5];
  217. __le16 max_outbound_iu_length;
  218. };
  219. struct pqi_device_capability {
  220. __le16 data_length;
  221. u8 reserved[6];
  222. u8 iq_arbitration_priority_support_bitmask;
  223. u8 maximum_aw_a;
  224. u8 maximum_aw_b;
  225. u8 maximum_aw_c;
  226. u8 max_arbitration_burst : 3;
  227. u8 reserved1 : 4;
  228. u8 iqa : 1;
  229. u8 reserved2[2];
  230. u8 iq_freeze : 1;
  231. u8 reserved3 : 7;
  232. __le16 max_inbound_queues;
  233. __le16 max_elements_per_iq;
  234. u8 reserved4[4];
  235. __le16 max_iq_element_length;
  236. __le16 min_iq_element_length;
  237. u8 reserved5[2];
  238. __le16 max_outbound_queues;
  239. __le16 max_elements_per_oq;
  240. __le16 intr_coalescing_time_granularity;
  241. __le16 max_oq_element_length;
  242. __le16 min_oq_element_length;
  243. u8 reserved6[24];
  244. struct pqi_iu_layer_descriptor iu_layer_descriptors[32];
  245. };
  246. #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4
  247. #define PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS 3
  248. struct pqi_raid_path_request {
  249. struct pqi_iu_header header;
  250. __le16 request_id;
  251. __le16 nexus_id;
  252. __le32 buffer_length;
  253. u8 lun_number[8];
  254. __le16 protocol_specific;
  255. u8 data_direction : 2;
  256. u8 partial : 1;
  257. u8 reserved1 : 4;
  258. u8 fence : 1;
  259. __le16 error_index;
  260. u8 reserved2;
  261. u8 task_attribute : 3;
  262. u8 command_priority : 4;
  263. u8 reserved3 : 1;
  264. u8 reserved4 : 2;
  265. u8 additional_cdb_bytes_usage : 3;
  266. u8 reserved5 : 3;
  267. u8 cdb[16];
  268. u8 reserved6[11];
  269. u8 ml_device_lun_number;
  270. __le32 timeout;
  271. struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
  272. };
  273. struct pqi_aio_path_request {
  274. struct pqi_iu_header header;
  275. __le16 request_id;
  276. u8 reserved1[2];
  277. __le32 nexus_id;
  278. __le32 buffer_length;
  279. u8 data_direction : 2;
  280. u8 partial : 1;
  281. u8 memory_type : 1;
  282. u8 fence : 1;
  283. u8 encryption_enable : 1;
  284. u8 reserved2 : 2;
  285. u8 task_attribute : 3;
  286. u8 command_priority : 4;
  287. u8 reserved3 : 1;
  288. __le16 data_encryption_key_index;
  289. __le32 encrypt_tweak_lower;
  290. __le32 encrypt_tweak_upper;
  291. u8 cdb[16];
  292. __le16 error_index;
  293. u8 num_sg_descriptors;
  294. u8 cdb_length;
  295. u8 lun_number[8];
  296. u8 reserved4[4];
  297. struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
  298. };
  299. #define PQI_RAID1_NVME_XFER_LIMIT (32 * 1024) /* 32 KiB */
  300. struct pqi_aio_r1_path_request {
  301. struct pqi_iu_header header;
  302. __le16 request_id;
  303. __le16 volume_id; /* ID of the RAID volume */
  304. __le32 it_nexus_1; /* IT nexus of the 1st drive in the RAID volume */
  305. __le32 it_nexus_2; /* IT nexus of the 2nd drive in the RAID volume */
  306. __le32 it_nexus_3; /* IT nexus of the 3rd drive in the RAID volume */
  307. __le32 data_length; /* total bytes to read/write */
  308. u8 data_direction : 2;
  309. u8 partial : 1;
  310. u8 memory_type : 1;
  311. u8 fence : 1;
  312. u8 encryption_enable : 1;
  313. u8 reserved : 2;
  314. u8 task_attribute : 3;
  315. u8 command_priority : 4;
  316. u8 reserved2 : 1;
  317. __le16 data_encryption_key_index;
  318. u8 cdb[16];
  319. __le16 error_index;
  320. u8 num_sg_descriptors;
  321. u8 cdb_length;
  322. u8 num_drives; /* number of drives in the RAID volume (2 or 3) */
  323. u8 reserved3[3];
  324. __le32 encrypt_tweak_lower;
  325. __le32 encrypt_tweak_upper;
  326. struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
  327. };
  328. #define PQI_DEFAULT_MAX_WRITE_RAID_5_6 (8 * 1024U)
  329. #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA (~0U)
  330. #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME (32 * 1024U)
  331. struct pqi_aio_r56_path_request {
  332. struct pqi_iu_header header;
  333. __le16 request_id;
  334. __le16 volume_id; /* ID of the RAID volume */
  335. __le32 data_it_nexus; /* IT nexus for the data drive */
  336. __le32 p_parity_it_nexus; /* IT nexus for the P parity drive */
  337. __le32 q_parity_it_nexus; /* IT nexus for the Q parity drive */
  338. __le32 data_length; /* total bytes to read/write */
  339. u8 data_direction : 2;
  340. u8 partial : 1;
  341. u8 mem_type : 1; /* 0 = PCIe, 1 = DDR */
  342. u8 fence : 1;
  343. u8 encryption_enable : 1;
  344. u8 reserved : 2;
  345. u8 task_attribute : 3;
  346. u8 command_priority : 4;
  347. u8 reserved1 : 1;
  348. __le16 data_encryption_key_index;
  349. u8 cdb[16];
  350. __le16 error_index;
  351. u8 num_sg_descriptors;
  352. u8 cdb_length;
  353. u8 xor_multiplier;
  354. u8 reserved2[3];
  355. __le32 encrypt_tweak_lower;
  356. __le32 encrypt_tweak_upper;
  357. __le64 row; /* row = logical LBA/blocks per row */
  358. u8 reserved3[8];
  359. struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS];
  360. };
  361. struct pqi_io_response {
  362. struct pqi_iu_header header;
  363. __le16 request_id;
  364. __le16 error_index;
  365. u8 reserved2[4];
  366. };
  367. struct pqi_general_management_request {
  368. struct pqi_iu_header header;
  369. __le16 request_id;
  370. union {
  371. struct {
  372. u8 reserved[2];
  373. __le32 buffer_length;
  374. struct pqi_sg_descriptor sg_descriptors[3];
  375. } report_event_configuration;
  376. struct {
  377. __le16 global_event_oq_id;
  378. __le32 buffer_length;
  379. struct pqi_sg_descriptor sg_descriptors[3];
  380. } set_event_configuration;
  381. } data;
  382. };
  383. struct pqi_event_descriptor {
  384. u8 event_type;
  385. u8 reserved;
  386. __le16 oq_id;
  387. };
  388. struct pqi_event_config {
  389. u8 reserved[2];
  390. u8 num_event_descriptors;
  391. u8 reserved1;
  392. struct pqi_event_descriptor descriptors[];
  393. };
  394. #define PQI_MAX_EVENT_DESCRIPTORS 255
  395. #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
  396. #define PQI_EVENT_OFA_QUIESCE 0x1
  397. #define PQI_EVENT_OFA_CANCELED 0x2
  398. struct pqi_event_response {
  399. struct pqi_iu_header header;
  400. u8 event_type;
  401. u8 reserved2 : 7;
  402. u8 request_acknowledge : 1;
  403. __le16 event_id;
  404. __le32 additional_event_id;
  405. union {
  406. struct {
  407. __le32 bytes_requested;
  408. u8 reserved[12];
  409. } ofa_memory_allocation;
  410. struct {
  411. __le16 reason; /* reason for cancellation */
  412. u8 reserved[14];
  413. } ofa_cancelled;
  414. } data;
  415. };
  416. struct pqi_event_acknowledge_request {
  417. struct pqi_iu_header header;
  418. u8 event_type;
  419. u8 reserved2;
  420. __le16 event_id;
  421. __le32 additional_event_id;
  422. };
  423. struct pqi_task_management_request {
  424. struct pqi_iu_header header;
  425. __le16 request_id;
  426. __le16 nexus_id;
  427. u8 reserved;
  428. u8 ml_device_lun_number;
  429. __le16 timeout;
  430. u8 lun_number[8];
  431. __le16 protocol_specific;
  432. __le16 outbound_queue_id_to_manage;
  433. __le16 request_id_to_manage;
  434. u8 task_management_function;
  435. u8 reserved2 : 7;
  436. u8 fence : 1;
  437. };
  438. #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
  439. struct pqi_task_management_response {
  440. struct pqi_iu_header header;
  441. __le16 request_id;
  442. __le16 nexus_id;
  443. u8 additional_response_info[3];
  444. u8 response_code;
  445. };
  446. struct pqi_vendor_general_request {
  447. struct pqi_iu_header header;
  448. __le16 request_id;
  449. __le16 function_code;
  450. union {
  451. struct {
  452. __le16 first_section;
  453. __le16 last_section;
  454. u8 reserved[48];
  455. } config_table_update;
  456. struct {
  457. __le64 buffer_address;
  458. __le32 buffer_length;
  459. u8 reserved[40];
  460. } ofa_memory_allocation;
  461. } data;
  462. };
  463. struct pqi_vendor_general_response {
  464. struct pqi_iu_header header;
  465. __le16 request_id;
  466. __le16 function_code;
  467. __le16 status;
  468. u8 reserved[2];
  469. };
  470. #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
  471. #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1
  472. #define PQI_OFA_VERSION 1
  473. #define PQI_OFA_SIGNATURE "OFA_QRM"
  474. #define PQI_OFA_MAX_SG_DESCRIPTORS 64
  475. struct pqi_ofa_memory {
  476. __le64 signature; /* "OFA_QRM" */
  477. __le16 version; /* version of this struct (1 = 1st version) */
  478. u8 reserved[62];
  479. __le32 bytes_allocated; /* total allocated memory in bytes */
  480. __le16 num_memory_descriptors;
  481. u8 reserved1[2];
  482. struct pqi_sg_descriptor sg_descriptor[PQI_OFA_MAX_SG_DESCRIPTORS];
  483. };
  484. struct pqi_aio_error_info {
  485. u8 status;
  486. u8 service_response;
  487. u8 data_present;
  488. u8 reserved;
  489. __le32 residual_count;
  490. __le16 data_length;
  491. __le16 reserved1;
  492. u8 data[256];
  493. };
  494. struct pqi_raid_error_info {
  495. u8 data_in_result;
  496. u8 data_out_result;
  497. u8 reserved[3];
  498. u8 status;
  499. __le16 status_qualifier;
  500. __le16 sense_data_length;
  501. __le16 response_data_length;
  502. __le32 data_in_transferred;
  503. __le32 data_out_transferred;
  504. u8 data[256];
  505. };
  506. #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13
  507. #define PQI_REQUEST_IU_RAID_PATH_IO 0x14
  508. #define PQI_REQUEST_IU_AIO_PATH_IO 0x15
  509. #define PQI_REQUEST_IU_AIO_PATH_RAID5_IO 0x18
  510. #define PQI_REQUEST_IU_AIO_PATH_RAID6_IO 0x19
  511. #define PQI_REQUEST_IU_AIO_PATH_RAID1_IO 0x1A
  512. #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
  513. #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
  514. #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
  515. #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
  516. #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
  517. #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
  518. #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
  519. #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
  520. #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0
  521. #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1
  522. #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2
  523. #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
  524. #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4
  525. #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5
  526. #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
  527. #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0
  528. #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10
  529. #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11
  530. #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12
  531. #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13
  532. #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14
  533. #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0
  534. #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1
  535. #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c
  536. #define PQI_PROTOCOL_SOP 0x0
  537. #define PQI_DATA_IN_OUT_GOOD 0x0
  538. #define PQI_DATA_IN_OUT_UNDERFLOW 0x1
  539. #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40
  540. #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41
  541. #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42
  542. #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43
  543. #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60
  544. #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61
  545. #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62
  546. #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63
  547. #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64
  548. #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65
  549. #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66
  550. #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67
  551. #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F
  552. #define PQI_DATA_IN_OUT_ERROR 0xf0
  553. #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1
  554. #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2
  555. #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
  556. #define PQI_DATA_IN_OUT_ABORTED 0xf4
  557. #define PQI_DATA_IN_OUT_TIMEOUT 0xf5
  558. #define CISS_CMD_STATUS_SUCCESS 0x0
  559. #define CISS_CMD_STATUS_TARGET_STATUS 0x1
  560. #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2
  561. #define CISS_CMD_STATUS_DATA_OVERRUN 0x3
  562. #define CISS_CMD_STATUS_INVALID 0x4
  563. #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5
  564. #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6
  565. #define CISS_CMD_STATUS_CONNECTION_LOST 0x7
  566. #define CISS_CMD_STATUS_ABORTED 0x8
  567. #define CISS_CMD_STATUS_ABORT_FAILED 0x9
  568. #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa
  569. #define CISS_CMD_STATUS_TIMEOUT 0xb
  570. #define CISS_CMD_STATUS_UNABORTABLE 0xc
  571. #define CISS_CMD_STATUS_TMF 0xd
  572. #define CISS_CMD_STATUS_AIO_DISABLED 0xe
  573. #define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED
  574. #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32
  575. #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response)
  576. #define PQI_EVENT_TYPE_HOTPLUG 0x1
  577. #define PQI_EVENT_TYPE_HARDWARE 0x2
  578. #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
  579. #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
  580. #define PQI_EVENT_TYPE_OFA 0xfb
  581. #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
  582. #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
  583. #pragma pack()
  584. #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \
  585. sizeof(struct pqi_raid_error_info)
  586. /* these values are based on our implementation */
  587. #define PQI_ADMIN_IQ_NUM_ELEMENTS 8
  588. #define PQI_ADMIN_OQ_NUM_ELEMENTS 20
  589. #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64
  590. #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64
  591. #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128
  592. #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16
  593. #define PQI_MIN_MSIX_VECTORS 1
  594. #define PQI_MAX_MSIX_VECTORS 64
  595. /* these values are defined by the PQI spec */
  596. #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255
  597. #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535
  598. #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64
  599. #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16
  600. #define PQI_ADMIN_INDEX_ALIGNMENT 64
  601. #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4
  602. #define PQI_MIN_OPERATIONAL_QUEUE_ID 1
  603. #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535
  604. #define PQI_AIO_SERV_RESPONSE_COMPLETE 0
  605. #define PQI_AIO_SERV_RESPONSE_FAILURE 1
  606. #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2
  607. #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
  608. #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
  609. #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
  610. #define PQI_AIO_STATUS_IO_ERROR 0x1
  611. #define PQI_AIO_STATUS_IO_ABORTED 0x2
  612. #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3
  613. #define PQI_AIO_STATUS_INVALID_DEVICE 0x4
  614. #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe
  615. #define PQI_AIO_STATUS_UNDERRUN 0x51
  616. #define PQI_AIO_STATUS_OVERRUN 0x75
  617. typedef u32 pqi_index_t;
  618. /* SOP data direction flags */
  619. #define SOP_NO_DIRECTION_FLAG 0
  620. #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */
  621. /* buffer */
  622. #define SOP_READ_FLAG 2 /* host receives data from Data-In */
  623. /* buffer */
  624. #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */
  625. /* Data-Out buffer and data is */
  626. /* transferred to the Data-In buffer */
  627. #define SOP_TASK_ATTRIBUTE_SIMPLE 0
  628. #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
  629. #define SOP_TASK_ATTRIBUTE_ORDERED 2
  630. #define SOP_TASK_ATTRIBUTE_ACA 4
  631. #define SOP_TMF_COMPLETE 0x0
  632. #define SOP_TMF_REJECTED 0x4
  633. #define SOP_TMF_FUNCTION_SUCCEEDED 0x8
  634. #define SOP_RC_INCORRECT_LOGICAL_UNIT 0x9
  635. /* additional CDB bytes usage field codes */
  636. #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */
  637. #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */
  638. #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */
  639. #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */
  640. #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */
  641. /*
  642. * The purpose of this structure is to obtain proper alignment of objects in
  643. * an admin queue pair.
  644. */
  645. struct pqi_admin_queues_aligned {
  646. __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
  647. u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH]
  648. [PQI_ADMIN_IQ_NUM_ELEMENTS];
  649. __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
  650. u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH]
  651. [PQI_ADMIN_OQ_NUM_ELEMENTS];
  652. __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci;
  653. __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi;
  654. };
  655. struct pqi_admin_queues {
  656. void *iq_element_array;
  657. void *oq_element_array;
  658. pqi_index_t __iomem *iq_ci;
  659. pqi_index_t __iomem *oq_pi;
  660. dma_addr_t iq_element_array_bus_addr;
  661. dma_addr_t oq_element_array_bus_addr;
  662. dma_addr_t iq_ci_bus_addr;
  663. dma_addr_t oq_pi_bus_addr;
  664. __le32 __iomem *iq_pi;
  665. pqi_index_t iq_pi_copy;
  666. __le32 __iomem *oq_ci;
  667. pqi_index_t oq_ci_copy;
  668. struct task_struct *task;
  669. u16 int_msg_num;
  670. };
  671. struct pqi_queue_group {
  672. struct pqi_ctrl_info *ctrl_info; /* backpointer */
  673. u16 iq_id[2];
  674. u16 oq_id;
  675. u16 int_msg_num;
  676. void *iq_element_array[2];
  677. void *oq_element_array;
  678. dma_addr_t iq_element_array_bus_addr[2];
  679. dma_addr_t oq_element_array_bus_addr;
  680. __le32 __iomem *iq_pi[2];
  681. pqi_index_t iq_pi_copy[2];
  682. pqi_index_t __iomem *iq_ci[2];
  683. pqi_index_t __iomem *oq_pi;
  684. dma_addr_t iq_ci_bus_addr[2];
  685. dma_addr_t oq_pi_bus_addr;
  686. __le32 __iomem *oq_ci;
  687. pqi_index_t oq_ci_copy;
  688. spinlock_t submit_lock[2]; /* protect submission queue */
  689. struct list_head request_list[2];
  690. };
  691. struct pqi_event_queue {
  692. u16 oq_id;
  693. u16 int_msg_num;
  694. void *oq_element_array;
  695. pqi_index_t __iomem *oq_pi;
  696. dma_addr_t oq_element_array_bus_addr;
  697. dma_addr_t oq_pi_bus_addr;
  698. __le32 __iomem *oq_ci;
  699. pqi_index_t oq_ci_copy;
  700. };
  701. #define PQI_DEFAULT_QUEUE_GROUP 0
  702. #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS
  703. struct pqi_encryption_info {
  704. u16 data_encryption_key_index;
  705. u32 encrypt_tweak_lower;
  706. u32 encrypt_tweak_upper;
  707. };
  708. #pragma pack(1)
  709. #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE"
  710. #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0)
  711. /* configuration table section IDs */
  712. #define PQI_CONFIG_TABLE_ALL_SECTIONS (-1)
  713. #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0
  714. #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1
  715. #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2
  716. #define PQI_CONFIG_TABLE_SECTION_DEBUG 3
  717. #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4
  718. #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5
  719. struct pqi_config_table {
  720. u8 signature[8]; /* "CFGTABLE" */
  721. __le32 first_section_offset; /* offset in bytes from the base */
  722. /* address of this table to the */
  723. /* first section */
  724. };
  725. struct pqi_config_table_section_header {
  726. __le16 section_id; /* as defined by the */
  727. /* PQI_CONFIG_TABLE_SECTION_* */
  728. /* manifest constants above */
  729. __le16 next_section_offset; /* offset in bytes from base */
  730. /* address of the table of the */
  731. /* next section or 0 if last entry */
  732. };
  733. struct pqi_config_table_general_info {
  734. struct pqi_config_table_section_header header;
  735. __le32 section_length; /* size of this section in bytes */
  736. /* including the section header */
  737. __le32 max_outstanding_requests; /* max. outstanding */
  738. /* commands supported by */
  739. /* the controller */
  740. __le32 max_sg_size; /* max. transfer size of a single */
  741. /* command */
  742. __le32 max_sg_per_request; /* max. number of scatter-gather */
  743. /* entries supported in a single */
  744. /* command */
  745. };
  746. struct pqi_config_table_firmware_features {
  747. struct pqi_config_table_section_header header;
  748. __le16 num_elements;
  749. u8 features_supported[];
  750. /* u8 features_requested_by_host[]; */
  751. /* u8 features_enabled[]; */
  752. /* The 2 fields below are only valid if the MAX_KNOWN_FEATURE bit is set. */
  753. /* __le16 firmware_max_known_feature; */
  754. /* __le16 host_max_known_feature; */
  755. };
  756. #define PQI_FIRMWARE_FEATURE_OFA 0
  757. #define PQI_FIRMWARE_FEATURE_SMP 1
  758. #define PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE 2
  759. #define PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS 3
  760. #define PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS 4
  761. #define PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS 5
  762. #define PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS 6
  763. #define PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS 7
  764. #define PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS 8
  765. #define PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS 9
  766. #define PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS 10
  767. #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
  768. #define PQI_FIRMWARE_FEATURE_UNIQUE_SATA_WWN 12
  769. #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT 13
  770. #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT 14
  771. #define PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME 15
  772. #define PQI_FIRMWARE_FEATURE_UNIQUE_WWID_IN_REPORT_PHYS_LUN 16
  773. #define PQI_FIRMWARE_FEATURE_FW_TRIAGE 17
  774. #define PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5 18
  775. #define PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT 21
  776. #define PQI_FIRMWARE_FEATURE_MAXIMUM 21
  777. struct pqi_config_table_debug {
  778. struct pqi_config_table_section_header header;
  779. __le32 scratchpad;
  780. };
  781. struct pqi_config_table_heartbeat {
  782. struct pqi_config_table_section_header header;
  783. __le32 heartbeat_counter;
  784. };
  785. struct pqi_config_table_soft_reset {
  786. struct pqi_config_table_section_header header;
  787. u8 soft_reset_status;
  788. };
  789. #define PQI_SOFT_RESET_INITIATE 0x1
  790. #define PQI_SOFT_RESET_ABORT 0x2
  791. enum pqi_soft_reset_status {
  792. RESET_INITIATE_FIRMWARE,
  793. RESET_INITIATE_DRIVER,
  794. RESET_ABORT,
  795. RESET_NORESPONSE,
  796. RESET_TIMEDOUT
  797. };
  798. union pqi_reset_register {
  799. struct {
  800. u32 reset_type : 3;
  801. u32 reserved : 2;
  802. u32 reset_action : 3;
  803. u32 hold_in_pd1 : 1;
  804. u32 reserved2 : 23;
  805. } bits;
  806. u32 all_bits;
  807. };
  808. #define PQI_RESET_ACTION_RESET 0x1
  809. #define PQI_RESET_TYPE_NO_RESET 0x0
  810. #define PQI_RESET_TYPE_SOFT_RESET 0x1
  811. #define PQI_RESET_TYPE_FIRM_RESET 0x2
  812. #define PQI_RESET_TYPE_HARD_RESET 0x3
  813. #define PQI_RESET_ACTION_COMPLETED 0x2
  814. #define PQI_RESET_POLL_INTERVAL_MSECS 100
  815. #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0)
  816. #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32
  817. #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U)
  818. #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U)
  819. #define RAID_MAP_MAX_ENTRIES 1024
  820. #define RAID_MAP_MAX_DATA_DISKS_PER_ROW 128
  821. #define PQI_PHYSICAL_DEVICE_BUS 0
  822. #define PQI_RAID_VOLUME_BUS 1
  823. #define PQI_HBA_BUS 2
  824. #define PQI_EXTERNAL_RAID_VOLUME_BUS 3
  825. #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS
  826. #define PQI_VSEP_CISS_BTL 379
  827. struct report_lun_header {
  828. __be32 list_length;
  829. u8 flags;
  830. u8 reserved[3];
  831. };
  832. /* for flags field of struct report_lun_header */
  833. #define CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID (1 << 0)
  834. #define CISS_REPORT_LOG_FLAG_QUEUE_DEPTH (1 << 5)
  835. #define CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX (1 << 6)
  836. #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2 0x2
  837. #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4 0x4
  838. #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK 0xf
  839. struct report_log_lun {
  840. u8 lunid[8];
  841. u8 volume_id[16];
  842. };
  843. struct report_log_lun_list {
  844. struct report_lun_header header;
  845. struct report_log_lun lun_entries[1];
  846. };
  847. struct report_phys_lun_8byte_wwid {
  848. u8 lunid[8];
  849. __be64 wwid;
  850. u8 device_type;
  851. u8 device_flags;
  852. u8 lun_count; /* number of LUNs in a multi-LUN device */
  853. u8 redundant_paths;
  854. u32 aio_handle;
  855. };
  856. struct report_phys_lun_16byte_wwid {
  857. u8 lunid[8];
  858. u8 wwid[16];
  859. u8 device_type;
  860. u8 device_flags;
  861. u8 lun_count; /* number of LUNs in a multi-LUN device */
  862. u8 redundant_paths;
  863. u32 aio_handle;
  864. };
  865. /* for device_flags field of struct report_phys_lun_extended_entry */
  866. #define CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED 0x8
  867. struct report_phys_lun_8byte_wwid_list {
  868. struct report_lun_header header;
  869. struct report_phys_lun_8byte_wwid lun_entries[1];
  870. };
  871. struct report_phys_lun_16byte_wwid_list {
  872. struct report_lun_header header;
  873. struct report_phys_lun_16byte_wwid lun_entries[1];
  874. };
  875. struct raid_map_disk_data {
  876. u32 aio_handle;
  877. u8 xor_mult[2];
  878. u8 reserved[2];
  879. };
  880. /* for flags field of RAID map */
  881. #define RAID_MAP_ENCRYPTION_ENABLED 0x1
  882. struct raid_map {
  883. __le32 structure_size; /* size of entire structure in bytes */
  884. __le32 volume_blk_size; /* bytes / block in the volume */
  885. __le64 volume_blk_cnt; /* logical blocks on the volume */
  886. u8 phys_blk_shift; /* shift factor to convert between */
  887. /* units of logical blocks and */
  888. /* physical disk blocks */
  889. u8 parity_rotation_shift; /* shift factor to convert between */
  890. /* units of logical stripes and */
  891. /* physical stripes */
  892. __le16 strip_size; /* blocks used on each disk / stripe */
  893. __le64 disk_starting_blk; /* first disk block used in volume */
  894. __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
  895. __le16 data_disks_per_row; /* data disk entries / row in the map */
  896. __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */
  897. /* in the map */
  898. __le16 row_cnt; /* rows in each layout map */
  899. __le16 layout_map_count; /* layout maps (1 map per */
  900. /* mirror parity group) */
  901. __le16 flags;
  902. __le16 data_encryption_key_index;
  903. u8 reserved[16];
  904. struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES];
  905. };
  906. #pragma pack()
  907. struct pqi_scsi_dev_raid_map_data {
  908. bool is_write;
  909. u8 raid_level;
  910. u32 map_index;
  911. u64 first_block;
  912. u64 last_block;
  913. u32 data_length;
  914. u32 block_cnt;
  915. u32 blocks_per_row;
  916. u64 first_row;
  917. u64 last_row;
  918. u32 first_row_offset;
  919. u32 last_row_offset;
  920. u32 first_column;
  921. u32 last_column;
  922. u64 r5or6_first_row;
  923. u64 r5or6_last_row;
  924. u32 r5or6_first_row_offset;
  925. u32 r5or6_last_row_offset;
  926. u32 r5or6_first_column;
  927. u32 r5or6_last_column;
  928. u16 data_disks_per_row;
  929. u32 total_disks_per_row;
  930. u16 layout_map_count;
  931. u32 stripesize;
  932. u16 strip_size;
  933. u32 first_group;
  934. u32 last_group;
  935. u32 map_row;
  936. u32 aio_handle;
  937. u64 disk_block;
  938. u32 disk_block_cnt;
  939. u8 cdb[16];
  940. u8 cdb_length;
  941. /* RAID 1 specific */
  942. #define NUM_RAID1_MAP_ENTRIES 3
  943. u32 num_it_nexus_entries;
  944. u32 it_nexus[NUM_RAID1_MAP_ENTRIES];
  945. /* RAID 5 / RAID 6 specific */
  946. u32 p_parity_it_nexus; /* aio_handle */
  947. u32 q_parity_it_nexus; /* aio_handle */
  948. u8 xor_mult;
  949. u64 row;
  950. u64 stripe_lba;
  951. u32 p_index;
  952. u32 q_index;
  953. };
  954. #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
  955. #define NUM_STREAMS_PER_LUN 8
  956. struct pqi_stream_data {
  957. u64 next_lba;
  958. u32 last_accessed;
  959. };
  960. #define PQI_MAX_LUNS_PER_DEVICE 256
  961. struct pqi_scsi_dev {
  962. int devtype; /* as reported by INQUIRY command */
  963. u8 device_type; /* as reported by */
  964. /* BMIC_IDENTIFY_PHYSICAL_DEVICE */
  965. /* only valid for devtype = TYPE_DISK */
  966. int bus;
  967. int target;
  968. int lun;
  969. u8 scsi3addr[8];
  970. u8 wwid[16];
  971. u8 volume_id[16];
  972. u8 is_physical_device : 1;
  973. u8 is_external_raid_device : 1;
  974. u8 is_expander_smp_device : 1;
  975. u8 target_lun_valid : 1;
  976. u8 device_gone : 1;
  977. u8 new_device : 1;
  978. u8 keep_device : 1;
  979. u8 volume_offline : 1;
  980. u8 rescan : 1;
  981. u8 ignore_device : 1;
  982. bool aio_enabled; /* only valid for physical disks */
  983. bool in_remove;
  984. bool device_offline;
  985. u8 vendor[8]; /* bytes 8-15 of inquiry data */
  986. u8 model[16]; /* bytes 16-31 of inquiry data */
  987. u64 sas_address;
  988. u8 raid_level;
  989. u16 queue_depth; /* max. queue_depth for this device */
  990. u16 advertised_queue_depth;
  991. u32 aio_handle;
  992. u8 volume_status;
  993. u8 active_path_index;
  994. u8 path_map;
  995. u8 bay;
  996. u8 box_index;
  997. u8 phys_box_on_bus;
  998. u8 phy_connected_dev_type;
  999. u8 box[8];
  1000. u16 phys_connector[8];
  1001. u8 phy_id;
  1002. u8 ncq_prio_enable;
  1003. u8 ncq_prio_support;
  1004. u8 lun_count;
  1005. bool raid_bypass_configured; /* RAID bypass configured */
  1006. bool raid_bypass_enabled; /* RAID bypass enabled */
  1007. u32 next_bypass_group[RAID_MAP_MAX_DATA_DISKS_PER_ROW];
  1008. struct raid_map *raid_map; /* RAID bypass map */
  1009. u32 max_transfer_encrypted;
  1010. struct pqi_sas_port *sas_port;
  1011. struct scsi_device *sdev;
  1012. struct list_head scsi_device_list_entry;
  1013. struct list_head new_device_list_entry;
  1014. struct list_head add_list_entry;
  1015. struct list_head delete_list_entry;
  1016. struct pqi_stream_data stream_data[NUM_STREAMS_PER_LUN];
  1017. atomic_t scsi_cmds_outstanding[PQI_MAX_LUNS_PER_DEVICE];
  1018. atomic_t raid_bypass_cnt;
  1019. };
  1020. /* VPD inquiry pages */
  1021. #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
  1022. #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */
  1023. #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */
  1024. #define VPD_PAGE (1 << 8)
  1025. #pragma pack(1)
  1026. /* structure for CISS_VPD_LV_STATUS */
  1027. struct ciss_vpd_logical_volume_status {
  1028. u8 peripheral_info;
  1029. u8 page_code;
  1030. u8 reserved;
  1031. u8 page_length;
  1032. u8 volume_status;
  1033. u8 reserved2[3];
  1034. __be32 flags;
  1035. };
  1036. #pragma pack()
  1037. /* constants for volume_status field of ciss_vpd_logical_volume_status */
  1038. #define CISS_LV_OK 0
  1039. #define CISS_LV_FAILED 1
  1040. #define CISS_LV_NOT_CONFIGURED 2
  1041. #define CISS_LV_DEGRADED 3
  1042. #define CISS_LV_READY_FOR_RECOVERY 4
  1043. #define CISS_LV_UNDERGOING_RECOVERY 5
  1044. #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6
  1045. #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7
  1046. #define CISS_LV_HARDWARE_OVERHEATING 8
  1047. #define CISS_LV_HARDWARE_HAS_OVERHEATED 9
  1048. #define CISS_LV_UNDERGOING_EXPANSION 10
  1049. #define CISS_LV_NOT_AVAILABLE 11
  1050. #define CISS_LV_QUEUED_FOR_EXPANSION 12
  1051. #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13
  1052. #define CISS_LV_EJECTED 14
  1053. #define CISS_LV_UNDERGOING_ERASE 15
  1054. /* state 16 not used */
  1055. #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17
  1056. #define CISS_LV_UNDERGOING_RPI 18
  1057. #define CISS_LV_PENDING_RPI 19
  1058. #define CISS_LV_ENCRYPTED_NO_KEY 20
  1059. /* state 21 not used */
  1060. #define CISS_LV_UNDERGOING_ENCRYPTION 22
  1061. #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23
  1062. #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24
  1063. #define CISS_LV_PENDING_ENCRYPTION 25
  1064. #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26
  1065. #define CISS_LV_NOT_SUPPORTED 27
  1066. #define CISS_LV_STATUS_UNAVAILABLE 255
  1067. /* constants for flags field of ciss_vpd_logical_volume_status */
  1068. #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */
  1069. /* host I/O */
  1070. /* for SAS hosts and SAS expanders */
  1071. struct pqi_sas_node {
  1072. struct device *parent_dev;
  1073. struct list_head port_list_head;
  1074. };
  1075. struct pqi_sas_port {
  1076. struct list_head port_list_entry;
  1077. u64 sas_address;
  1078. struct pqi_scsi_dev *device;
  1079. struct sas_port *port;
  1080. int next_phy_index;
  1081. struct list_head phy_list_head;
  1082. struct pqi_sas_node *parent_node;
  1083. struct sas_rphy *rphy;
  1084. };
  1085. struct pqi_sas_phy {
  1086. struct list_head phy_list_entry;
  1087. struct sas_phy *phy;
  1088. struct pqi_sas_port *parent_port;
  1089. bool added_to_port;
  1090. };
  1091. struct pqi_io_request {
  1092. atomic_t refcount;
  1093. u16 index;
  1094. void (*io_complete_callback)(struct pqi_io_request *io_request,
  1095. void *context);
  1096. void *context;
  1097. u8 raid_bypass : 1;
  1098. int status;
  1099. struct pqi_queue_group *queue_group;
  1100. struct scsi_cmnd *scmd;
  1101. void *error_info;
  1102. struct pqi_sg_descriptor *sg_chain_buffer;
  1103. dma_addr_t sg_chain_buffer_dma_handle;
  1104. void *iu;
  1105. struct list_head request_list_entry;
  1106. };
  1107. #define PQI_NUM_SUPPORTED_EVENTS 7
  1108. struct pqi_event {
  1109. bool pending;
  1110. u8 event_type;
  1111. u16 event_id;
  1112. u32 additional_event_id;
  1113. };
  1114. #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1
  1115. #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS
  1116. #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3
  1117. #define PQI_RESERVED_IO_SLOTS \
  1118. (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \
  1119. PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS)
  1120. #define PQI_CTRL_PRODUCT_ID_GEN1 0
  1121. #define PQI_CTRL_PRODUCT_ID_GEN2 7
  1122. #define PQI_CTRL_PRODUCT_REVISION_A 0
  1123. #define PQI_CTRL_PRODUCT_REVISION_B 1
  1124. enum pqi_ctrl_removal_state {
  1125. PQI_CTRL_PRESENT = 0,
  1126. PQI_CTRL_GRACEFUL_REMOVAL,
  1127. PQI_CTRL_SURPRISE_REMOVAL
  1128. };
  1129. struct pqi_ctrl_info {
  1130. unsigned int ctrl_id;
  1131. struct pci_dev *pci_dev;
  1132. char firmware_version[32];
  1133. char serial_number[17];
  1134. char model[17];
  1135. char vendor[9];
  1136. u8 product_id;
  1137. u8 product_revision;
  1138. void __iomem *iomem_base;
  1139. struct pqi_ctrl_registers __iomem *registers;
  1140. struct pqi_device_registers __iomem *pqi_registers;
  1141. u32 max_sg_entries;
  1142. u32 config_table_offset;
  1143. u32 config_table_length;
  1144. u16 max_inbound_queues;
  1145. u16 max_elements_per_iq;
  1146. u16 max_iq_element_length;
  1147. u16 max_outbound_queues;
  1148. u16 max_elements_per_oq;
  1149. u16 max_oq_element_length;
  1150. u32 max_transfer_size;
  1151. u32 max_outstanding_requests;
  1152. u32 max_io_slots;
  1153. unsigned int scsi_ml_can_queue;
  1154. unsigned short sg_tablesize;
  1155. unsigned int max_sectors;
  1156. u32 error_buffer_length;
  1157. void *error_buffer;
  1158. dma_addr_t error_buffer_dma_handle;
  1159. size_t sg_chain_buffer_length;
  1160. unsigned int num_queue_groups;
  1161. u16 max_hw_queue_index;
  1162. u16 num_elements_per_iq;
  1163. u16 num_elements_per_oq;
  1164. u16 max_inbound_iu_length_per_firmware;
  1165. u16 max_inbound_iu_length;
  1166. unsigned int max_sg_per_iu;
  1167. unsigned int max_sg_per_r56_iu;
  1168. void *admin_queue_memory_base;
  1169. u32 admin_queue_memory_length;
  1170. dma_addr_t admin_queue_memory_base_dma_handle;
  1171. void *queue_memory_base;
  1172. u32 queue_memory_length;
  1173. dma_addr_t queue_memory_base_dma_handle;
  1174. struct pqi_admin_queues admin_queues;
  1175. struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS];
  1176. struct pqi_event_queue event_queue;
  1177. enum pqi_irq_mode irq_mode;
  1178. int max_msix_vectors;
  1179. int num_msix_vectors_enabled;
  1180. int num_msix_vectors_initialized;
  1181. int event_irq;
  1182. struct Scsi_Host *scsi_host;
  1183. struct mutex scan_mutex;
  1184. struct mutex lun_reset_mutex;
  1185. bool controller_online;
  1186. bool block_requests;
  1187. bool scan_blocked;
  1188. u8 logical_volume_rescan_needed : 1;
  1189. u8 inbound_spanning_supported : 1;
  1190. u8 outbound_spanning_supported : 1;
  1191. u8 pqi_mode_enabled : 1;
  1192. u8 pqi_reset_quiesce_supported : 1;
  1193. u8 soft_reset_handshake_supported : 1;
  1194. u8 raid_iu_timeout_supported : 1;
  1195. u8 tmf_iu_timeout_supported : 1;
  1196. u8 firmware_triage_supported : 1;
  1197. u8 rpl_extended_format_4_5_supported : 1;
  1198. u8 multi_lun_device_supported : 1;
  1199. u8 enable_r1_writes : 1;
  1200. u8 enable_r5_writes : 1;
  1201. u8 enable_r6_writes : 1;
  1202. u8 lv_drive_type_mix_valid : 1;
  1203. u8 enable_stream_detection : 1;
  1204. u8 disable_managed_interrupts : 1;
  1205. u8 ciss_report_log_flags;
  1206. u32 max_transfer_encrypted_sas_sata;
  1207. u32 max_transfer_encrypted_nvme;
  1208. u32 max_write_raid_5_6;
  1209. u32 max_write_raid_1_10_2drive;
  1210. u32 max_write_raid_1_10_3drive;
  1211. struct list_head scsi_device_list;
  1212. spinlock_t scsi_device_list_lock;
  1213. struct delayed_work rescan_work;
  1214. struct delayed_work update_time_work;
  1215. struct pqi_sas_node *sas_host;
  1216. u64 sas_address;
  1217. struct pqi_io_request *io_request_pool;
  1218. u16 next_io_request_slot;
  1219. struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS];
  1220. struct work_struct event_work;
  1221. atomic_t num_interrupts;
  1222. int previous_num_interrupts;
  1223. u32 previous_heartbeat_count;
  1224. __le32 __iomem *heartbeat_counter;
  1225. u8 __iomem *soft_reset_status;
  1226. struct timer_list heartbeat_timer;
  1227. struct work_struct ctrl_offline_work;
  1228. struct semaphore sync_request_sem;
  1229. atomic_t num_busy_threads;
  1230. atomic_t num_blocked_threads;
  1231. wait_queue_head_t block_requests_wait;
  1232. struct mutex ofa_mutex;
  1233. struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
  1234. dma_addr_t pqi_ofa_mem_dma_handle;
  1235. void **pqi_ofa_chunk_virt_addr;
  1236. struct work_struct ofa_memory_alloc_work;
  1237. struct work_struct ofa_quiesce_work;
  1238. u32 ofa_bytes_requested;
  1239. u16 ofa_cancel_reason;
  1240. enum pqi_ctrl_removal_state ctrl_removal_state;
  1241. };
  1242. enum pqi_ctrl_mode {
  1243. SIS_MODE = 0,
  1244. PQI_MODE
  1245. };
  1246. /*
  1247. * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
  1248. */
  1249. #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
  1250. /* CISS commands */
  1251. #define CISS_READ 0xc0
  1252. #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */
  1253. #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */
  1254. #define CISS_GET_RAID_MAP 0xc8
  1255. /* BMIC commands */
  1256. #define BMIC_IDENTIFY_CONTROLLER 0x11
  1257. #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
  1258. #define BMIC_READ 0x26
  1259. #define BMIC_WRITE 0x27
  1260. #define BMIC_SENSE_FEATURE 0x61
  1261. #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
  1262. #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
  1263. #define BMIC_CSMI_PASSTHRU 0x68
  1264. #define BMIC_WRITE_HOST_WELLNESS 0xa5
  1265. #define BMIC_FLUSH_CACHE 0xc2
  1266. #define BMIC_SET_DIAG_OPTIONS 0xf4
  1267. #define BMIC_SENSE_DIAG_OPTIONS 0xf5
  1268. #define CSMI_CC_SAS_SMP_PASSTHRU 0x17
  1269. #define SA_FLUSH_CACHE 0x1
  1270. #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0)
  1271. #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f)
  1272. #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6])
  1273. #define CISS_GET_DRIVE_NUMBER(lunid) \
  1274. (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
  1275. CISS_GET_LEVEL_2_TARGET((lunid)))
  1276. #define LV_GET_DRIVE_TYPE_MIX(lunid) ((lunid)[6])
  1277. #define LV_DRIVE_TYPE_MIX_UNKNOWN 0
  1278. #define LV_DRIVE_TYPE_MIX_NO_RESTRICTION 1
  1279. #define LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY 2
  1280. #define LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY 3
  1281. #define LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY 4
  1282. #define LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY 5
  1283. #define LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY 6
  1284. #define LV_DRIVE_TYPE_MIX_SAS_ONLY 7
  1285. #define LV_DRIVE_TYPE_MIX_SATA_ONLY 8
  1286. #define LV_DRIVE_TYPE_MIX_NVME_ONLY 9
  1287. #define NO_TIMEOUT ((unsigned long) -1)
  1288. #pragma pack(1)
  1289. struct bmic_identify_controller {
  1290. u8 configured_logical_drive_count;
  1291. __le32 configuration_signature;
  1292. u8 firmware_version_short[4];
  1293. u8 reserved[145];
  1294. __le16 extended_logical_unit_count;
  1295. u8 reserved1[34];
  1296. __le16 firmware_build_number;
  1297. u8 reserved2[8];
  1298. u8 vendor_id[8];
  1299. u8 product_id[16];
  1300. u8 reserved3[62];
  1301. __le32 extra_controller_flags;
  1302. u8 reserved4[2];
  1303. u8 controller_mode;
  1304. u8 spare_part_number[32];
  1305. u8 firmware_version_long[32];
  1306. };
  1307. /* constants for extra_controller_flags field of bmic_identify_controller */
  1308. #define BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED 0x20000000
  1309. struct bmic_sense_subsystem_info {
  1310. u8 reserved[44];
  1311. u8 ctrl_serial_number[16];
  1312. };
  1313. /* constants for device_type field */
  1314. #define SA_DEVICE_TYPE_SATA 0x1
  1315. #define SA_DEVICE_TYPE_SAS 0x2
  1316. #define SA_DEVICE_TYPE_EXPANDER_SMP 0x5
  1317. #define SA_DEVICE_TYPE_SES 0x6
  1318. #define SA_DEVICE_TYPE_CONTROLLER 0x7
  1319. #define SA_DEVICE_TYPE_NVME 0x9
  1320. struct bmic_identify_physical_device {
  1321. u8 scsi_bus; /* SCSI Bus number on controller */
  1322. u8 scsi_id; /* SCSI ID on this bus */
  1323. __le16 block_size; /* sector size in bytes */
  1324. __le32 total_blocks; /* number for sectors on drive */
  1325. __le32 reserved_blocks; /* controller reserved (RIS) */
  1326. u8 model[40]; /* Physical Drive Model */
  1327. u8 serial_number[40]; /* Drive Serial Number */
  1328. u8 firmware_revision[8]; /* drive firmware revision */
  1329. u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
  1330. u8 compaq_drive_stamp; /* 0 means drive not stamped */
  1331. u8 last_failure_reason;
  1332. u8 flags;
  1333. u8 more_flags;
  1334. u8 scsi_lun; /* SCSI LUN for phys drive */
  1335. u8 yet_more_flags;
  1336. u8 even_more_flags;
  1337. __le32 spi_speed_rules;
  1338. u8 phys_connector[2]; /* connector number on controller */
  1339. u8 phys_box_on_bus; /* phys enclosure this drive resides */
  1340. u8 phys_bay_in_box; /* phys drv bay this drive resides */
  1341. __le32 rpm; /* drive rotational speed in RPM */
  1342. u8 device_type; /* type of drive */
  1343. u8 sata_version; /* only valid when device_type = */
  1344. /* SA_DEVICE_TYPE_SATA */
  1345. __le64 big_total_block_count;
  1346. __le64 ris_starting_lba;
  1347. __le32 ris_size;
  1348. u8 wwid[20];
  1349. u8 controller_phy_map[32];
  1350. __le16 phy_count;
  1351. u8 phy_connected_dev_type[256];
  1352. u8 phy_to_drive_bay_num[256];
  1353. __le16 phy_to_attached_dev_index[256];
  1354. u8 box_index;
  1355. u8 reserved;
  1356. __le16 extra_physical_drive_flags;
  1357. u8 negotiated_link_rate[256];
  1358. u8 phy_to_phy_map[256];
  1359. u8 redundant_path_present_map;
  1360. u8 redundant_path_failure_map;
  1361. u8 active_path_number;
  1362. __le16 alternate_paths_phys_connector[8];
  1363. u8 alternate_paths_phys_box_on_port[8];
  1364. u8 multi_lun_device_lun_count;
  1365. u8 minimum_good_fw_revision[8];
  1366. u8 unique_inquiry_bytes[20];
  1367. u8 current_temperature_degrees;
  1368. u8 temperature_threshold_degrees;
  1369. u8 max_temperature_degrees;
  1370. u8 logical_blocks_per_phys_block_exp;
  1371. __le16 current_queue_depth_limit;
  1372. u8 switch_name[10];
  1373. __le16 switch_port;
  1374. u8 alternate_paths_switch_name[40];
  1375. u8 alternate_paths_switch_port[8];
  1376. __le16 power_on_hours;
  1377. __le16 percent_endurance_used;
  1378. u8 drive_authentication;
  1379. u8 smart_carrier_authentication;
  1380. u8 smart_carrier_app_fw_version;
  1381. u8 smart_carrier_bootloader_fw_version;
  1382. u8 sanitize_flags;
  1383. u8 encryption_key_flags;
  1384. u8 encryption_key_name[64];
  1385. __le32 misc_drive_flags;
  1386. __le16 dek_index;
  1387. __le16 hba_drive_encryption_flags;
  1388. __le16 max_overwrite_time;
  1389. __le16 max_block_erase_time;
  1390. __le16 max_crypto_erase_time;
  1391. u8 connector_info[5];
  1392. u8 connector_name[8][8];
  1393. u8 page_83_identifier[16];
  1394. u8 maximum_link_rate[256];
  1395. u8 negotiated_physical_link_rate[256];
  1396. u8 box_connector_name[8];
  1397. u8 padding_to_multiple_of_512[9];
  1398. };
  1399. #define BMIC_SENSE_FEATURE_IO_PAGE 0x8
  1400. #define BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE 0x2
  1401. struct bmic_sense_feature_buffer_header {
  1402. u8 page_code;
  1403. u8 subpage_code;
  1404. __le16 buffer_length;
  1405. };
  1406. struct bmic_sense_feature_page_header {
  1407. u8 page_code;
  1408. u8 subpage_code;
  1409. __le16 page_length;
  1410. };
  1411. struct bmic_sense_feature_io_page_aio_subpage {
  1412. struct bmic_sense_feature_page_header header;
  1413. u8 firmware_read_support;
  1414. u8 driver_read_support;
  1415. u8 firmware_write_support;
  1416. u8 driver_write_support;
  1417. __le16 max_transfer_encrypted_sas_sata;
  1418. __le16 max_transfer_encrypted_nvme;
  1419. __le16 max_write_raid_5_6;
  1420. __le16 max_write_raid_1_10_2drive;
  1421. __le16 max_write_raid_1_10_3drive;
  1422. };
  1423. struct bmic_smp_request {
  1424. u8 frame_type;
  1425. u8 function;
  1426. u8 allocated_response_length;
  1427. u8 request_length;
  1428. u8 additional_request_bytes[1016];
  1429. };
  1430. struct bmic_smp_response {
  1431. u8 frame_type;
  1432. u8 function;
  1433. u8 function_result;
  1434. u8 response_length;
  1435. u8 additional_response_bytes[1016];
  1436. };
  1437. struct bmic_csmi_ioctl_header {
  1438. __le32 header_length;
  1439. u8 signature[8];
  1440. __le32 timeout;
  1441. __le32 control_code;
  1442. __le32 return_code;
  1443. __le32 length;
  1444. };
  1445. struct bmic_csmi_smp_passthru {
  1446. u8 phy_identifier;
  1447. u8 port_identifier;
  1448. u8 connection_rate;
  1449. u8 reserved;
  1450. __be64 destination_sas_address;
  1451. __le32 request_length;
  1452. struct bmic_smp_request request;
  1453. u8 connection_status;
  1454. u8 reserved1[3];
  1455. __le32 response_length;
  1456. struct bmic_smp_response response;
  1457. };
  1458. struct bmic_csmi_smp_passthru_buffer {
  1459. struct bmic_csmi_ioctl_header ioctl_header;
  1460. struct bmic_csmi_smp_passthru parameters;
  1461. };
  1462. struct bmic_flush_cache {
  1463. u8 disable_flag;
  1464. u8 system_power_action;
  1465. u8 ndu_flush;
  1466. u8 shutdown_event;
  1467. u8 reserved[28];
  1468. };
  1469. /* for shutdown_event member of struct bmic_flush_cache */
  1470. enum bmic_flush_cache_shutdown_event {
  1471. NONE_CACHE_FLUSH_ONLY = 0,
  1472. SHUTDOWN = 1,
  1473. HIBERNATE = 2,
  1474. SUSPEND = 3,
  1475. RESTART = 4
  1476. };
  1477. struct bmic_diag_options {
  1478. __le32 options;
  1479. };
  1480. #pragma pack()
  1481. static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
  1482. {
  1483. void *hostdata = shost_priv(shost);
  1484. return *((struct pqi_ctrl_info **)hostdata);
  1485. }
  1486. void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
  1487. struct sas_rphy *rphy);
  1488. int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
  1489. void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
  1490. int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
  1491. struct pqi_scsi_dev *device);
  1492. void pqi_remove_sas_device(struct pqi_scsi_dev *device);
  1493. struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
  1494. struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
  1495. void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
  1496. int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
  1497. struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
  1498. struct pqi_raid_error_info *error_info);
  1499. extern struct sas_function_template pqi_sas_transport_functions;
  1500. #endif /* _SMARTPQI_H */