dc395x.h 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /************************************************************************/
  3. /* */
  4. /* dc395x.h */
  5. /* */
  6. /* Device Driver for Tekram DC395(U/UW/F), DC315(U) */
  7. /* PCI SCSI Bus Master Host Adapter */
  8. /* (SCSI chip set used Tekram ASIC TRM-S1040) */
  9. /* */
  10. /************************************************************************/
  11. #ifndef DC395x_H
  12. #define DC395x_H
  13. /************************************************************************/
  14. /* */
  15. /* Initial values */
  16. /* */
  17. /************************************************************************/
  18. #define DC395x_MAX_CMD_QUEUE 32
  19. /* #define DC395x_MAX_QTAGS 32 */
  20. #define DC395x_MAX_QTAGS 16
  21. #define DC395x_MAX_SCSI_ID 16
  22. #define DC395x_MAX_CMD_PER_LUN DC395x_MAX_QTAGS
  23. #define DC395x_MAX_SG_TABLESIZE 64 /* HW limitation */
  24. #define DC395x_MAX_SG_LISTENTRY 64 /* Must be equal or lower to previous */
  25. /* item */
  26. #define DC395x_MAX_SRB_CNT 63
  27. /* #define DC395x_MAX_CAN_QUEUE 7 * DC395x_MAX_QTAGS */
  28. #define DC395x_MAX_CAN_QUEUE DC395x_MAX_SRB_CNT
  29. #define DC395x_END_SCAN 2
  30. #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
  31. #define DC395x_MAX_RETRIES 3
  32. #if 0
  33. #define SYNC_FIRST
  34. #endif
  35. #define NORM_REC_LVL 0
  36. /************************************************************************/
  37. /* */
  38. /* Various definitions */
  39. /* */
  40. /************************************************************************/
  41. #define BIT31 0x80000000
  42. #define BIT30 0x40000000
  43. #define BIT29 0x20000000
  44. #define BIT28 0x10000000
  45. #define BIT27 0x08000000
  46. #define BIT26 0x04000000
  47. #define BIT25 0x02000000
  48. #define BIT24 0x01000000
  49. #define BIT23 0x00800000
  50. #define BIT22 0x00400000
  51. #define BIT21 0x00200000
  52. #define BIT20 0x00100000
  53. #define BIT19 0x00080000
  54. #define BIT18 0x00040000
  55. #define BIT17 0x00020000
  56. #define BIT16 0x00010000
  57. #define BIT15 0x00008000
  58. #define BIT14 0x00004000
  59. #define BIT13 0x00002000
  60. #define BIT12 0x00001000
  61. #define BIT11 0x00000800
  62. #define BIT10 0x00000400
  63. #define BIT9 0x00000200
  64. #define BIT8 0x00000100
  65. #define BIT7 0x00000080
  66. #define BIT6 0x00000040
  67. #define BIT5 0x00000020
  68. #define BIT4 0x00000010
  69. #define BIT3 0x00000008
  70. #define BIT2 0x00000004
  71. #define BIT1 0x00000002
  72. #define BIT0 0x00000001
  73. /* UnitCtrlFlag */
  74. #define UNIT_ALLOCATED BIT0
  75. #define UNIT_INFO_CHANGED BIT1
  76. #define FORMATING_MEDIA BIT2
  77. #define UNIT_RETRY BIT3
  78. /* UnitFlags */
  79. #define DASD_SUPPORT BIT0
  80. #define SCSI_SUPPORT BIT1
  81. #define ASPI_SUPPORT BIT2
  82. /* SRBState machine definition */
  83. #define SRB_FREE 0x0000
  84. #define SRB_WAIT 0x0001
  85. #define SRB_READY 0x0002
  86. #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */
  87. #define SRB_MSGIN 0x0008
  88. #define SRB_EXTEND_MSGIN 0x0010
  89. #define SRB_COMMAND 0x0020
  90. #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */
  91. #define SRB_DISCONNECT 0x0080
  92. #define SRB_DATA_XFER 0x0100
  93. #define SRB_XFERPAD 0x0200
  94. #define SRB_STATUS 0x0400
  95. #define SRB_COMPLETED 0x0800
  96. #define SRB_ABORT_SENT 0x1000
  97. #define SRB_DO_SYNC_NEGO 0x2000
  98. #define SRB_DO_WIDE_NEGO 0x4000
  99. #define SRB_UNEXPECT_RESEL 0x8000
  100. /************************************************************************/
  101. /* */
  102. /* ACB Config */
  103. /* */
  104. /************************************************************************/
  105. #define HCC_WIDE_CARD 0x20
  106. #define HCC_SCSI_RESET 0x10
  107. #define HCC_PARITY 0x08
  108. #define HCC_AUTOTERM 0x04
  109. #define HCC_LOW8TERM 0x02
  110. #define HCC_UP8TERM 0x01
  111. /* ACBFlag */
  112. #define RESET_DEV BIT0
  113. #define RESET_DETECT BIT1
  114. #define RESET_DONE BIT2
  115. /* DCBFlag */
  116. #define ABORT_DEV_ BIT0
  117. /* SRBstatus */
  118. #define SRB_OK BIT0
  119. #define ABORTION BIT1
  120. #define OVER_RUN BIT2
  121. #define UNDER_RUN BIT3
  122. #define PARITY_ERROR BIT4
  123. #define SRB_ERROR BIT5
  124. /* SRBFlag */
  125. #define DATAOUT BIT7
  126. #define DATAIN BIT6
  127. #define RESIDUAL_VALID BIT5
  128. #define ENABLE_TIMER BIT4
  129. #define RESET_DEV0 BIT2
  130. #define ABORT_DEV BIT1
  131. #define AUTO_REQSENSE BIT0
  132. /* Adapter status */
  133. #define H_STATUS_GOOD 0
  134. #define H_SEL_TIMEOUT 0x11
  135. #define H_OVER_UNDER_RUN 0x12
  136. #define H_UNEXP_BUS_FREE 0x13
  137. #define H_TARGET_PHASE_F 0x14
  138. #define H_INVALID_CCB_OP 0x16
  139. #define H_LINK_CCB_BAD 0x17
  140. #define H_BAD_TARGET_DIR 0x18
  141. #define H_DUPLICATE_CCB 0x19
  142. #define H_BAD_CCB_OR_SG 0x1A
  143. #define H_ABORT 0x0FF
  144. /* SCSI BUS Status byte codes */
  145. #define SCSI_STAT_UNEXP_BUS_F 0xFD /* Unexpect Bus Free */
  146. #define SCSI_STAT_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */
  147. #define SCSI_STAT_SEL_TIMEOUT 0xFF /* Selection Time out */
  148. /* Sync_Mode */
  149. #define SYNC_WIDE_TAG_ATNT_DISABLE 0
  150. #define SYNC_NEGO_ENABLE BIT0
  151. #define SYNC_NEGO_DONE BIT1
  152. #define WIDE_NEGO_ENABLE BIT2
  153. #define WIDE_NEGO_DONE BIT3
  154. #define WIDE_NEGO_STATE BIT4
  155. #define EN_TAG_QUEUEING BIT5
  156. #define EN_ATN_STOP BIT6
  157. #define SYNC_NEGO_OFFSET 15
  158. /* cmd->result */
  159. #define STATUS_MASK_ 0xFF
  160. #define MSG_MASK 0xFF00
  161. #define RETURN_MASK 0xFF0000
  162. /************************************************************************/
  163. /* */
  164. /* Inquiry Data format */
  165. /* */
  166. /************************************************************************/
  167. struct ScsiInqData
  168. { /* INQ */
  169. u8 DevType; /* Periph Qualifier & Periph Dev Type */
  170. u8 RMB_TypeMod; /* rem media bit & Dev Type Modifier */
  171. u8 Vers; /* ISO, ECMA, & ANSI versions */
  172. u8 RDF; /* AEN, TRMIOP, & response data format */
  173. u8 AddLen; /* length of additional data */
  174. u8 Res1; /* reserved */
  175. u8 Res2; /* reserved */
  176. u8 Flags; /* RelADr, Wbus32, Wbus16, Sync, etc. */
  177. u8 VendorID[8]; /* Vendor Identification */
  178. u8 ProductID[16]; /* Product Identification */
  179. u8 ProductRev[4]; /* Product Revision */
  180. };
  181. /* Inquiry byte 0 masks */
  182. #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
  183. #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
  184. /* Inquiry byte 1 mask */
  185. #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
  186. /* Peripheral Device Type definitions */
  187. /* See include/scsi/scsi.h */
  188. #define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */
  189. #ifndef TYPE_PRINTER /* */
  190. # define TYPE_PRINTER 0x02 /* Printer device */
  191. #endif /* */
  192. #ifndef TYPE_COMM /* */
  193. # define TYPE_COMM 0x09 /* Communications device */
  194. #endif
  195. /************************************************************************/
  196. /* */
  197. /* Inquiry flag definitions (Inq data byte 7) */
  198. /* */
  199. /************************************************************************/
  200. #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing */
  201. #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
  202. #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
  203. #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
  204. #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
  205. #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
  206. #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
  207. #define ENABLE_CE 1
  208. #define DISABLE_CE 0
  209. #define EEPROM_READ 0x80
  210. /************************************************************************/
  211. /* */
  212. /* The PCI configuration register offset for TRM_S1040 */
  213. /* */
  214. /************************************************************************/
  215. #define TRM_S1040_ID 0x00 /* Vendor and Device ID */
  216. #define TRM_S1040_COMMAND 0x04 /* PCI command register */
  217. #define TRM_S1040_IOBASE 0x10 /* I/O Space base address */
  218. #define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */
  219. #define TRM_S1040_INTLINE 0x3C /* Interrupt line */
  220. /************************************************************************/
  221. /* */
  222. /* The SCSI register offset for TRM_S1040 */
  223. /* */
  224. /************************************************************************/
  225. #define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */
  226. #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
  227. #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
  228. #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
  229. #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
  230. #define COMMANDABORT 0x0040 /* SCSI command abort */
  231. #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
  232. #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
  233. #define PARITYERROR 0x0008 /* SCSI parity error */
  234. #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
  235. #define PH_DATA_OUT 0x00 /* Data out phase */
  236. #define PH_DATA_IN 0x01 /* Data in phase */
  237. #define PH_COMMAND 0x02 /* Command phase */
  238. #define PH_STATUS 0x03 /* Status phase */
  239. #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
  240. #define PH_MSG_OUT 0x06 /* Message out phase */
  241. #define PH_MSG_IN 0x07 /* Message in phase */
  242. #define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */
  243. #define DO_CLRATN 0x0400 /* Clear ATN */
  244. #define DO_SETATN 0x0200 /* Set ATN */
  245. #define DO_CMDABORT 0x0100 /* Abort SCSI command */
  246. #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
  247. #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
  248. #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
  249. #define DO_DATALATCH 0x0002 /* Enable SCSI bus data input (latched) */
  250. /* #define DO_DATALATCH 0x0000 */ /* KG: DISable SCSI bus data latch */
  251. #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
  252. #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
  253. #define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
  254. #define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
  255. #define INT_SCAM 0x80 /* SCAM selection interrupt */
  256. #define INT_SELECT 0x40 /* Selection interrupt */
  257. #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
  258. #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
  259. #define INT_RESELECTED 0x08 /* Reselected interrupt */
  260. #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */
  261. #define INT_BUSSERVICE 0x02 /* Bus service interrupt */
  262. #define INT_CMDDONE 0x01 /* SCSI command done interrupt */
  263. #define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
  264. /************************************************************************/
  265. /* */
  266. /* Bit Name Definition */
  267. /* --------- ------------- ---------------------------- */
  268. /* 07-05 0 RSVD Reversed. Always 0. */
  269. /* 04 0 OFFSET4 Reversed for LVDS. Always 0. */
  270. /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
  271. /* */
  272. /************************************************************************/
  273. #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */
  274. #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
  275. #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
  276. #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
  277. /************************************************************************/
  278. /* */
  279. /* SYNCM 7 6 5 4 3 2 1 0 */
  280. /* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 */
  281. /* Default 0 0 0 0 0 0 0 0 */
  282. /* */
  283. /* Bit Name Definition */
  284. /* --------- ------------- --------------------------- */
  285. /* 07-06 0 RSVD Reversed. Always read 0 */
  286. /* 05 0 LVDS Reversed. Always read 0 */
  287. /* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */
  288. /* transfer. */
  289. /* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. */
  290. /* */
  291. /* @@ When this bit is set, */
  292. /* the synchronous period bits 2:0 */
  293. /* in the Synchronous Mode register */
  294. /* are used to transfer data */
  295. /* at the Fast-20 rate. */
  296. /* @@ When this bit is unset, */
  297. /* the synchronous period bits 2:0 */
  298. /* in the Synchronous Mode Register */
  299. /* are used to transfer data */
  300. /* at the Fast-10 rate (or Fast-40 w/ LVDS). */
  301. /* */
  302. /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
  303. /* SXPD[02:00] These 3 bits specify */
  304. /* the Synchronous SCSI Transfer */
  305. /* Rate for Fast-20 and Fast-10. */
  306. /* These bits are also reset */
  307. /* by a SCSI Bus reset. */
  308. /* */
  309. /* For Fast-10 bit ALTPD = 0 and LVDS = 0 */
  310. /* and bit2,bit1,bit0 is defined as follows : */
  311. /* */
  312. /* 000 100ns, 10.0 MHz */
  313. /* 001 150ns, 6.6 MHz */
  314. /* 010 200ns, 5.0 MHz */
  315. /* 011 250ns, 4.0 MHz */
  316. /* 100 300ns, 3.3 MHz */
  317. /* 101 350ns, 2.8 MHz */
  318. /* 110 400ns, 2.5 MHz */
  319. /* 111 450ns, 2.2 MHz */
  320. /* */
  321. /* For Fast-20 bit ALTPD = 1 and LVDS = 0 */
  322. /* and bit2,bit1,bit0 is defined as follows : */
  323. /* */
  324. /* 000 50ns, 20.0 MHz */
  325. /* 001 75ns, 13.3 MHz */
  326. /* 010 100ns, 10.0 MHz */
  327. /* 011 125ns, 8.0 MHz */
  328. /* 100 150ns, 6.6 MHz */
  329. /* 101 175ns, 5.7 MHz */
  330. /* 110 200ns, 5.0 MHz */
  331. /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */
  332. /* */
  333. /* For Fast-40 bit ALTPD = 0 and LVDS = 1 */
  334. /* and bit2,bit1,bit0 is defined as follows : */
  335. /* */
  336. /* 000 25ns, 40.0 MHz */
  337. /* 001 50ns, 20.0 MHz */
  338. /* 010 75ns, 13.3 MHz */
  339. /* 011 100ns, 10.0 MHz */
  340. /* 100 125ns, 8.0 MHz */
  341. /* 101 150ns, 6.6 MHz */
  342. /* 110 175ns, 5.7 MHz */
  343. /* 111 200ns, 5.0 MHz */
  344. /* */
  345. /************************************************************************/
  346. #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
  347. #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
  348. #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
  349. #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
  350. #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
  351. #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */
  352. #define EN_SELECT 0x40 /* Enable selection interrupt */
  353. #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */
  354. #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */
  355. #define EN_RESELECTED 0x08 /* Enable reselected interrupt */
  356. #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt */
  357. #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
  358. #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */
  359. #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
  360. #define PHASELATCH 0x40 /* Enable phase latch */
  361. #define INITIATOR 0x20 /* Enable initiator mode */
  362. #define PARITYCHECK 0x10 /* Enable parity check */
  363. #define BLOCKRST 0x01 /* Disable SCSI reset1 */
  364. #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
  365. #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
  366. #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
  367. #define FAST_FILTER 0x04 /* ? */
  368. #define ACTIVE_NEG 0x02 /* Enable active negation */
  369. #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
  370. #define CFG2_WIDEFIFO 0x02 /* */
  371. #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
  372. #define SCMD_COMP 0x12 /* Command complete */
  373. #define SCMD_SEL_ATN 0x60 /* Selection with ATN */
  374. #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
  375. #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
  376. #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
  377. #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
  378. #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
  379. #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
  380. #define SCMD_MSGACCEPT 0xD8 /* Message accept */
  381. /************************************************************************/
  382. /* */
  383. /* Code Command Description */
  384. /* ---- ---------------------------------------- */
  385. /* 02 Enable reselection with FIFO */
  386. /* 40 Select without ATN with FIFO */
  387. /* 60 Select with ATN with FIFO */
  388. /* 64 Select with ATN3 with FIFO */
  389. /* A0 Select with ATN and stop with FIFO */
  390. /* C0 Transfer information out with FIFO */
  391. /* C1 Transfer information out with DMA */
  392. /* C2 Transfer information in with FIFO */
  393. /* C3 Transfer information in with DMA */
  394. /* 12 Initiator command complete with FIFO */
  395. /* 50 Initiator transfer information out sequence without ATN */
  396. /* with FIFO */
  397. /* 70 Initiator transfer information out sequence with ATN */
  398. /* with FIFO */
  399. /* 74 Initiator transfer information out sequence with ATN3 */
  400. /* with FIFO */
  401. /* 52 Initiator transfer information in sequence without ATN */
  402. /* with FIFO */
  403. /* 72 Initiator transfer information in sequence with ATN */
  404. /* with FIFO */
  405. /* 76 Initiator transfer information in sequence with ATN3 */
  406. /* with FIFO */
  407. /* 90 Initiator transfer information out command complete */
  408. /* with FIFO */
  409. /* 92 Initiator transfer information in command complete */
  410. /* with FIFO */
  411. /* D2 Enable selection */
  412. /* 08 Reselection */
  413. /* 48 Disconnect command with FIFO */
  414. /* 88 Terminate command with FIFO */
  415. /* C8 Target command complete with FIFO */
  416. /* 18 SCAM Arbitration/ Selection */
  417. /* 5A Enable reselection */
  418. /* 98 Select without ATN with FIFO */
  419. /* B8 Select with ATN with FIFO */
  420. /* D8 Message Accepted */
  421. /* 58 NOP */
  422. /* */
  423. /************************************************************************/
  424. #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
  425. #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
  426. #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
  427. #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
  428. #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */
  429. #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */
  430. #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */
  431. #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
  432. #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
  433. #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
  434. #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
  435. #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
  436. #define TCR0_OFFSET_MASK 0x001F /* Offset number */
  437. #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
  438. #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
  439. #define NON_TAG_BUSY 0x0080 /* Non tag command active */
  440. #define ACTTAG_MASK 0x007F /* Active tags */
  441. /************************************************************************/
  442. /* */
  443. /* The DMA register offset for TRM_S1040 */
  444. /* */
  445. /************************************************************************/
  446. #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
  447. #define DMACMD_SG 0x02 /* Enable HW S/G support */
  448. #define DMACMD_DIR 0x01 /* 1 = read from SCSI write to Host */
  449. #define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */
  450. #define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */
  451. #define XFERDATAIN 0x0101 /* Transfer data in w/o SG */
  452. #define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */
  453. #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
  454. #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */
  455. #define DMARESETMODULE 0x10 /* Reset PCI/DMA module */
  456. #define STOPDMAXFER 0x08 /* Stop DMA transfer */
  457. #define ABORTXFER 0x04 /* Abort DMA transfer */
  458. #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
  459. #define STARTDMAXFER 0x01 /* Start DMA transfer */
  460. #define TRM_S1040_DMA_FIFOSTAT 0xA2 /* DMA FIFO Status (R) */
  461. #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
  462. #define XFERPENDING 0x80 /* Transfer pending */
  463. #define SCSIBUSY 0x40 /* SCSI busy */
  464. #define GLOBALINT 0x20 /* DMA_INTEN bit 0-4 set */
  465. #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
  466. #define DMAXFERERROR 0x08 /* DMA transfer error */
  467. #define DMAXFERABORT 0x04 /* DMA transfer abort */
  468. #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
  469. #define SCSICOMP 0x01 /* SCSI complete interrupt */
  470. #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */
  471. #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
  472. #define EN_DMAXFERERROR 0x08 /* DMA transfer error */
  473. #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
  474. #define EN_DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
  475. #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
  476. #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
  477. #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature (SG?) */
  478. #define DMA_PCI_DUAL_ADDR 0x4000 /* */
  479. #define DMA_CFG_RES 0x2000 /* Always 1 */
  480. #define DMA_AUTO_CLR_FIFO 0x1000 /* DISable DMA auto clear FIFO */
  481. #define DMA_MEM_MULTI_READ 0x0800 /* */
  482. #define DMA_MEM_WRITE_INVAL 0x0400 /* Memory write and invalidate */
  483. #define DMA_FIFO_CTRL 0x0300 /* Control FIFO operation with DMA */
  484. #define DMA_FIFO_HALF_HALF 0x0200 /* Keep half filled on both read/write */
  485. #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */
  486. #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
  487. #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
  488. #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
  489. /************************************************************************/
  490. /* */
  491. /* The general register offset for TRM_S1040 */
  492. /* */
  493. /************************************************************************/
  494. #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */
  495. #define CTRL_LED 0x80 /* Control onboard LED */
  496. #define EN_EEPROM 0x10 /* Enable EEPROM programming */
  497. #define DIS_TERM 0x08 /* Disable onboard termination */
  498. #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
  499. #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
  500. #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
  501. #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */
  502. #define GTIMEOUT 0x80 /* Global timer reach 0 */
  503. #define EXT68HIGH 0x40 /* Higher 8 bit connected externally */
  504. #define INT68HIGH 0x20 /* Higher 8 bit connected internally */
  505. #define CON5068 0x10 /* External 50/68 pin connected (low) */
  506. #define CON68 0x08 /* Internal 68 pin connected (low) */
  507. #define CON50 0x04 /* Internal 50 pin connected (low!) */
  508. #define WIDESCSI 0x02 /* Wide SCSI card */
  509. #define STATUS_LOAD_DEFAULT 0x01 /* */
  510. #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
  511. #define NVR_BITOUT 0x08 /* Serial data out */
  512. #define NVR_BITIN 0x04 /* Serial data in */
  513. #define NVR_CLOCK 0x02 /* Serial clock */
  514. #define NVR_SELECT 0x01 /* Serial select */
  515. #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
  516. #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
  517. #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */
  518. /************************************************************************/
  519. /* */
  520. /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */
  521. /* */
  522. /************************************************************************/
  523. #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
  524. #define NTC_DO_TAG_QUEUEING 0x10 /* Enable SCSI tag queuing */
  525. #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */
  526. #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
  527. #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
  528. #define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC) */
  529. /* Parity check enable */
  530. /************************************************************************/
  531. /* */
  532. /* Nvram Initiater bits definition */
  533. /* */
  534. /************************************************************************/
  535. #if 0
  536. #define MORE2_DRV BIT0
  537. #define GREATER_1G BIT1
  538. #define RST_SCSI_BUS BIT2
  539. #define ACTIVE_NEGATION BIT3
  540. #define NO_SEEK BIT4
  541. #define LUN_CHECK BIT5
  542. #endif
  543. /************************************************************************/
  544. /* */
  545. /* Nvram Adapter Cfg bits definition */
  546. /* */
  547. /************************************************************************/
  548. #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
  549. #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
  550. #define NAC_GREATER_1G 0x02 /* > 1G support enable */
  551. #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
  552. /* #define NAC_DO_PARITY_CHK 0x08 */ /* Parity check enable */
  553. #endif