rtc-xgene.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * APM X-Gene SoC Real Time Clock Driver
  4. *
  5. * Copyright (c) 2014, Applied Micro Circuits Corporation
  6. * Author: Rameshwar Prasad Sahu <[email protected]>
  7. * Loc Ho <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/rtc.h>
  17. #include <linux/slab.h>
  18. /* RTC CSR Registers */
  19. #define RTC_CCVR 0x00
  20. #define RTC_CMR 0x04
  21. #define RTC_CLR 0x08
  22. #define RTC_CCR 0x0C
  23. #define RTC_CCR_IE BIT(0)
  24. #define RTC_CCR_MASK BIT(1)
  25. #define RTC_CCR_EN BIT(2)
  26. #define RTC_CCR_WEN BIT(3)
  27. #define RTC_STAT 0x10
  28. #define RTC_STAT_BIT BIT(0)
  29. #define RTC_RSTAT 0x14
  30. #define RTC_EOI 0x18
  31. #define RTC_VER 0x1C
  32. struct xgene_rtc_dev {
  33. struct rtc_device *rtc;
  34. void __iomem *csr_base;
  35. struct clk *clk;
  36. unsigned int irq_wake;
  37. unsigned int irq_enabled;
  38. };
  39. static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)
  40. {
  41. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  42. rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
  43. return 0;
  44. }
  45. static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm)
  46. {
  47. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  48. /*
  49. * NOTE: After the following write, the RTC_CCVR is only reflected
  50. * after the update cycle of 1 seconds.
  51. */
  52. writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
  53. readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
  54. return 0;
  55. }
  56. static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  57. {
  58. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  59. /* If possible, CMR should be read here */
  60. rtc_time64_to_tm(0, &alrm->time);
  61. alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
  62. return 0;
  63. }
  64. static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
  65. {
  66. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  67. u32 ccr;
  68. ccr = readl(pdata->csr_base + RTC_CCR);
  69. if (enabled) {
  70. ccr &= ~RTC_CCR_MASK;
  71. ccr |= RTC_CCR_IE;
  72. } else {
  73. ccr &= ~RTC_CCR_IE;
  74. ccr |= RTC_CCR_MASK;
  75. }
  76. writel(ccr, pdata->csr_base + RTC_CCR);
  77. return 0;
  78. }
  79. static int xgene_rtc_alarm_irq_enabled(struct device *dev)
  80. {
  81. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  82. return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
  83. }
  84. static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  85. {
  86. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  87. writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
  88. xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
  89. return 0;
  90. }
  91. static const struct rtc_class_ops xgene_rtc_ops = {
  92. .read_time = xgene_rtc_read_time,
  93. .set_time = xgene_rtc_set_time,
  94. .read_alarm = xgene_rtc_read_alarm,
  95. .set_alarm = xgene_rtc_set_alarm,
  96. .alarm_irq_enable = xgene_rtc_alarm_irq_enable,
  97. };
  98. static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
  99. {
  100. struct xgene_rtc_dev *pdata = id;
  101. /* Check if interrupt asserted */
  102. if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
  103. return IRQ_NONE;
  104. /* Clear interrupt */
  105. readl(pdata->csr_base + RTC_EOI);
  106. rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
  107. return IRQ_HANDLED;
  108. }
  109. static int xgene_rtc_probe(struct platform_device *pdev)
  110. {
  111. struct xgene_rtc_dev *pdata;
  112. int ret;
  113. int irq;
  114. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  115. if (!pdata)
  116. return -ENOMEM;
  117. platform_set_drvdata(pdev, pdata);
  118. pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
  119. if (IS_ERR(pdata->csr_base))
  120. return PTR_ERR(pdata->csr_base);
  121. pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
  122. if (IS_ERR(pdata->rtc))
  123. return PTR_ERR(pdata->rtc);
  124. irq = platform_get_irq(pdev, 0);
  125. if (irq < 0)
  126. return irq;
  127. ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
  128. dev_name(&pdev->dev), pdata);
  129. if (ret) {
  130. dev_err(&pdev->dev, "Could not request IRQ\n");
  131. return ret;
  132. }
  133. pdata->clk = devm_clk_get(&pdev->dev, NULL);
  134. if (IS_ERR(pdata->clk)) {
  135. dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
  136. return -ENODEV;
  137. }
  138. ret = clk_prepare_enable(pdata->clk);
  139. if (ret)
  140. return ret;
  141. /* Turn on the clock and the crystal */
  142. writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
  143. ret = device_init_wakeup(&pdev->dev, 1);
  144. if (ret) {
  145. clk_disable_unprepare(pdata->clk);
  146. return ret;
  147. }
  148. pdata->rtc->ops = &xgene_rtc_ops;
  149. pdata->rtc->range_max = U32_MAX;
  150. ret = devm_rtc_register_device(pdata->rtc);
  151. if (ret) {
  152. clk_disable_unprepare(pdata->clk);
  153. return ret;
  154. }
  155. return 0;
  156. }
  157. static int xgene_rtc_remove(struct platform_device *pdev)
  158. {
  159. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  160. xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
  161. device_init_wakeup(&pdev->dev, 0);
  162. clk_disable_unprepare(pdata->clk);
  163. return 0;
  164. }
  165. static int __maybe_unused xgene_rtc_suspend(struct device *dev)
  166. {
  167. struct platform_device *pdev = to_platform_device(dev);
  168. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  169. int irq;
  170. irq = platform_get_irq(pdev, 0);
  171. /*
  172. * If this RTC alarm will be used for waking the system up,
  173. * don't disable it of course. Else we just disable the alarm
  174. * and await suspension.
  175. */
  176. if (device_may_wakeup(&pdev->dev)) {
  177. if (!enable_irq_wake(irq))
  178. pdata->irq_wake = 1;
  179. } else {
  180. pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
  181. xgene_rtc_alarm_irq_enable(dev, 0);
  182. clk_disable_unprepare(pdata->clk);
  183. }
  184. return 0;
  185. }
  186. static int __maybe_unused xgene_rtc_resume(struct device *dev)
  187. {
  188. struct platform_device *pdev = to_platform_device(dev);
  189. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  190. int irq;
  191. int rc;
  192. irq = platform_get_irq(pdev, 0);
  193. if (device_may_wakeup(&pdev->dev)) {
  194. if (pdata->irq_wake) {
  195. disable_irq_wake(irq);
  196. pdata->irq_wake = 0;
  197. }
  198. } else {
  199. rc = clk_prepare_enable(pdata->clk);
  200. if (rc) {
  201. dev_err(dev, "Unable to enable clock error %d\n", rc);
  202. return rc;
  203. }
  204. xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
  205. }
  206. return 0;
  207. }
  208. static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);
  209. #ifdef CONFIG_OF
  210. static const struct of_device_id xgene_rtc_of_match[] = {
  211. {.compatible = "apm,xgene-rtc" },
  212. { }
  213. };
  214. MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
  215. #endif
  216. static struct platform_driver xgene_rtc_driver = {
  217. .probe = xgene_rtc_probe,
  218. .remove = xgene_rtc_remove,
  219. .driver = {
  220. .name = "xgene-rtc",
  221. .pm = &xgene_rtc_pm_ops,
  222. .of_match_table = of_match_ptr(xgene_rtc_of_match),
  223. },
  224. };
  225. module_platform_driver(xgene_rtc_driver);
  226. MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
  227. MODULE_AUTHOR("Rameshwar Sahu <[email protected]>");
  228. MODULE_LICENSE("GPL");