rtc-sunplus.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * The RTC driver for Sunplus SP7021
  4. *
  5. * Copyright (C) 2019 Sunplus Technology Inc., All rights reseerved.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/clk.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/ktime.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reset.h>
  16. #include <linux/rtc.h>
  17. #define RTC_REG_NAME "rtc"
  18. #define RTC_CTRL 0x40
  19. #define TIMER_FREEZE_MASK_BIT BIT(5 + 16)
  20. #define TIMER_FREEZE BIT(5)
  21. #define DIS_SYS_RST_RTC_MASK_BIT BIT(4 + 16)
  22. #define DIS_SYS_RST_RTC BIT(4)
  23. #define RTC32K_MODE_RESET_MASK_BIT BIT(3 + 16)
  24. #define RTC32K_MODE_RESET BIT(3)
  25. #define ALARM_EN_OVERDUE_MASK_BIT BIT(2 + 16)
  26. #define ALARM_EN_OVERDUE BIT(2)
  27. #define ALARM_EN_PMC_MASK_BIT BIT(1 + 16)
  28. #define ALARM_EN_PMC BIT(1)
  29. #define ALARM_EN_MASK_BIT BIT(0 + 16)
  30. #define ALARM_EN BIT(0)
  31. #define RTC_TIMER_OUT 0x44
  32. #define RTC_DIVIDER 0x48
  33. #define RTC_TIMER_SET 0x4c
  34. #define RTC_ALARM_SET 0x50
  35. #define RTC_USER_DATA 0x54
  36. #define RTC_RESET_RECORD 0x58
  37. #define RTC_BATT_CHARGE_CTRL 0x5c
  38. #define BAT_CHARGE_RSEL_MASK_BIT GENMASK(3 + 16, 2 + 16)
  39. #define BAT_CHARGE_RSEL_MASK GENMASK(3, 2)
  40. #define BAT_CHARGE_RSEL_2K_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 0)
  41. #define BAT_CHARGE_RSEL_250_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 1)
  42. #define BAT_CHARGE_RSEL_50_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 2)
  43. #define BAT_CHARGE_RSEL_0_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 3)
  44. #define BAT_CHARGE_DSEL_MASK_BIT BIT(1 + 16)
  45. #define BAT_CHARGE_DSEL_MASK GENMASK(1, 1)
  46. #define BAT_CHARGE_DSEL_ON FIELD_PREP(BAT_CHARGE_DSEL_MASK, 0)
  47. #define BAT_CHARGE_DSEL_OFF FIELD_PREP(BAT_CHARGE_DSEL_MASK, 1)
  48. #define BAT_CHARGE_EN_MASK_BIT BIT(0 + 16)
  49. #define BAT_CHARGE_EN BIT(0)
  50. #define RTC_TRIM_CTRL 0x60
  51. struct sunplus_rtc {
  52. struct rtc_device *rtc;
  53. struct resource *res;
  54. struct clk *rtcclk;
  55. struct reset_control *rstc;
  56. void __iomem *reg_base;
  57. int irq;
  58. };
  59. static void sp_get_seconds(struct device *dev, unsigned long *secs)
  60. {
  61. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  62. *secs = (unsigned long)readl(sp_rtc->reg_base + RTC_TIMER_OUT);
  63. }
  64. static void sp_set_seconds(struct device *dev, unsigned long secs)
  65. {
  66. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  67. writel((u32)secs, sp_rtc->reg_base + RTC_TIMER_SET);
  68. }
  69. static int sp_rtc_read_time(struct device *dev, struct rtc_time *tm)
  70. {
  71. unsigned long secs;
  72. sp_get_seconds(dev, &secs);
  73. rtc_time64_to_tm(secs, tm);
  74. return 0;
  75. }
  76. static int sp_rtc_set_time(struct device *dev, struct rtc_time *tm)
  77. {
  78. unsigned long secs;
  79. secs = rtc_tm_to_time64(tm);
  80. dev_dbg(dev, "%s, secs = %lu\n", __func__, secs);
  81. sp_set_seconds(dev, secs);
  82. return 0;
  83. }
  84. static int sp_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  85. {
  86. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  87. unsigned long alarm_time;
  88. alarm_time = rtc_tm_to_time64(&alrm->time);
  89. dev_dbg(dev, "%s, alarm_time: %u\n", __func__, (u32)(alarm_time));
  90. writel((u32)alarm_time, sp_rtc->reg_base + RTC_ALARM_SET);
  91. return 0;
  92. }
  93. static int sp_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  94. {
  95. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  96. unsigned int alarm_time;
  97. alarm_time = readl(sp_rtc->reg_base + RTC_ALARM_SET);
  98. dev_dbg(dev, "%s, alarm_time: %u\n", __func__, alarm_time);
  99. if (alarm_time == 0)
  100. alrm->enabled = 0;
  101. else
  102. alrm->enabled = 1;
  103. rtc_time64_to_tm((unsigned long)(alarm_time), &alrm->time);
  104. return 0;
  105. }
  106. static int sp_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  107. {
  108. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  109. if (enabled)
  110. writel((TIMER_FREEZE_MASK_BIT | DIS_SYS_RST_RTC_MASK_BIT |
  111. RTC32K_MODE_RESET_MASK_BIT | ALARM_EN_OVERDUE_MASK_BIT |
  112. ALARM_EN_PMC_MASK_BIT | ALARM_EN_MASK_BIT) |
  113. (DIS_SYS_RST_RTC | ALARM_EN_OVERDUE | ALARM_EN_PMC | ALARM_EN),
  114. sp_rtc->reg_base + RTC_CTRL);
  115. else
  116. writel((ALARM_EN_OVERDUE_MASK_BIT | ALARM_EN_PMC_MASK_BIT | ALARM_EN_MASK_BIT) |
  117. 0x0, sp_rtc->reg_base + RTC_CTRL);
  118. return 0;
  119. }
  120. static const struct rtc_class_ops sp_rtc_ops = {
  121. .read_time = sp_rtc_read_time,
  122. .set_time = sp_rtc_set_time,
  123. .set_alarm = sp_rtc_set_alarm,
  124. .read_alarm = sp_rtc_read_alarm,
  125. .alarm_irq_enable = sp_rtc_alarm_irq_enable,
  126. };
  127. static irqreturn_t sp_rtc_irq_handler(int irq, void *dev_id)
  128. {
  129. struct platform_device *plat_dev = dev_id;
  130. struct sunplus_rtc *sp_rtc = dev_get_drvdata(&plat_dev->dev);
  131. rtc_update_irq(sp_rtc->rtc, 1, RTC_IRQF | RTC_AF);
  132. dev_dbg(&plat_dev->dev, "[RTC] ALARM INT\n");
  133. return IRQ_HANDLED;
  134. }
  135. /*
  136. * -------------------------------------------------------------------------------------
  137. * bat_charge_rsel bat_charge_dsel bat_charge_en Remarks
  138. * x x 0 Disable
  139. * 0 0 1 0.86mA (2K Ohm with diode)
  140. * 1 0 1 1.81mA (250 Ohm with diode)
  141. * 2 0 1 2.07mA (50 Ohm with diode)
  142. * 3 0 1 16.0mA (0 Ohm with diode)
  143. * 0 1 1 1.36mA (2K Ohm without diode)
  144. * 1 1 1 3.99mA (250 Ohm without diode)
  145. * 2 1 1 4.41mA (50 Ohm without diode)
  146. * 3 1 1 16.0mA (0 Ohm without diode)
  147. * -------------------------------------------------------------------------------------
  148. */
  149. static void sp_rtc_set_trickle_charger(struct device dev)
  150. {
  151. struct sunplus_rtc *sp_rtc = dev_get_drvdata(&dev);
  152. u32 ohms, rsel;
  153. u32 chargeable;
  154. if (of_property_read_u32(dev.of_node, "trickle-resistor-ohms", &ohms) ||
  155. of_property_read_u32(dev.of_node, "aux-voltage-chargeable", &chargeable)) {
  156. dev_warn(&dev, "battery charger disabled\n");
  157. return;
  158. }
  159. switch (ohms) {
  160. case 2000:
  161. rsel = BAT_CHARGE_RSEL_2K_OHM;
  162. break;
  163. case 250:
  164. rsel = BAT_CHARGE_RSEL_250_OHM;
  165. break;
  166. case 50:
  167. rsel = BAT_CHARGE_RSEL_50_OHM;
  168. break;
  169. case 0:
  170. rsel = BAT_CHARGE_RSEL_0_OHM;
  171. break;
  172. default:
  173. dev_err(&dev, "invalid charger resistor value (%d)\n", ohms);
  174. return;
  175. }
  176. writel(BAT_CHARGE_RSEL_MASK_BIT | rsel, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
  177. switch (chargeable) {
  178. case 0:
  179. writel(BAT_CHARGE_DSEL_MASK_BIT | BAT_CHARGE_DSEL_OFF,
  180. sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
  181. break;
  182. case 1:
  183. writel(BAT_CHARGE_DSEL_MASK_BIT | BAT_CHARGE_DSEL_ON,
  184. sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
  185. break;
  186. default:
  187. dev_err(&dev, "invalid aux-voltage-chargeable value (%d)\n", chargeable);
  188. return;
  189. }
  190. writel(BAT_CHARGE_EN_MASK_BIT | BAT_CHARGE_EN, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
  191. }
  192. static int sp_rtc_probe(struct platform_device *plat_dev)
  193. {
  194. struct sunplus_rtc *sp_rtc;
  195. int ret;
  196. sp_rtc = devm_kzalloc(&plat_dev->dev, sizeof(*sp_rtc), GFP_KERNEL);
  197. if (!sp_rtc)
  198. return -ENOMEM;
  199. sp_rtc->res = platform_get_resource_byname(plat_dev, IORESOURCE_MEM, RTC_REG_NAME);
  200. sp_rtc->reg_base = devm_ioremap_resource(&plat_dev->dev, sp_rtc->res);
  201. if (IS_ERR(sp_rtc->reg_base))
  202. return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->reg_base),
  203. "%s devm_ioremap_resource fail\n", RTC_REG_NAME);
  204. dev_dbg(&plat_dev->dev, "res = %pR, reg_base = %p\n",
  205. sp_rtc->res, sp_rtc->reg_base);
  206. sp_rtc->irq = platform_get_irq(plat_dev, 0);
  207. if (sp_rtc->irq < 0)
  208. return dev_err_probe(&plat_dev->dev, sp_rtc->irq, "platform_get_irq failed\n");
  209. ret = devm_request_irq(&plat_dev->dev, sp_rtc->irq, sp_rtc_irq_handler,
  210. IRQF_TRIGGER_RISING, "rtc irq", plat_dev);
  211. if (ret)
  212. return dev_err_probe(&plat_dev->dev, ret, "devm_request_irq failed:\n");
  213. sp_rtc->rtcclk = devm_clk_get(&plat_dev->dev, NULL);
  214. if (IS_ERR(sp_rtc->rtcclk))
  215. return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->rtcclk),
  216. "devm_clk_get fail\n");
  217. sp_rtc->rstc = devm_reset_control_get_exclusive(&plat_dev->dev, NULL);
  218. if (IS_ERR(sp_rtc->rstc))
  219. return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->rstc),
  220. "failed to retrieve reset controller\n");
  221. ret = clk_prepare_enable(sp_rtc->rtcclk);
  222. if (ret)
  223. goto free_clk;
  224. ret = reset_control_deassert(sp_rtc->rstc);
  225. if (ret)
  226. goto free_reset_assert;
  227. device_init_wakeup(&plat_dev->dev, 1);
  228. dev_set_drvdata(&plat_dev->dev, sp_rtc);
  229. sp_rtc->rtc = devm_rtc_allocate_device(&plat_dev->dev);
  230. if (IS_ERR(sp_rtc->rtc)) {
  231. ret = PTR_ERR(sp_rtc->rtc);
  232. goto free_reset_assert;
  233. }
  234. sp_rtc->rtc->range_max = U32_MAX;
  235. sp_rtc->rtc->range_min = 0;
  236. sp_rtc->rtc->ops = &sp_rtc_ops;
  237. ret = devm_rtc_register_device(sp_rtc->rtc);
  238. if (ret)
  239. goto free_reset_assert;
  240. /* Setup trickle charger */
  241. if (plat_dev->dev.of_node)
  242. sp_rtc_set_trickle_charger(plat_dev->dev);
  243. /* Keep RTC from system reset */
  244. writel(DIS_SYS_RST_RTC_MASK_BIT | DIS_SYS_RST_RTC, sp_rtc->reg_base + RTC_CTRL);
  245. return 0;
  246. free_reset_assert:
  247. reset_control_assert(sp_rtc->rstc);
  248. free_clk:
  249. clk_disable_unprepare(sp_rtc->rtcclk);
  250. return ret;
  251. }
  252. static int sp_rtc_remove(struct platform_device *plat_dev)
  253. {
  254. struct sunplus_rtc *sp_rtc = dev_get_drvdata(&plat_dev->dev);
  255. device_init_wakeup(&plat_dev->dev, 0);
  256. reset_control_assert(sp_rtc->rstc);
  257. clk_disable_unprepare(sp_rtc->rtcclk);
  258. return 0;
  259. }
  260. #ifdef CONFIG_PM_SLEEP
  261. static int sp_rtc_suspend(struct device *dev)
  262. {
  263. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  264. if (device_may_wakeup(dev))
  265. enable_irq_wake(sp_rtc->irq);
  266. return 0;
  267. }
  268. static int sp_rtc_resume(struct device *dev)
  269. {
  270. struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
  271. if (device_may_wakeup(dev))
  272. disable_irq_wake(sp_rtc->irq);
  273. return 0;
  274. }
  275. #endif
  276. static const struct of_device_id sp_rtc_of_match[] = {
  277. { .compatible = "sunplus,sp7021-rtc" },
  278. { /* sentinel */ }
  279. };
  280. MODULE_DEVICE_TABLE(of, sp_rtc_of_match);
  281. static SIMPLE_DEV_PM_OPS(sp_rtc_pm_ops, sp_rtc_suspend, sp_rtc_resume);
  282. static struct platform_driver sp_rtc_driver = {
  283. .probe = sp_rtc_probe,
  284. .remove = sp_rtc_remove,
  285. .driver = {
  286. .name = "sp7021-rtc",
  287. .of_match_table = sp_rtc_of_match,
  288. .pm = &sp_rtc_pm_ops,
  289. },
  290. };
  291. module_platform_driver(sp_rtc_driver);
  292. MODULE_AUTHOR("Vincent Shih <[email protected]>");
  293. MODULE_DESCRIPTION("Sunplus RTC driver");
  294. MODULE_LICENSE("GPL v2");