rtc-rs5c372.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * An I2C driver for Ricoh RS5C372, R2025S/D and RV5C38[67] RTCs
  4. *
  5. * Copyright (C) 2005 Pavel Mironchik <[email protected]>
  6. * Copyright (C) 2006 Tower Technologies
  7. * Copyright (C) 2008 Paul Mundt
  8. */
  9. #include <linux/i2c.h>
  10. #include <linux/rtc.h>
  11. #include <linux/bcd.h>
  12. #include <linux/slab.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. /*
  16. * Ricoh has a family of I2C based RTCs, which differ only slightly from
  17. * each other. Differences center on pinout (e.g. how many interrupts,
  18. * output clock, etc) and how the control registers are used. The '372
  19. * is significant only because that's the one this driver first supported.
  20. */
  21. #define RS5C372_REG_SECS 0
  22. #define RS5C372_REG_MINS 1
  23. #define RS5C372_REG_HOURS 2
  24. #define RS5C372_REG_WDAY 3
  25. #define RS5C372_REG_DAY 4
  26. #define RS5C372_REG_MONTH 5
  27. #define RS5C372_REG_YEAR 6
  28. #define RS5C372_REG_TRIM 7
  29. # define RS5C372_TRIM_XSL 0x80 /* only if RS5C372[a|b] */
  30. # define RS5C372_TRIM_MASK 0x7F
  31. # define R2221TL_TRIM_DEV (1 << 7) /* only if R2221TL */
  32. # define RS5C372_TRIM_DECR (1 << 6)
  33. #define RS5C_REG_ALARM_A_MIN 8 /* or ALARM_W */
  34. #define RS5C_REG_ALARM_A_HOURS 9
  35. #define RS5C_REG_ALARM_A_WDAY 10
  36. #define RS5C_REG_ALARM_B_MIN 11 /* or ALARM_D */
  37. #define RS5C_REG_ALARM_B_HOURS 12
  38. #define RS5C_REG_ALARM_B_WDAY 13 /* (ALARM_B only) */
  39. #define RS5C_REG_CTRL1 14
  40. # define RS5C_CTRL1_AALE (1 << 7) /* or WALE */
  41. # define RS5C_CTRL1_BALE (1 << 6) /* or DALE */
  42. # define RV5C387_CTRL1_24 (1 << 5)
  43. # define RS5C372A_CTRL1_SL1 (1 << 5)
  44. # define RS5C_CTRL1_CT_MASK (7 << 0)
  45. # define RS5C_CTRL1_CT0 (0 << 0) /* no periodic irq */
  46. # define RS5C_CTRL1_CT4 (4 << 0) /* 1 Hz level irq */
  47. #define RS5C_REG_CTRL2 15
  48. # define RS5C372_CTRL2_24 (1 << 5)
  49. # define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2x2x */
  50. # define R2x2x_CTRL2_VDET (1 << 6) /* only if R2x2x */
  51. # define R2x2x_CTRL2_XSTP (1 << 5) /* only if R2x2x */
  52. # define R2x2x_CTRL2_PON (1 << 4) /* only if R2x2x */
  53. # define RS5C_CTRL2_CTFG (1 << 2)
  54. # define RS5C_CTRL2_AAFG (1 << 1) /* or WAFG */
  55. # define RS5C_CTRL2_BAFG (1 << 0) /* or DAFG */
  56. /* to read (style 1) or write registers starting at R */
  57. #define RS5C_ADDR(R) (((R) << 4) | 0)
  58. enum rtc_type {
  59. rtc_undef = 0,
  60. rtc_r2025sd,
  61. rtc_r2221tl,
  62. rtc_rs5c372a,
  63. rtc_rs5c372b,
  64. rtc_rv5c386,
  65. rtc_rv5c387a,
  66. };
  67. static const struct i2c_device_id rs5c372_id[] = {
  68. { "r2025sd", rtc_r2025sd },
  69. { "r2221tl", rtc_r2221tl },
  70. { "rs5c372a", rtc_rs5c372a },
  71. { "rs5c372b", rtc_rs5c372b },
  72. { "rv5c386", rtc_rv5c386 },
  73. { "rv5c387a", rtc_rv5c387a },
  74. { }
  75. };
  76. MODULE_DEVICE_TABLE(i2c, rs5c372_id);
  77. static const __maybe_unused struct of_device_id rs5c372_of_match[] = {
  78. {
  79. .compatible = "ricoh,r2025sd",
  80. .data = (void *)rtc_r2025sd
  81. },
  82. {
  83. .compatible = "ricoh,r2221tl",
  84. .data = (void *)rtc_r2221tl
  85. },
  86. {
  87. .compatible = "ricoh,rs5c372a",
  88. .data = (void *)rtc_rs5c372a
  89. },
  90. {
  91. .compatible = "ricoh,rs5c372b",
  92. .data = (void *)rtc_rs5c372b
  93. },
  94. {
  95. .compatible = "ricoh,rv5c386",
  96. .data = (void *)rtc_rv5c386
  97. },
  98. {
  99. .compatible = "ricoh,rv5c387a",
  100. .data = (void *)rtc_rv5c387a
  101. },
  102. { }
  103. };
  104. MODULE_DEVICE_TABLE(of, rs5c372_of_match);
  105. /* REVISIT: this assumes that:
  106. * - we're in the 21st century, so it's safe to ignore the century
  107. * bit for rv5c38[67] (REG_MONTH bit 7);
  108. * - we should use ALARM_A not ALARM_B (may be wrong on some boards)
  109. */
  110. struct rs5c372 {
  111. struct i2c_client *client;
  112. struct rtc_device *rtc;
  113. enum rtc_type type;
  114. unsigned time24:1;
  115. unsigned has_irq:1;
  116. unsigned smbus:1;
  117. char buf[17];
  118. char *regs;
  119. };
  120. static int rs5c_get_regs(struct rs5c372 *rs5c)
  121. {
  122. struct i2c_client *client = rs5c->client;
  123. struct i2c_msg msgs[] = {
  124. {
  125. .addr = client->addr,
  126. .flags = I2C_M_RD,
  127. .len = sizeof(rs5c->buf),
  128. .buf = rs5c->buf
  129. },
  130. };
  131. /* This implements the third reading method from the datasheet, using
  132. * an internal address that's reset after each transaction (by STOP)
  133. * to 0x0f ... so we read extra registers, and skip the first one.
  134. *
  135. * The first method doesn't work with the iop3xx adapter driver, on at
  136. * least 80219 chips; this works around that bug.
  137. *
  138. * The third method on the other hand doesn't work for the SMBus-only
  139. * configurations, so we use the the first method there, stripping off
  140. * the extra register in the process.
  141. */
  142. if (rs5c->smbus) {
  143. int addr = RS5C_ADDR(RS5C372_REG_SECS);
  144. int size = sizeof(rs5c->buf) - 1;
  145. if (i2c_smbus_read_i2c_block_data(client, addr, size,
  146. rs5c->buf + 1) != size) {
  147. dev_warn(&client->dev, "can't read registers\n");
  148. return -EIO;
  149. }
  150. } else {
  151. if ((i2c_transfer(client->adapter, msgs, 1)) != 1) {
  152. dev_warn(&client->dev, "can't read registers\n");
  153. return -EIO;
  154. }
  155. }
  156. dev_dbg(&client->dev,
  157. "%3ph (%02x) %3ph (%02x), %3ph, %3ph; %02x %02x\n",
  158. rs5c->regs + 0, rs5c->regs[3],
  159. rs5c->regs + 4, rs5c->regs[7],
  160. rs5c->regs + 8, rs5c->regs + 11,
  161. rs5c->regs[14], rs5c->regs[15]);
  162. return 0;
  163. }
  164. static unsigned rs5c_reg2hr(struct rs5c372 *rs5c, unsigned reg)
  165. {
  166. unsigned hour;
  167. if (rs5c->time24)
  168. return bcd2bin(reg & 0x3f);
  169. hour = bcd2bin(reg & 0x1f);
  170. if (hour == 12)
  171. hour = 0;
  172. if (reg & 0x20)
  173. hour += 12;
  174. return hour;
  175. }
  176. static unsigned rs5c_hr2reg(struct rs5c372 *rs5c, unsigned hour)
  177. {
  178. if (rs5c->time24)
  179. return bin2bcd(hour);
  180. if (hour > 12)
  181. return 0x20 | bin2bcd(hour - 12);
  182. if (hour == 12)
  183. return 0x20 | bin2bcd(12);
  184. if (hour == 0)
  185. return bin2bcd(12);
  186. return bin2bcd(hour);
  187. }
  188. static int rs5c372_rtc_read_time(struct device *dev, struct rtc_time *tm)
  189. {
  190. struct i2c_client *client = to_i2c_client(dev);
  191. struct rs5c372 *rs5c = i2c_get_clientdata(client);
  192. int status = rs5c_get_regs(rs5c);
  193. unsigned char ctrl2 = rs5c->regs[RS5C_REG_CTRL2];
  194. if (status < 0)
  195. return status;
  196. switch (rs5c->type) {
  197. case rtc_r2025sd:
  198. case rtc_r2221tl:
  199. if ((rs5c->type == rtc_r2025sd && !(ctrl2 & R2x2x_CTRL2_XSTP)) ||
  200. (rs5c->type == rtc_r2221tl && (ctrl2 & R2x2x_CTRL2_XSTP))) {
  201. dev_warn(&client->dev, "rtc oscillator interruption detected. Please reset the rtc clock.\n");
  202. return -EINVAL;
  203. }
  204. break;
  205. default:
  206. if (ctrl2 & RS5C_CTRL2_XSTP) {
  207. dev_warn(&client->dev, "rtc oscillator interruption detected. Please reset the rtc clock.\n");
  208. return -EINVAL;
  209. }
  210. }
  211. tm->tm_sec = bcd2bin(rs5c->regs[RS5C372_REG_SECS] & 0x7f);
  212. tm->tm_min = bcd2bin(rs5c->regs[RS5C372_REG_MINS] & 0x7f);
  213. tm->tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C372_REG_HOURS]);
  214. tm->tm_wday = bcd2bin(rs5c->regs[RS5C372_REG_WDAY] & 0x07);
  215. tm->tm_mday = bcd2bin(rs5c->regs[RS5C372_REG_DAY] & 0x3f);
  216. /* tm->tm_mon is zero-based */
  217. tm->tm_mon = bcd2bin(rs5c->regs[RS5C372_REG_MONTH] & 0x1f) - 1;
  218. /* year is 1900 + tm->tm_year */
  219. tm->tm_year = bcd2bin(rs5c->regs[RS5C372_REG_YEAR]) + 100;
  220. dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  221. "mday=%d, mon=%d, year=%d, wday=%d\n",
  222. __func__,
  223. tm->tm_sec, tm->tm_min, tm->tm_hour,
  224. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  225. return 0;
  226. }
  227. static int rs5c372_rtc_set_time(struct device *dev, struct rtc_time *tm)
  228. {
  229. struct i2c_client *client = to_i2c_client(dev);
  230. struct rs5c372 *rs5c = i2c_get_clientdata(client);
  231. unsigned char buf[7];
  232. unsigned char ctrl2;
  233. int addr;
  234. dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d "
  235. "mday=%d, mon=%d, year=%d, wday=%d\n",
  236. __func__,
  237. tm->tm_sec, tm->tm_min, tm->tm_hour,
  238. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  239. addr = RS5C_ADDR(RS5C372_REG_SECS);
  240. buf[0] = bin2bcd(tm->tm_sec);
  241. buf[1] = bin2bcd(tm->tm_min);
  242. buf[2] = rs5c_hr2reg(rs5c, tm->tm_hour);
  243. buf[3] = bin2bcd(tm->tm_wday);
  244. buf[4] = bin2bcd(tm->tm_mday);
  245. buf[5] = bin2bcd(tm->tm_mon + 1);
  246. buf[6] = bin2bcd(tm->tm_year - 100);
  247. if (i2c_smbus_write_i2c_block_data(client, addr, sizeof(buf), buf) < 0) {
  248. dev_dbg(&client->dev, "%s: write error in line %i\n",
  249. __func__, __LINE__);
  250. return -EIO;
  251. }
  252. addr = RS5C_ADDR(RS5C_REG_CTRL2);
  253. ctrl2 = i2c_smbus_read_byte_data(client, addr);
  254. /* clear rtc warning bits */
  255. switch (rs5c->type) {
  256. case rtc_r2025sd:
  257. case rtc_r2221tl:
  258. ctrl2 &= ~(R2x2x_CTRL2_VDET | R2x2x_CTRL2_PON);
  259. if (rs5c->type == rtc_r2025sd)
  260. ctrl2 |= R2x2x_CTRL2_XSTP;
  261. else
  262. ctrl2 &= ~R2x2x_CTRL2_XSTP;
  263. break;
  264. default:
  265. ctrl2 &= ~RS5C_CTRL2_XSTP;
  266. break;
  267. }
  268. if (i2c_smbus_write_byte_data(client, addr, ctrl2) < 0) {
  269. dev_dbg(&client->dev, "%s: write error in line %i\n",
  270. __func__, __LINE__);
  271. return -EIO;
  272. }
  273. return 0;
  274. }
  275. #if IS_ENABLED(CONFIG_RTC_INTF_PROC)
  276. #define NEED_TRIM
  277. #endif
  278. #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS)
  279. #define NEED_TRIM
  280. #endif
  281. #ifdef NEED_TRIM
  282. static int rs5c372_get_trim(struct i2c_client *client, int *osc, int *trim)
  283. {
  284. struct rs5c372 *rs5c372 = i2c_get_clientdata(client);
  285. u8 tmp = rs5c372->regs[RS5C372_REG_TRIM];
  286. if (osc) {
  287. if (rs5c372->type == rtc_rs5c372a || rs5c372->type == rtc_rs5c372b)
  288. *osc = (tmp & RS5C372_TRIM_XSL) ? 32000 : 32768;
  289. else
  290. *osc = 32768;
  291. }
  292. if (trim) {
  293. dev_dbg(&client->dev, "%s: raw trim=%x\n", __func__, tmp);
  294. tmp &= RS5C372_TRIM_MASK;
  295. if (tmp & 0x3e) {
  296. int t = tmp & 0x3f;
  297. if (tmp & 0x40)
  298. t = (~t | (s8)0xc0) + 1;
  299. else
  300. t = t - 1;
  301. tmp = t * 2;
  302. } else
  303. tmp = 0;
  304. *trim = tmp;
  305. }
  306. return 0;
  307. }
  308. #endif
  309. static int rs5c_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  310. {
  311. struct i2c_client *client = to_i2c_client(dev);
  312. struct rs5c372 *rs5c = i2c_get_clientdata(client);
  313. unsigned char buf;
  314. int status, addr;
  315. buf = rs5c->regs[RS5C_REG_CTRL1];
  316. if (!rs5c->has_irq)
  317. return -EINVAL;
  318. status = rs5c_get_regs(rs5c);
  319. if (status < 0)
  320. return status;
  321. addr = RS5C_ADDR(RS5C_REG_CTRL1);
  322. if (enabled)
  323. buf |= RS5C_CTRL1_AALE;
  324. else
  325. buf &= ~RS5C_CTRL1_AALE;
  326. if (i2c_smbus_write_byte_data(client, addr, buf) < 0) {
  327. dev_warn(dev, "can't update alarm\n");
  328. status = -EIO;
  329. } else
  330. rs5c->regs[RS5C_REG_CTRL1] = buf;
  331. return status;
  332. }
  333. /* NOTE: Since RTC_WKALM_{RD,SET} were originally defined for EFI,
  334. * which only exposes a polled programming interface; and since
  335. * these calls map directly to those EFI requests; we don't demand
  336. * we have an IRQ for this chip when we go through this API.
  337. *
  338. * The older x86_pc derived RTC_ALM_{READ,SET} calls require irqs
  339. * though, managed through RTC_AIE_{ON,OFF} requests.
  340. */
  341. static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  342. {
  343. struct i2c_client *client = to_i2c_client(dev);
  344. struct rs5c372 *rs5c = i2c_get_clientdata(client);
  345. int status;
  346. status = rs5c_get_regs(rs5c);
  347. if (status < 0)
  348. return status;
  349. /* report alarm time */
  350. t->time.tm_sec = 0;
  351. t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f);
  352. t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]);
  353. /* ... and status */
  354. t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE);
  355. t->pending = !!(rs5c->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_AAFG);
  356. return 0;
  357. }
  358. static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  359. {
  360. struct i2c_client *client = to_i2c_client(dev);
  361. struct rs5c372 *rs5c = i2c_get_clientdata(client);
  362. int status, addr, i;
  363. unsigned char buf[3];
  364. /* only handle up to 24 hours in the future, like RTC_ALM_SET */
  365. if (t->time.tm_mday != -1
  366. || t->time.tm_mon != -1
  367. || t->time.tm_year != -1)
  368. return -EINVAL;
  369. /* REVISIT: round up tm_sec */
  370. /* if needed, disable irq (clears pending status) */
  371. status = rs5c_get_regs(rs5c);
  372. if (status < 0)
  373. return status;
  374. if (rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE) {
  375. addr = RS5C_ADDR(RS5C_REG_CTRL1);
  376. buf[0] = rs5c->regs[RS5C_REG_CTRL1] & ~RS5C_CTRL1_AALE;
  377. if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) {
  378. dev_dbg(dev, "can't disable alarm\n");
  379. return -EIO;
  380. }
  381. rs5c->regs[RS5C_REG_CTRL1] = buf[0];
  382. }
  383. /* set alarm */
  384. buf[0] = bin2bcd(t->time.tm_min);
  385. buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour);
  386. buf[2] = 0x7f; /* any/all days */
  387. for (i = 0; i < sizeof(buf); i++) {
  388. addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i);
  389. if (i2c_smbus_write_byte_data(client, addr, buf[i]) < 0) {
  390. dev_dbg(dev, "can't set alarm time\n");
  391. return -EIO;
  392. }
  393. }
  394. /* ... and maybe enable its irq */
  395. if (t->enabled) {
  396. addr = RS5C_ADDR(RS5C_REG_CTRL1);
  397. buf[0] = rs5c->regs[RS5C_REG_CTRL1] | RS5C_CTRL1_AALE;
  398. if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0)
  399. dev_warn(dev, "can't enable alarm\n");
  400. rs5c->regs[RS5C_REG_CTRL1] = buf[0];
  401. }
  402. return 0;
  403. }
  404. #if IS_ENABLED(CONFIG_RTC_INTF_PROC)
  405. static int rs5c372_rtc_proc(struct device *dev, struct seq_file *seq)
  406. {
  407. int err, osc, trim;
  408. err = rs5c372_get_trim(to_i2c_client(dev), &osc, &trim);
  409. if (err == 0) {
  410. seq_printf(seq, "crystal\t\t: %d.%03d KHz\n",
  411. osc / 1000, osc % 1000);
  412. seq_printf(seq, "trim\t\t: %d\n", trim);
  413. }
  414. return 0;
  415. }
  416. #else
  417. #define rs5c372_rtc_proc NULL
  418. #endif
  419. #ifdef CONFIG_RTC_INTF_DEV
  420. static int rs5c372_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  421. {
  422. struct rs5c372 *rs5c = i2c_get_clientdata(to_i2c_client(dev));
  423. unsigned char ctrl2;
  424. int addr;
  425. unsigned int flags;
  426. dev_dbg(dev, "%s: cmd=%x\n", __func__, cmd);
  427. addr = RS5C_ADDR(RS5C_REG_CTRL2);
  428. ctrl2 = i2c_smbus_read_byte_data(rs5c->client, addr);
  429. switch (cmd) {
  430. case RTC_VL_READ:
  431. flags = 0;
  432. switch (rs5c->type) {
  433. case rtc_r2025sd:
  434. case rtc_r2221tl:
  435. if ((rs5c->type == rtc_r2025sd && !(ctrl2 & R2x2x_CTRL2_XSTP)) ||
  436. (rs5c->type == rtc_r2221tl && (ctrl2 & R2x2x_CTRL2_XSTP))) {
  437. flags |= RTC_VL_DATA_INVALID;
  438. }
  439. if (ctrl2 & R2x2x_CTRL2_VDET)
  440. flags |= RTC_VL_BACKUP_LOW;
  441. break;
  442. default:
  443. if (ctrl2 & RS5C_CTRL2_XSTP)
  444. flags |= RTC_VL_DATA_INVALID;
  445. break;
  446. }
  447. return put_user(flags, (unsigned int __user *)arg);
  448. case RTC_VL_CLR:
  449. /* clear VDET bit */
  450. if (rs5c->type == rtc_r2025sd || rs5c->type == rtc_r2221tl) {
  451. ctrl2 &= ~R2x2x_CTRL2_VDET;
  452. if (i2c_smbus_write_byte_data(rs5c->client, addr, ctrl2) < 0) {
  453. dev_dbg(&rs5c->client->dev, "%s: write error in line %i\n",
  454. __func__, __LINE__);
  455. return -EIO;
  456. }
  457. }
  458. return 0;
  459. default:
  460. return -ENOIOCTLCMD;
  461. }
  462. return 0;
  463. }
  464. #else
  465. #define rs5c372_ioctl NULL
  466. #endif
  467. static int rs5c372_read_offset(struct device *dev, long *offset)
  468. {
  469. struct rs5c372 *rs5c = i2c_get_clientdata(to_i2c_client(dev));
  470. u8 val = rs5c->regs[RS5C372_REG_TRIM];
  471. long ppb_per_step = 0;
  472. bool decr = val & RS5C372_TRIM_DECR;
  473. switch (rs5c->type) {
  474. case rtc_r2221tl:
  475. ppb_per_step = val & R2221TL_TRIM_DEV ? 1017 : 3051;
  476. break;
  477. case rtc_rs5c372a:
  478. case rtc_rs5c372b:
  479. ppb_per_step = val & RS5C372_TRIM_XSL ? 3125 : 3051;
  480. break;
  481. default:
  482. ppb_per_step = 3051;
  483. break;
  484. }
  485. /* Only bits[0:5] repsents the time counts */
  486. val &= 0x3F;
  487. /* If bits[1:5] are all 0, it means no increment or decrement */
  488. if (!(val & 0x3E)) {
  489. *offset = 0;
  490. } else {
  491. if (decr)
  492. *offset = -(((~val) & 0x3F) + 1) * ppb_per_step;
  493. else
  494. *offset = (val - 1) * ppb_per_step;
  495. }
  496. return 0;
  497. }
  498. static int rs5c372_set_offset(struct device *dev, long offset)
  499. {
  500. struct rs5c372 *rs5c = i2c_get_clientdata(to_i2c_client(dev));
  501. int addr = RS5C_ADDR(RS5C372_REG_TRIM);
  502. u8 val = 0;
  503. u8 tmp = 0;
  504. long ppb_per_step = 3051;
  505. long steps = LONG_MIN;
  506. switch (rs5c->type) {
  507. case rtc_rs5c372a:
  508. case rtc_rs5c372b:
  509. tmp = rs5c->regs[RS5C372_REG_TRIM];
  510. if (tmp & RS5C372_TRIM_XSL) {
  511. ppb_per_step = 3125;
  512. val |= RS5C372_TRIM_XSL;
  513. }
  514. break;
  515. case rtc_r2221tl:
  516. /*
  517. * Check if it is possible to use high resolution mode (DEV=1).
  518. * In this mode, the minimum resolution is 2 / (32768 * 20 * 3),
  519. * which is about 1017 ppb.
  520. */
  521. steps = DIV_ROUND_CLOSEST(offset, 1017);
  522. if (steps >= -0x3E && steps <= 0x3E) {
  523. ppb_per_step = 1017;
  524. val |= R2221TL_TRIM_DEV;
  525. } else {
  526. /*
  527. * offset is out of the range of high resolution mode.
  528. * Try to use low resolution mode (DEV=0). In this mode,
  529. * the minimum resolution is 2 / (32768 * 20), which is
  530. * about 3051 ppb.
  531. */
  532. steps = LONG_MIN;
  533. }
  534. break;
  535. default:
  536. break;
  537. }
  538. if (steps == LONG_MIN) {
  539. steps = DIV_ROUND_CLOSEST(offset, ppb_per_step);
  540. if (steps > 0x3E || steps < -0x3E)
  541. return -ERANGE;
  542. }
  543. if (steps > 0) {
  544. val |= steps + 1;
  545. } else {
  546. val |= RS5C372_TRIM_DECR;
  547. val |= (~(-steps - 1)) & 0x3F;
  548. }
  549. if (!steps || !(val & 0x3E)) {
  550. /*
  551. * if offset is too small, set oscillation adjustment register
  552. * or time trimming register with its default value whic means
  553. * no increment or decrement. But for rs5c372[a|b], the XSL bit
  554. * should be kept unchanged.
  555. */
  556. if (rs5c->type == rtc_rs5c372a || rs5c->type == rtc_rs5c372b)
  557. val &= RS5C372_TRIM_XSL;
  558. else
  559. val = 0;
  560. }
  561. dev_dbg(&rs5c->client->dev, "write 0x%x for offset %ld\n", val, offset);
  562. if (i2c_smbus_write_byte_data(rs5c->client, addr, val) < 0) {
  563. dev_err(&rs5c->client->dev, "failed to write 0x%x to reg %d\n", val, addr);
  564. return -EIO;
  565. }
  566. rs5c->regs[RS5C372_REG_TRIM] = val;
  567. return 0;
  568. }
  569. static const struct rtc_class_ops rs5c372_rtc_ops = {
  570. .proc = rs5c372_rtc_proc,
  571. .read_time = rs5c372_rtc_read_time,
  572. .set_time = rs5c372_rtc_set_time,
  573. .read_alarm = rs5c_read_alarm,
  574. .set_alarm = rs5c_set_alarm,
  575. .alarm_irq_enable = rs5c_rtc_alarm_irq_enable,
  576. .ioctl = rs5c372_ioctl,
  577. .read_offset = rs5c372_read_offset,
  578. .set_offset = rs5c372_set_offset,
  579. };
  580. #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS)
  581. static ssize_t rs5c372_sysfs_show_trim(struct device *dev,
  582. struct device_attribute *attr, char *buf)
  583. {
  584. int err, trim;
  585. err = rs5c372_get_trim(to_i2c_client(dev), NULL, &trim);
  586. if (err)
  587. return err;
  588. return sprintf(buf, "%d\n", trim);
  589. }
  590. static DEVICE_ATTR(trim, S_IRUGO, rs5c372_sysfs_show_trim, NULL);
  591. static ssize_t rs5c372_sysfs_show_osc(struct device *dev,
  592. struct device_attribute *attr, char *buf)
  593. {
  594. int err, osc;
  595. err = rs5c372_get_trim(to_i2c_client(dev), &osc, NULL);
  596. if (err)
  597. return err;
  598. return sprintf(buf, "%d.%03d KHz\n", osc / 1000, osc % 1000);
  599. }
  600. static DEVICE_ATTR(osc, S_IRUGO, rs5c372_sysfs_show_osc, NULL);
  601. static int rs5c_sysfs_register(struct device *dev)
  602. {
  603. int err;
  604. err = device_create_file(dev, &dev_attr_trim);
  605. if (err)
  606. return err;
  607. err = device_create_file(dev, &dev_attr_osc);
  608. if (err)
  609. device_remove_file(dev, &dev_attr_trim);
  610. return err;
  611. }
  612. static void rs5c_sysfs_unregister(struct device *dev)
  613. {
  614. device_remove_file(dev, &dev_attr_trim);
  615. device_remove_file(dev, &dev_attr_osc);
  616. }
  617. #else
  618. static int rs5c_sysfs_register(struct device *dev)
  619. {
  620. return 0;
  621. }
  622. static void rs5c_sysfs_unregister(struct device *dev)
  623. {
  624. /* nothing */
  625. }
  626. #endif /* SYSFS */
  627. static struct i2c_driver rs5c372_driver;
  628. static int rs5c_oscillator_setup(struct rs5c372 *rs5c372)
  629. {
  630. unsigned char buf[2];
  631. int addr, i, ret = 0;
  632. addr = RS5C_ADDR(RS5C_REG_CTRL1);
  633. buf[0] = rs5c372->regs[RS5C_REG_CTRL1];
  634. buf[1] = rs5c372->regs[RS5C_REG_CTRL2];
  635. switch (rs5c372->type) {
  636. case rtc_r2025sd:
  637. if (buf[1] & R2x2x_CTRL2_XSTP)
  638. return ret;
  639. break;
  640. case rtc_r2221tl:
  641. if (!(buf[1] & R2x2x_CTRL2_XSTP))
  642. return ret;
  643. break;
  644. default:
  645. if (!(buf[1] & RS5C_CTRL2_XSTP))
  646. return ret;
  647. break;
  648. }
  649. /* use 24hr mode */
  650. switch (rs5c372->type) {
  651. case rtc_rs5c372a:
  652. case rtc_rs5c372b:
  653. buf[1] |= RS5C372_CTRL2_24;
  654. rs5c372->time24 = 1;
  655. break;
  656. case rtc_r2025sd:
  657. case rtc_r2221tl:
  658. case rtc_rv5c386:
  659. case rtc_rv5c387a:
  660. buf[0] |= RV5C387_CTRL1_24;
  661. rs5c372->time24 = 1;
  662. break;
  663. default:
  664. /* impossible */
  665. break;
  666. }
  667. for (i = 0; i < sizeof(buf); i++) {
  668. addr = RS5C_ADDR(RS5C_REG_CTRL1 + i);
  669. ret = i2c_smbus_write_byte_data(rs5c372->client, addr, buf[i]);
  670. if (unlikely(ret < 0))
  671. return ret;
  672. }
  673. rs5c372->regs[RS5C_REG_CTRL1] = buf[0];
  674. rs5c372->regs[RS5C_REG_CTRL2] = buf[1];
  675. return 0;
  676. }
  677. static int rs5c372_probe(struct i2c_client *client,
  678. const struct i2c_device_id *id)
  679. {
  680. int err = 0;
  681. int smbus_mode = 0;
  682. struct rs5c372 *rs5c372;
  683. dev_dbg(&client->dev, "%s\n", __func__);
  684. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
  685. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) {
  686. /*
  687. * If we don't have any master mode adapter, try breaking
  688. * it down in to the barest of capabilities.
  689. */
  690. if (i2c_check_functionality(client->adapter,
  691. I2C_FUNC_SMBUS_BYTE_DATA |
  692. I2C_FUNC_SMBUS_I2C_BLOCK))
  693. smbus_mode = 1;
  694. else {
  695. /* Still no good, give up */
  696. err = -ENODEV;
  697. goto exit;
  698. }
  699. }
  700. rs5c372 = devm_kzalloc(&client->dev, sizeof(struct rs5c372),
  701. GFP_KERNEL);
  702. if (!rs5c372) {
  703. err = -ENOMEM;
  704. goto exit;
  705. }
  706. rs5c372->client = client;
  707. i2c_set_clientdata(client, rs5c372);
  708. if (client->dev.of_node)
  709. rs5c372->type = (enum rtc_type)
  710. of_device_get_match_data(&client->dev);
  711. else
  712. rs5c372->type = id->driver_data;
  713. /* we read registers 0x0f then 0x00-0x0f; skip the first one */
  714. rs5c372->regs = &rs5c372->buf[1];
  715. rs5c372->smbus = smbus_mode;
  716. err = rs5c_get_regs(rs5c372);
  717. if (err < 0)
  718. goto exit;
  719. /* clock may be set for am/pm or 24 hr time */
  720. switch (rs5c372->type) {
  721. case rtc_rs5c372a:
  722. case rtc_rs5c372b:
  723. /* alarm uses ALARM_A; and nINTRA on 372a, nINTR on 372b.
  724. * so does periodic irq, except some 327a modes.
  725. */
  726. if (rs5c372->regs[RS5C_REG_CTRL2] & RS5C372_CTRL2_24)
  727. rs5c372->time24 = 1;
  728. break;
  729. case rtc_r2025sd:
  730. case rtc_r2221tl:
  731. case rtc_rv5c386:
  732. case rtc_rv5c387a:
  733. if (rs5c372->regs[RS5C_REG_CTRL1] & RV5C387_CTRL1_24)
  734. rs5c372->time24 = 1;
  735. /* alarm uses ALARM_W; and nINTRB for alarm and periodic
  736. * irq, on both 386 and 387
  737. */
  738. break;
  739. default:
  740. dev_err(&client->dev, "unknown RTC type\n");
  741. goto exit;
  742. }
  743. /* if the oscillator lost power and no other software (like
  744. * the bootloader) set it up, do it here.
  745. *
  746. * The R2025S/D does this a little differently than the other
  747. * parts, so we special case that..
  748. */
  749. err = rs5c_oscillator_setup(rs5c372);
  750. if (unlikely(err < 0)) {
  751. dev_err(&client->dev, "setup error\n");
  752. goto exit;
  753. }
  754. dev_info(&client->dev, "%s found, %s\n",
  755. ({ char *s; switch (rs5c372->type) {
  756. case rtc_r2025sd: s = "r2025sd"; break;
  757. case rtc_r2221tl: s = "r2221tl"; break;
  758. case rtc_rs5c372a: s = "rs5c372a"; break;
  759. case rtc_rs5c372b: s = "rs5c372b"; break;
  760. case rtc_rv5c386: s = "rv5c386"; break;
  761. case rtc_rv5c387a: s = "rv5c387a"; break;
  762. default: s = "chip"; break;
  763. }; s;}),
  764. rs5c372->time24 ? "24hr" : "am/pm"
  765. );
  766. /* REVISIT use client->irq to register alarm irq ... */
  767. rs5c372->rtc = devm_rtc_device_register(&client->dev,
  768. rs5c372_driver.driver.name,
  769. &rs5c372_rtc_ops, THIS_MODULE);
  770. if (IS_ERR(rs5c372->rtc)) {
  771. err = PTR_ERR(rs5c372->rtc);
  772. goto exit;
  773. }
  774. err = rs5c_sysfs_register(&client->dev);
  775. if (err)
  776. goto exit;
  777. return 0;
  778. exit:
  779. return err;
  780. }
  781. static void rs5c372_remove(struct i2c_client *client)
  782. {
  783. rs5c_sysfs_unregister(&client->dev);
  784. }
  785. static struct i2c_driver rs5c372_driver = {
  786. .driver = {
  787. .name = "rtc-rs5c372",
  788. .of_match_table = of_match_ptr(rs5c372_of_match),
  789. },
  790. .probe = rs5c372_probe,
  791. .remove = rs5c372_remove,
  792. .id_table = rs5c372_id,
  793. };
  794. module_i2c_driver(rs5c372_driver);
  795. MODULE_AUTHOR(
  796. "Pavel Mironchik <[email protected]>, "
  797. "Alessandro Zummo <[email protected]>, "
  798. "Paul Mundt <[email protected]>");
  799. MODULE_DESCRIPTION("Ricoh RS5C372 RTC driver");
  800. MODULE_LICENSE("GPL");