rtc-ds1685.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
  4. * chips.
  5. *
  6. * Copyright (C) 2011-2014 Joshua Kinard <[email protected]>.
  7. * Copyright (C) 2009 Matthias Fuchs <[email protected]>.
  8. *
  9. * References:
  10. * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
  11. * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
  12. * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
  13. * Application Note 90, Using the Multiplex Bus RTC Extended Features.
  14. */
  15. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16. #include <linux/bcd.h>
  17. #include <linux/delay.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/rtc.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/rtc/ds1685.h>
  24. #ifdef CONFIG_PROC_FS
  25. #include <linux/proc_fs.h>
  26. #endif
  27. /* ----------------------------------------------------------------------- */
  28. /*
  29. * Standard read/write
  30. * all registers are mapped in CPU address space
  31. */
  32. /**
  33. * ds1685_read - read a value from an rtc register.
  34. * @rtc: pointer to the ds1685 rtc structure.
  35. * @reg: the register address to read.
  36. */
  37. static u8
  38. ds1685_read(struct ds1685_priv *rtc, int reg)
  39. {
  40. return readb((u8 __iomem *)rtc->regs +
  41. (reg * rtc->regstep));
  42. }
  43. /**
  44. * ds1685_write - write a value to an rtc register.
  45. * @rtc: pointer to the ds1685 rtc structure.
  46. * @reg: the register address to write.
  47. * @value: value to write to the register.
  48. */
  49. static void
  50. ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
  51. {
  52. writeb(value, ((u8 __iomem *)rtc->regs +
  53. (reg * rtc->regstep)));
  54. }
  55. /* ----------------------------------------------------------------------- */
  56. /*
  57. * Indirect read/write functions
  58. * access happens via address and data register mapped in CPU address space
  59. */
  60. /**
  61. * ds1685_indirect_read - read a value from an rtc register.
  62. * @rtc: pointer to the ds1685 rtc structure.
  63. * @reg: the register address to read.
  64. */
  65. static u8
  66. ds1685_indirect_read(struct ds1685_priv *rtc, int reg)
  67. {
  68. writeb(reg, rtc->regs);
  69. return readb(rtc->data);
  70. }
  71. /**
  72. * ds1685_indirect_write - write a value to an rtc register.
  73. * @rtc: pointer to the ds1685 rtc structure.
  74. * @reg: the register address to write.
  75. * @value: value to write to the register.
  76. */
  77. static void
  78. ds1685_indirect_write(struct ds1685_priv *rtc, int reg, u8 value)
  79. {
  80. writeb(reg, rtc->regs);
  81. writeb(value, rtc->data);
  82. }
  83. /* ----------------------------------------------------------------------- */
  84. /* Inlined functions */
  85. /**
  86. * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
  87. * @rtc: pointer to the ds1685 rtc structure.
  88. * @val: u8 time value to consider converting.
  89. * @bcd_mask: u8 mask value if BCD mode is used.
  90. * @bin_mask: u8 mask value if BIN mode is used.
  91. *
  92. * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
  93. */
  94. static inline u8
  95. ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
  96. {
  97. if (rtc->bcd_mode)
  98. return (bcd2bin(val) & bcd_mask);
  99. return (val & bin_mask);
  100. }
  101. /**
  102. * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
  103. * @rtc: pointer to the ds1685 rtc structure.
  104. * @val: u8 time value to consider converting.
  105. * @bin_mask: u8 mask value if BIN mode is used.
  106. * @bcd_mask: u8 mask value if BCD mode is used.
  107. *
  108. * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
  109. */
  110. static inline u8
  111. ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
  112. {
  113. if (rtc->bcd_mode)
  114. return (bin2bcd(val) & bcd_mask);
  115. return (val & bin_mask);
  116. }
  117. /**
  118. * ds1685_rtc_check_mday - check validity of the day of month.
  119. * @rtc: pointer to the ds1685 rtc structure.
  120. * @mday: day of month.
  121. *
  122. * Returns -EDOM if the day of month is not within 1..31 range.
  123. */
  124. static inline int
  125. ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
  126. {
  127. if (rtc->bcd_mode) {
  128. if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
  129. return -EDOM;
  130. } else {
  131. if (mday < 1 || mday > 31)
  132. return -EDOM;
  133. }
  134. return 0;
  135. }
  136. /**
  137. * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
  138. * @rtc: pointer to the ds1685 rtc structure.
  139. */
  140. static inline void
  141. ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
  142. {
  143. rtc->write(rtc, RTC_CTRL_A,
  144. (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
  145. }
  146. /**
  147. * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
  148. * @rtc: pointer to the ds1685 rtc structure.
  149. */
  150. static inline void
  151. ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
  152. {
  153. rtc->write(rtc, RTC_CTRL_A,
  154. (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
  155. }
  156. /**
  157. * ds1685_rtc_begin_data_access - prepare the rtc for data access.
  158. * @rtc: pointer to the ds1685 rtc structure.
  159. *
  160. * This takes several steps to prepare the rtc for access to get/set time
  161. * and alarm values from the rtc registers:
  162. * - Sets the SET bit in Control Register B.
  163. * - Reads Ext Control Register 4A and checks the INCR bit.
  164. * - If INCR is active, a short delay is added before Ext Control Register 4A
  165. * is read again in a loop until INCR is inactive.
  166. * - Switches the rtc to bank 1. This allows access to all relevant
  167. * data for normal rtc operation, as bank 0 contains only the nvram.
  168. */
  169. static inline void
  170. ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
  171. {
  172. /* Set the SET bit in Ctrl B */
  173. rtc->write(rtc, RTC_CTRL_B,
  174. (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
  175. /* Switch to Bank 1 */
  176. ds1685_rtc_switch_to_bank1(rtc);
  177. /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
  178. while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
  179. cpu_relax();
  180. }
  181. /**
  182. * ds1685_rtc_end_data_access - end data access on the rtc.
  183. * @rtc: pointer to the ds1685 rtc structure.
  184. *
  185. * This ends what was started by ds1685_rtc_begin_data_access:
  186. * - Switches the rtc back to bank 0.
  187. * - Clears the SET bit in Control Register B.
  188. */
  189. static inline void
  190. ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
  191. {
  192. /* Switch back to Bank 0 */
  193. ds1685_rtc_switch_to_bank0(rtc);
  194. /* Clear the SET bit in Ctrl B */
  195. rtc->write(rtc, RTC_CTRL_B,
  196. (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
  197. }
  198. /**
  199. * ds1685_rtc_get_ssn - retrieve the silicon serial number.
  200. * @rtc: pointer to the ds1685 rtc structure.
  201. * @ssn: u8 array to hold the bits of the silicon serial number.
  202. *
  203. * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
  204. * first byte is the model number, the next six bytes are the serial number
  205. * digits, and the final byte is a CRC check byte. Together, they form the
  206. * silicon serial number.
  207. *
  208. * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
  209. * called first before calling this function, else data will be read out of
  210. * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
  211. */
  212. static inline void
  213. ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
  214. {
  215. ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
  216. ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
  217. ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
  218. ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
  219. ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
  220. ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
  221. ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
  222. ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
  223. }
  224. /* ----------------------------------------------------------------------- */
  225. /* ----------------------------------------------------------------------- */
  226. /* Read/Set Time & Alarm functions */
  227. /**
  228. * ds1685_rtc_read_time - reads the time registers.
  229. * @dev: pointer to device structure.
  230. * @tm: pointer to rtc_time structure.
  231. */
  232. static int
  233. ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
  234. {
  235. struct ds1685_priv *rtc = dev_get_drvdata(dev);
  236. u8 century;
  237. u8 seconds, minutes, hours, wday, mday, month, years;
  238. /* Fetch the time info from the RTC registers. */
  239. ds1685_rtc_begin_data_access(rtc);
  240. seconds = rtc->read(rtc, RTC_SECS);
  241. minutes = rtc->read(rtc, RTC_MINS);
  242. hours = rtc->read(rtc, RTC_HRS);
  243. wday = rtc->read(rtc, RTC_WDAY);
  244. mday = rtc->read(rtc, RTC_MDAY);
  245. month = rtc->read(rtc, RTC_MONTH);
  246. years = rtc->read(rtc, RTC_YEAR);
  247. century = rtc->read(rtc, RTC_CENTURY);
  248. ds1685_rtc_end_data_access(rtc);
  249. /* bcd2bin if needed, perform fixups, and store to rtc_time. */
  250. years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
  251. RTC_YEAR_BIN_MASK);
  252. century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
  253. RTC_CENTURY_MASK);
  254. tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
  255. RTC_SECS_BIN_MASK);
  256. tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
  257. RTC_MINS_BIN_MASK);
  258. tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
  259. RTC_HRS_24_BIN_MASK);
  260. tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
  261. RTC_WDAY_MASK) - 1);
  262. tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
  263. RTC_MDAY_BIN_MASK);
  264. tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
  265. RTC_MONTH_BIN_MASK) - 1);
  266. tm->tm_year = ((years + (century * 100)) - 1900);
  267. tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
  268. tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
  269. return 0;
  270. }
  271. /**
  272. * ds1685_rtc_set_time - sets the time registers.
  273. * @dev: pointer to device structure.
  274. * @tm: pointer to rtc_time structure.
  275. */
  276. static int
  277. ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
  278. {
  279. struct ds1685_priv *rtc = dev_get_drvdata(dev);
  280. u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
  281. /* Fetch the time info from rtc_time. */
  282. seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
  283. RTC_SECS_BCD_MASK);
  284. minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
  285. RTC_MINS_BCD_MASK);
  286. hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
  287. RTC_HRS_24_BCD_MASK);
  288. wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
  289. RTC_WDAY_MASK);
  290. mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
  291. RTC_MDAY_BCD_MASK);
  292. month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
  293. RTC_MONTH_BCD_MASK);
  294. years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
  295. RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
  296. century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
  297. RTC_CENTURY_MASK, RTC_CENTURY_MASK);
  298. /*
  299. * Perform Sanity Checks:
  300. * - Months: !> 12, Month Day != 0.
  301. * - Month Day !> Max days in current month.
  302. * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
  303. */
  304. if ((tm->tm_mon > 11) || (mday == 0))
  305. return -EDOM;
  306. if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
  307. return -EDOM;
  308. if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
  309. (tm->tm_sec >= 60) || (wday > 7))
  310. return -EDOM;
  311. /*
  312. * Set the data mode to use and store the time values in the
  313. * RTC registers.
  314. */
  315. ds1685_rtc_begin_data_access(rtc);
  316. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  317. if (rtc->bcd_mode)
  318. ctrlb &= ~(RTC_CTRL_B_DM);
  319. else
  320. ctrlb |= RTC_CTRL_B_DM;
  321. rtc->write(rtc, RTC_CTRL_B, ctrlb);
  322. rtc->write(rtc, RTC_SECS, seconds);
  323. rtc->write(rtc, RTC_MINS, minutes);
  324. rtc->write(rtc, RTC_HRS, hours);
  325. rtc->write(rtc, RTC_WDAY, wday);
  326. rtc->write(rtc, RTC_MDAY, mday);
  327. rtc->write(rtc, RTC_MONTH, month);
  328. rtc->write(rtc, RTC_YEAR, years);
  329. rtc->write(rtc, RTC_CENTURY, century);
  330. ds1685_rtc_end_data_access(rtc);
  331. return 0;
  332. }
  333. /**
  334. * ds1685_rtc_read_alarm - reads the alarm registers.
  335. * @dev: pointer to device structure.
  336. * @alrm: pointer to rtc_wkalrm structure.
  337. *
  338. * There are three primary alarm registers: seconds, minutes, and hours.
  339. * A fourth alarm register for the month date is also available in bank1 for
  340. * kickstart/wakeup features. The DS1685/DS1687 manual states that a
  341. * "don't care" value ranging from 0xc0 to 0xff may be written into one or
  342. * more of the three alarm bytes to act as a wildcard value. The fourth
  343. * byte doesn't support a "don't care" value.
  344. */
  345. static int
  346. ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  347. {
  348. struct ds1685_priv *rtc = dev_get_drvdata(dev);
  349. u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
  350. int ret;
  351. /* Fetch the alarm info from the RTC alarm registers. */
  352. ds1685_rtc_begin_data_access(rtc);
  353. seconds = rtc->read(rtc, RTC_SECS_ALARM);
  354. minutes = rtc->read(rtc, RTC_MINS_ALARM);
  355. hours = rtc->read(rtc, RTC_HRS_ALARM);
  356. mday = rtc->read(rtc, RTC_MDAY_ALARM);
  357. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  358. ctrlc = rtc->read(rtc, RTC_CTRL_C);
  359. ds1685_rtc_end_data_access(rtc);
  360. /* Check the month date for validity. */
  361. ret = ds1685_rtc_check_mday(rtc, mday);
  362. if (ret)
  363. return ret;
  364. /*
  365. * Check the three alarm bytes.
  366. *
  367. * The Linux RTC system doesn't support the "don't care" capability
  368. * of this RTC chip. We check for it anyways in case support is
  369. * added in the future and only assign when we care.
  370. */
  371. if (likely(seconds < 0xc0))
  372. alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
  373. RTC_SECS_BCD_MASK,
  374. RTC_SECS_BIN_MASK);
  375. if (likely(minutes < 0xc0))
  376. alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
  377. RTC_MINS_BCD_MASK,
  378. RTC_MINS_BIN_MASK);
  379. if (likely(hours < 0xc0))
  380. alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
  381. RTC_HRS_24_BCD_MASK,
  382. RTC_HRS_24_BIN_MASK);
  383. /* Write the data to rtc_wkalrm. */
  384. alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
  385. RTC_MDAY_BIN_MASK);
  386. alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
  387. alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
  388. return 0;
  389. }
  390. /**
  391. * ds1685_rtc_set_alarm - sets the alarm in registers.
  392. * @dev: pointer to device structure.
  393. * @alrm: pointer to rtc_wkalrm structure.
  394. */
  395. static int
  396. ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  397. {
  398. struct ds1685_priv *rtc = dev_get_drvdata(dev);
  399. u8 ctrlb, seconds, minutes, hours, mday;
  400. int ret;
  401. /* Fetch the alarm info and convert to BCD. */
  402. seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
  403. RTC_SECS_BIN_MASK,
  404. RTC_SECS_BCD_MASK);
  405. minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
  406. RTC_MINS_BIN_MASK,
  407. RTC_MINS_BCD_MASK);
  408. hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
  409. RTC_HRS_24_BIN_MASK,
  410. RTC_HRS_24_BCD_MASK);
  411. mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
  412. RTC_MDAY_BIN_MASK,
  413. RTC_MDAY_BCD_MASK);
  414. /* Check the month date for validity. */
  415. ret = ds1685_rtc_check_mday(rtc, mday);
  416. if (ret)
  417. return ret;
  418. /*
  419. * Check the three alarm bytes.
  420. *
  421. * The Linux RTC system doesn't support the "don't care" capability
  422. * of this RTC chip because rtc_valid_tm tries to validate every
  423. * field, and we only support four fields. We put the support
  424. * here anyways for the future.
  425. */
  426. if (unlikely(seconds >= 0xc0))
  427. seconds = 0xff;
  428. if (unlikely(minutes >= 0xc0))
  429. minutes = 0xff;
  430. if (unlikely(hours >= 0xc0))
  431. hours = 0xff;
  432. alrm->time.tm_mon = -1;
  433. alrm->time.tm_year = -1;
  434. alrm->time.tm_wday = -1;
  435. alrm->time.tm_yday = -1;
  436. alrm->time.tm_isdst = -1;
  437. /* Disable the alarm interrupt first. */
  438. ds1685_rtc_begin_data_access(rtc);
  439. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  440. rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
  441. /* Read ctrlc to clear RTC_CTRL_C_AF. */
  442. rtc->read(rtc, RTC_CTRL_C);
  443. /*
  444. * Set the data mode to use and store the time values in the
  445. * RTC registers.
  446. */
  447. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  448. if (rtc->bcd_mode)
  449. ctrlb &= ~(RTC_CTRL_B_DM);
  450. else
  451. ctrlb |= RTC_CTRL_B_DM;
  452. rtc->write(rtc, RTC_CTRL_B, ctrlb);
  453. rtc->write(rtc, RTC_SECS_ALARM, seconds);
  454. rtc->write(rtc, RTC_MINS_ALARM, minutes);
  455. rtc->write(rtc, RTC_HRS_ALARM, hours);
  456. rtc->write(rtc, RTC_MDAY_ALARM, mday);
  457. /* Re-enable the alarm if needed. */
  458. if (alrm->enabled) {
  459. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  460. ctrlb |= RTC_CTRL_B_AIE;
  461. rtc->write(rtc, RTC_CTRL_B, ctrlb);
  462. }
  463. /* Done! */
  464. ds1685_rtc_end_data_access(rtc);
  465. return 0;
  466. }
  467. /* ----------------------------------------------------------------------- */
  468. /* ----------------------------------------------------------------------- */
  469. /* /dev/rtcX Interface functions */
  470. /**
  471. * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
  472. * @dev: pointer to device structure.
  473. * @enabled: flag indicating whether to enable or disable.
  474. */
  475. static int
  476. ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  477. {
  478. struct ds1685_priv *rtc = dev_get_drvdata(dev);
  479. /* Flip the requisite interrupt-enable bit. */
  480. if (enabled)
  481. rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
  482. RTC_CTRL_B_AIE));
  483. else
  484. rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
  485. ~(RTC_CTRL_B_AIE)));
  486. /* Read Control C to clear all the flag bits. */
  487. rtc->read(rtc, RTC_CTRL_C);
  488. return 0;
  489. }
  490. /* ----------------------------------------------------------------------- */
  491. /* ----------------------------------------------------------------------- */
  492. /* IRQ handler */
  493. /**
  494. * ds1685_rtc_extended_irq - take care of extended interrupts
  495. * @rtc: pointer to the ds1685 rtc structure.
  496. * @pdev: platform device pointer.
  497. */
  498. static void
  499. ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev)
  500. {
  501. u8 ctrl4a, ctrl4b;
  502. ds1685_rtc_switch_to_bank1(rtc);
  503. ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
  504. ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
  505. /*
  506. * Check for a kickstart interrupt. With Vcc applied, this
  507. * typically means that the power button was pressed, so we
  508. * begin the shutdown sequence.
  509. */
  510. if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
  511. /* Briefly disable kickstarts to debounce button presses. */
  512. rtc->write(rtc, RTC_EXT_CTRL_4B,
  513. (rtc->read(rtc, RTC_EXT_CTRL_4B) &
  514. ~(RTC_CTRL_4B_KSE)));
  515. /* Clear the kickstart flag. */
  516. rtc->write(rtc, RTC_EXT_CTRL_4A,
  517. (ctrl4a & ~(RTC_CTRL_4A_KF)));
  518. /*
  519. * Sleep 500ms before re-enabling kickstarts. This allows
  520. * adequate time to avoid reading signal jitter as additional
  521. * button presses.
  522. */
  523. msleep(500);
  524. rtc->write(rtc, RTC_EXT_CTRL_4B,
  525. (rtc->read(rtc, RTC_EXT_CTRL_4B) |
  526. RTC_CTRL_4B_KSE));
  527. /* Call the platform pre-poweroff function. Else, shutdown. */
  528. if (rtc->prepare_poweroff != NULL)
  529. rtc->prepare_poweroff();
  530. else
  531. ds1685_rtc_poweroff(pdev);
  532. }
  533. /*
  534. * Check for a wake-up interrupt. With Vcc applied, this is
  535. * essentially a second alarm interrupt, except it takes into
  536. * account the 'date' register in bank1 in addition to the
  537. * standard three alarm registers.
  538. */
  539. if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
  540. rtc->write(rtc, RTC_EXT_CTRL_4A,
  541. (ctrl4a & ~(RTC_CTRL_4A_WF)));
  542. /* Call the platform wake_alarm function if defined. */
  543. if (rtc->wake_alarm != NULL)
  544. rtc->wake_alarm();
  545. else
  546. dev_warn(&pdev->dev,
  547. "Wake Alarm IRQ just occurred!\n");
  548. }
  549. /*
  550. * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
  551. * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
  552. * each byte to a logic 1. This has no effect on any extended
  553. * NV-SRAM that might be present, nor on the time/calendar/alarm
  554. * registers. After a ram-clear is completed, there is a minimum
  555. * recovery time of ~150ms in which all reads/writes are locked out.
  556. * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
  557. * catch this scenario.
  558. */
  559. if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
  560. rtc->write(rtc, RTC_EXT_CTRL_4A,
  561. (ctrl4a & ~(RTC_CTRL_4A_RF)));
  562. msleep(150);
  563. /* Call the platform post_ram_clear function if defined. */
  564. if (rtc->post_ram_clear != NULL)
  565. rtc->post_ram_clear();
  566. else
  567. dev_warn(&pdev->dev,
  568. "RAM-Clear IRQ just occurred!\n");
  569. }
  570. ds1685_rtc_switch_to_bank0(rtc);
  571. }
  572. /**
  573. * ds1685_rtc_irq_handler - IRQ handler.
  574. * @irq: IRQ number.
  575. * @dev_id: platform device pointer.
  576. */
  577. static irqreturn_t
  578. ds1685_rtc_irq_handler(int irq, void *dev_id)
  579. {
  580. struct platform_device *pdev = dev_id;
  581. struct ds1685_priv *rtc = platform_get_drvdata(pdev);
  582. u8 ctrlb, ctrlc;
  583. unsigned long events = 0;
  584. u8 num_irqs = 0;
  585. /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
  586. if (unlikely(!rtc))
  587. return IRQ_HANDLED;
  588. rtc_lock(rtc->dev);
  589. /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
  590. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  591. ctrlc = rtc->read(rtc, RTC_CTRL_C);
  592. /* Is the IRQF bit set? */
  593. if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
  594. /*
  595. * We need to determine if it was one of the standard
  596. * events: PF, AF, or UF. If so, we handle them and
  597. * update the RTC core.
  598. */
  599. if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
  600. events = RTC_IRQF;
  601. /* Check for a periodic interrupt. */
  602. if ((ctrlb & RTC_CTRL_B_PIE) &&
  603. (ctrlc & RTC_CTRL_C_PF)) {
  604. events |= RTC_PF;
  605. num_irqs++;
  606. }
  607. /* Check for an alarm interrupt. */
  608. if ((ctrlb & RTC_CTRL_B_AIE) &&
  609. (ctrlc & RTC_CTRL_C_AF)) {
  610. events |= RTC_AF;
  611. num_irqs++;
  612. }
  613. /* Check for an update interrupt. */
  614. if ((ctrlb & RTC_CTRL_B_UIE) &&
  615. (ctrlc & RTC_CTRL_C_UF)) {
  616. events |= RTC_UF;
  617. num_irqs++;
  618. }
  619. } else {
  620. /*
  621. * One of the "extended" interrupts was received that
  622. * is not recognized by the RTC core.
  623. */
  624. ds1685_rtc_extended_irq(rtc, pdev);
  625. }
  626. }
  627. rtc_update_irq(rtc->dev, num_irqs, events);
  628. rtc_unlock(rtc->dev);
  629. return events ? IRQ_HANDLED : IRQ_NONE;
  630. }
  631. /* ----------------------------------------------------------------------- */
  632. /* ----------------------------------------------------------------------- */
  633. /* ProcFS interface */
  634. #ifdef CONFIG_PROC_FS
  635. #define NUM_REGS 6 /* Num of control registers. */
  636. #define NUM_BITS 8 /* Num bits per register. */
  637. #define NUM_SPACES 4 /* Num spaces between each bit. */
  638. /*
  639. * Periodic Interrupt Rates.
  640. */
  641. static const char *ds1685_rtc_pirq_rate[16] = {
  642. "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
  643. "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
  644. "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
  645. };
  646. /*
  647. * Square-Wave Output Frequencies.
  648. */
  649. static const char *ds1685_rtc_sqw_freq[16] = {
  650. "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
  651. "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
  652. };
  653. /**
  654. * ds1685_rtc_proc - procfs access function.
  655. * @dev: pointer to device structure.
  656. * @seq: pointer to seq_file structure.
  657. */
  658. static int
  659. ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
  660. {
  661. struct ds1685_priv *rtc = dev_get_drvdata(dev);
  662. u8 ctrla, ctrlb, ctrld, ctrl4a, ctrl4b, ssn[8];
  663. char *model;
  664. /* Read all the relevant data from the control registers. */
  665. ds1685_rtc_switch_to_bank1(rtc);
  666. ds1685_rtc_get_ssn(rtc, ssn);
  667. ctrla = rtc->read(rtc, RTC_CTRL_A);
  668. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  669. ctrld = rtc->read(rtc, RTC_CTRL_D);
  670. ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
  671. ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
  672. ds1685_rtc_switch_to_bank0(rtc);
  673. /* Determine the RTC model. */
  674. switch (ssn[0]) {
  675. case RTC_MODEL_DS1685:
  676. model = "DS1685/DS1687\0";
  677. break;
  678. case RTC_MODEL_DS1689:
  679. model = "DS1689/DS1693\0";
  680. break;
  681. case RTC_MODEL_DS17285:
  682. model = "DS17285/DS17287\0";
  683. break;
  684. case RTC_MODEL_DS17485:
  685. model = "DS17485/DS17487\0";
  686. break;
  687. case RTC_MODEL_DS17885:
  688. model = "DS17885/DS17887\0";
  689. break;
  690. default:
  691. model = "Unknown\0";
  692. break;
  693. }
  694. /* Print out the information. */
  695. seq_printf(seq,
  696. "Model\t\t: %s\n"
  697. "Oscillator\t: %s\n"
  698. "12/24hr\t\t: %s\n"
  699. "DST\t\t: %s\n"
  700. "Data mode\t: %s\n"
  701. "Battery\t\t: %s\n"
  702. "Aux batt\t: %s\n"
  703. "Update IRQ\t: %s\n"
  704. "Periodic IRQ\t: %s\n"
  705. "Periodic Rate\t: %s\n"
  706. "SQW Freq\t: %s\n"
  707. "Serial #\t: %8phC\n",
  708. model,
  709. ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
  710. ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
  711. ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
  712. ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
  713. ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
  714. ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
  715. ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
  716. ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
  717. (!(ctrl4b & RTC_CTRL_4B_E32K) ?
  718. ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
  719. (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
  720. ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
  721. ssn);
  722. return 0;
  723. }
  724. #else
  725. #define ds1685_rtc_proc NULL
  726. #endif /* CONFIG_PROC_FS */
  727. /* ----------------------------------------------------------------------- */
  728. /* ----------------------------------------------------------------------- */
  729. /* RTC Class operations */
  730. static const struct rtc_class_ops
  731. ds1685_rtc_ops = {
  732. .proc = ds1685_rtc_proc,
  733. .read_time = ds1685_rtc_read_time,
  734. .set_time = ds1685_rtc_set_time,
  735. .read_alarm = ds1685_rtc_read_alarm,
  736. .set_alarm = ds1685_rtc_set_alarm,
  737. .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
  738. };
  739. /* ----------------------------------------------------------------------- */
  740. static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
  741. size_t size)
  742. {
  743. struct ds1685_priv *rtc = priv;
  744. struct mutex *rtc_mutex = &rtc->dev->ops_lock;
  745. ssize_t count;
  746. u8 *buf = val;
  747. int err;
  748. err = mutex_lock_interruptible(rtc_mutex);
  749. if (err)
  750. return err;
  751. ds1685_rtc_switch_to_bank0(rtc);
  752. /* Read NVRAM in time and bank0 registers. */
  753. for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
  754. count++, size--) {
  755. if (count < NVRAM_SZ_TIME)
  756. *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
  757. else
  758. *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
  759. }
  760. #ifndef CONFIG_RTC_DRV_DS1689
  761. if (size > 0) {
  762. ds1685_rtc_switch_to_bank1(rtc);
  763. #ifndef CONFIG_RTC_DRV_DS1685
  764. /* Enable burst-mode on DS17x85/DS17x87 */
  765. rtc->write(rtc, RTC_EXT_CTRL_4A,
  766. (rtc->read(rtc, RTC_EXT_CTRL_4A) |
  767. RTC_CTRL_4A_BME));
  768. /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
  769. * reading with burst-mode */
  770. rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
  771. (pos - NVRAM_TOTAL_SZ_BANK0));
  772. #endif
  773. /* Read NVRAM in bank1 registers. */
  774. for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
  775. count++, size--) {
  776. #ifdef CONFIG_RTC_DRV_DS1685
  777. /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
  778. * before each read. */
  779. rtc->write(rtc, RTC_BANK1_RAM_ADDR,
  780. (pos - NVRAM_TOTAL_SZ_BANK0));
  781. #endif
  782. *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
  783. pos++;
  784. }
  785. #ifndef CONFIG_RTC_DRV_DS1685
  786. /* Disable burst-mode on DS17x85/DS17x87 */
  787. rtc->write(rtc, RTC_EXT_CTRL_4A,
  788. (rtc->read(rtc, RTC_EXT_CTRL_4A) &
  789. ~(RTC_CTRL_4A_BME)));
  790. #endif
  791. ds1685_rtc_switch_to_bank0(rtc);
  792. }
  793. #endif /* !CONFIG_RTC_DRV_DS1689 */
  794. mutex_unlock(rtc_mutex);
  795. return 0;
  796. }
  797. static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
  798. size_t size)
  799. {
  800. struct ds1685_priv *rtc = priv;
  801. struct mutex *rtc_mutex = &rtc->dev->ops_lock;
  802. ssize_t count;
  803. u8 *buf = val;
  804. int err;
  805. err = mutex_lock_interruptible(rtc_mutex);
  806. if (err)
  807. return err;
  808. ds1685_rtc_switch_to_bank0(rtc);
  809. /* Write NVRAM in time and bank0 registers. */
  810. for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
  811. count++, size--)
  812. if (count < NVRAM_SZ_TIME)
  813. rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
  814. *buf++);
  815. else
  816. rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
  817. #ifndef CONFIG_RTC_DRV_DS1689
  818. if (size > 0) {
  819. ds1685_rtc_switch_to_bank1(rtc);
  820. #ifndef CONFIG_RTC_DRV_DS1685
  821. /* Enable burst-mode on DS17x85/DS17x87 */
  822. rtc->write(rtc, RTC_EXT_CTRL_4A,
  823. (rtc->read(rtc, RTC_EXT_CTRL_4A) |
  824. RTC_CTRL_4A_BME));
  825. /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
  826. * writing with burst-mode */
  827. rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
  828. (pos - NVRAM_TOTAL_SZ_BANK0));
  829. #endif
  830. /* Write NVRAM in bank1 registers. */
  831. for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
  832. count++, size--) {
  833. #ifdef CONFIG_RTC_DRV_DS1685
  834. /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
  835. * before each read. */
  836. rtc->write(rtc, RTC_BANK1_RAM_ADDR,
  837. (pos - NVRAM_TOTAL_SZ_BANK0));
  838. #endif
  839. rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
  840. pos++;
  841. }
  842. #ifndef CONFIG_RTC_DRV_DS1685
  843. /* Disable burst-mode on DS17x85/DS17x87 */
  844. rtc->write(rtc, RTC_EXT_CTRL_4A,
  845. (rtc->read(rtc, RTC_EXT_CTRL_4A) &
  846. ~(RTC_CTRL_4A_BME)));
  847. #endif
  848. ds1685_rtc_switch_to_bank0(rtc);
  849. }
  850. #endif /* !CONFIG_RTC_DRV_DS1689 */
  851. mutex_unlock(rtc_mutex);
  852. return 0;
  853. }
  854. /* ----------------------------------------------------------------------- */
  855. /* SysFS interface */
  856. /**
  857. * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
  858. * @dev: pointer to device structure.
  859. * @attr: pointer to device_attribute structure.
  860. * @buf: pointer to char array to hold the output.
  861. */
  862. static ssize_t
  863. ds1685_rtc_sysfs_battery_show(struct device *dev,
  864. struct device_attribute *attr, char *buf)
  865. {
  866. struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
  867. u8 ctrld;
  868. ctrld = rtc->read(rtc, RTC_CTRL_D);
  869. return sprintf(buf, "%s\n",
  870. (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
  871. }
  872. static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
  873. /**
  874. * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
  875. * @dev: pointer to device structure.
  876. * @attr: pointer to device_attribute structure.
  877. * @buf: pointer to char array to hold the output.
  878. */
  879. static ssize_t
  880. ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
  881. struct device_attribute *attr, char *buf)
  882. {
  883. struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
  884. u8 ctrl4a;
  885. ds1685_rtc_switch_to_bank1(rtc);
  886. ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
  887. ds1685_rtc_switch_to_bank0(rtc);
  888. return sprintf(buf, "%s\n",
  889. (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
  890. }
  891. static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
  892. /**
  893. * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
  894. * @dev: pointer to device structure.
  895. * @attr: pointer to device_attribute structure.
  896. * @buf: pointer to char array to hold the output.
  897. */
  898. static ssize_t
  899. ds1685_rtc_sysfs_serial_show(struct device *dev,
  900. struct device_attribute *attr, char *buf)
  901. {
  902. struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
  903. u8 ssn[8];
  904. ds1685_rtc_switch_to_bank1(rtc);
  905. ds1685_rtc_get_ssn(rtc, ssn);
  906. ds1685_rtc_switch_to_bank0(rtc);
  907. return sprintf(buf, "%8phC\n", ssn);
  908. }
  909. static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
  910. /*
  911. * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
  912. */
  913. static struct attribute*
  914. ds1685_rtc_sysfs_misc_attrs[] = {
  915. &dev_attr_battery.attr,
  916. &dev_attr_auxbatt.attr,
  917. &dev_attr_serial.attr,
  918. NULL,
  919. };
  920. /*
  921. * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
  922. */
  923. static const struct attribute_group
  924. ds1685_rtc_sysfs_misc_grp = {
  925. .name = "misc",
  926. .attrs = ds1685_rtc_sysfs_misc_attrs,
  927. };
  928. /* ----------------------------------------------------------------------- */
  929. /* Driver Probe/Removal */
  930. /**
  931. * ds1685_rtc_probe - initializes rtc driver.
  932. * @pdev: pointer to platform_device structure.
  933. */
  934. static int
  935. ds1685_rtc_probe(struct platform_device *pdev)
  936. {
  937. struct rtc_device *rtc_dev;
  938. struct ds1685_priv *rtc;
  939. struct ds1685_rtc_platform_data *pdata;
  940. u8 ctrla, ctrlb, hours;
  941. unsigned char am_pm;
  942. int ret = 0;
  943. struct nvmem_config nvmem_cfg = {
  944. .name = "ds1685_nvram",
  945. .size = NVRAM_TOTAL_SZ,
  946. .reg_read = ds1685_nvram_read,
  947. .reg_write = ds1685_nvram_write,
  948. };
  949. /* Get the platform data. */
  950. pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
  951. if (!pdata)
  952. return -ENODEV;
  953. /* Allocate memory for the rtc device. */
  954. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  955. if (!rtc)
  956. return -ENOMEM;
  957. /* Setup resources and access functions */
  958. switch (pdata->access_type) {
  959. case ds1685_reg_direct:
  960. rtc->regs = devm_platform_ioremap_resource(pdev, 0);
  961. if (IS_ERR(rtc->regs))
  962. return PTR_ERR(rtc->regs);
  963. rtc->read = ds1685_read;
  964. rtc->write = ds1685_write;
  965. break;
  966. case ds1685_reg_indirect:
  967. rtc->regs = devm_platform_ioremap_resource(pdev, 0);
  968. if (IS_ERR(rtc->regs))
  969. return PTR_ERR(rtc->regs);
  970. rtc->data = devm_platform_ioremap_resource(pdev, 1);
  971. if (IS_ERR(rtc->data))
  972. return PTR_ERR(rtc->data);
  973. rtc->read = ds1685_indirect_read;
  974. rtc->write = ds1685_indirect_write;
  975. break;
  976. }
  977. if (!rtc->read || !rtc->write)
  978. return -ENXIO;
  979. /* Get the register step size. */
  980. if (pdata->regstep > 0)
  981. rtc->regstep = pdata->regstep;
  982. else
  983. rtc->regstep = 1;
  984. /* Platform pre-shutdown function, if defined. */
  985. if (pdata->plat_prepare_poweroff)
  986. rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
  987. /* Platform wake_alarm function, if defined. */
  988. if (pdata->plat_wake_alarm)
  989. rtc->wake_alarm = pdata->plat_wake_alarm;
  990. /* Platform post_ram_clear function, if defined. */
  991. if (pdata->plat_post_ram_clear)
  992. rtc->post_ram_clear = pdata->plat_post_ram_clear;
  993. /* set the driver data. */
  994. platform_set_drvdata(pdev, rtc);
  995. /* Turn the oscillator on if is not already on (DV1 = 1). */
  996. ctrla = rtc->read(rtc, RTC_CTRL_A);
  997. if (!(ctrla & RTC_CTRL_A_DV1))
  998. ctrla |= RTC_CTRL_A_DV1;
  999. /* Enable the countdown chain (DV2 = 0) */
  1000. ctrla &= ~(RTC_CTRL_A_DV2);
  1001. /* Clear RS3-RS0 in Control A. */
  1002. ctrla &= ~(RTC_CTRL_A_RS_MASK);
  1003. /*
  1004. * All done with Control A. Switch to Bank 1 for the remainder of
  1005. * the RTC setup so we have access to the extended functions.
  1006. */
  1007. ctrla |= RTC_CTRL_A_DV0;
  1008. rtc->write(rtc, RTC_CTRL_A, ctrla);
  1009. /* Default to 32768kHz output. */
  1010. rtc->write(rtc, RTC_EXT_CTRL_4B,
  1011. (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
  1012. /* Set the SET bit in Control B so we can do some housekeeping. */
  1013. rtc->write(rtc, RTC_CTRL_B,
  1014. (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
  1015. /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
  1016. while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
  1017. cpu_relax();
  1018. /*
  1019. * If the platform supports BCD mode, then set DM=0 in Control B.
  1020. * Otherwise, set DM=1 for BIN mode.
  1021. */
  1022. ctrlb = rtc->read(rtc, RTC_CTRL_B);
  1023. if (pdata->bcd_mode)
  1024. ctrlb &= ~(RTC_CTRL_B_DM);
  1025. else
  1026. ctrlb |= RTC_CTRL_B_DM;
  1027. rtc->bcd_mode = pdata->bcd_mode;
  1028. /*
  1029. * Disable Daylight Savings Time (DSE = 0).
  1030. * The RTC has hardcoded timezone information that is rendered
  1031. * obselete. We'll let the OS deal with DST settings instead.
  1032. */
  1033. if (ctrlb & RTC_CTRL_B_DSE)
  1034. ctrlb &= ~(RTC_CTRL_B_DSE);
  1035. /* Force 24-hour mode (2412 = 1). */
  1036. if (!(ctrlb & RTC_CTRL_B_2412)) {
  1037. /* Reinitialize the time hours. */
  1038. hours = rtc->read(rtc, RTC_HRS);
  1039. am_pm = hours & RTC_HRS_AMPM_MASK;
  1040. hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
  1041. RTC_HRS_12_BIN_MASK);
  1042. hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
  1043. /* Enable 24-hour mode. */
  1044. ctrlb |= RTC_CTRL_B_2412;
  1045. /* Write back to Control B, including DM & DSE bits. */
  1046. rtc->write(rtc, RTC_CTRL_B, ctrlb);
  1047. /* Write the time hours back. */
  1048. rtc->write(rtc, RTC_HRS,
  1049. ds1685_rtc_bin2bcd(rtc, hours,
  1050. RTC_HRS_24_BIN_MASK,
  1051. RTC_HRS_24_BCD_MASK));
  1052. /* Reinitialize the alarm hours. */
  1053. hours = rtc->read(rtc, RTC_HRS_ALARM);
  1054. am_pm = hours & RTC_HRS_AMPM_MASK;
  1055. hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
  1056. RTC_HRS_12_BIN_MASK);
  1057. hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
  1058. /* Write the alarm hours back. */
  1059. rtc->write(rtc, RTC_HRS_ALARM,
  1060. ds1685_rtc_bin2bcd(rtc, hours,
  1061. RTC_HRS_24_BIN_MASK,
  1062. RTC_HRS_24_BCD_MASK));
  1063. } else {
  1064. /* 24-hour mode is already set, so write Control B back. */
  1065. rtc->write(rtc, RTC_CTRL_B, ctrlb);
  1066. }
  1067. /* Unset the SET bit in Control B so the RTC can update. */
  1068. rtc->write(rtc, RTC_CTRL_B,
  1069. (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
  1070. /* Check the main battery. */
  1071. if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
  1072. dev_warn(&pdev->dev,
  1073. "Main battery is exhausted! RTC may be invalid!\n");
  1074. /* Check the auxillary battery. It is optional. */
  1075. if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
  1076. dev_warn(&pdev->dev,
  1077. "Aux battery is exhausted or not available.\n");
  1078. /* Read Ctrl B and clear PIE/AIE/UIE. */
  1079. rtc->write(rtc, RTC_CTRL_B,
  1080. (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
  1081. /* Reading Ctrl C auto-clears PF/AF/UF. */
  1082. rtc->read(rtc, RTC_CTRL_C);
  1083. /* Read Ctrl 4B and clear RIE/WIE/KSE. */
  1084. rtc->write(rtc, RTC_EXT_CTRL_4B,
  1085. (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
  1086. /* Clear RF/WF/KF in Ctrl 4A. */
  1087. rtc->write(rtc, RTC_EXT_CTRL_4A,
  1088. (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
  1089. /*
  1090. * Re-enable KSE to handle power button events. We do not enable
  1091. * WIE or RIE by default.
  1092. */
  1093. rtc->write(rtc, RTC_EXT_CTRL_4B,
  1094. (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
  1095. rtc_dev = devm_rtc_allocate_device(&pdev->dev);
  1096. if (IS_ERR(rtc_dev))
  1097. return PTR_ERR(rtc_dev);
  1098. rtc_dev->ops = &ds1685_rtc_ops;
  1099. /* Century bit is useless because leap year fails in 1900 and 2100 */
  1100. rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
  1101. rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
  1102. /* Maximum periodic rate is 8192Hz (0.122070ms). */
  1103. rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
  1104. /* See if the platform doesn't support UIE. */
  1105. if (pdata->uie_unsupported)
  1106. clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc_dev->features);
  1107. rtc->dev = rtc_dev;
  1108. /*
  1109. * Fetch the IRQ and setup the interrupt handler.
  1110. *
  1111. * Not all platforms have the IRQF pin tied to something. If not, the
  1112. * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
  1113. * there won't be an automatic way of notifying the kernel about it,
  1114. * unless ctrlc is explicitly polled.
  1115. */
  1116. rtc->irq_num = platform_get_irq(pdev, 0);
  1117. if (rtc->irq_num <= 0) {
  1118. clear_bit(RTC_FEATURE_ALARM, rtc_dev->features);
  1119. } else {
  1120. /* Request an IRQ. */
  1121. ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num,
  1122. NULL, ds1685_rtc_irq_handler,
  1123. IRQF_SHARED | IRQF_ONESHOT,
  1124. pdev->name, pdev);
  1125. /* Check to see if something came back. */
  1126. if (unlikely(ret)) {
  1127. dev_warn(&pdev->dev,
  1128. "RTC interrupt not available\n");
  1129. rtc->irq_num = 0;
  1130. }
  1131. }
  1132. /* Setup complete. */
  1133. ds1685_rtc_switch_to_bank0(rtc);
  1134. ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp);
  1135. if (ret)
  1136. return ret;
  1137. nvmem_cfg.priv = rtc;
  1138. ret = devm_rtc_nvmem_register(rtc_dev, &nvmem_cfg);
  1139. if (ret)
  1140. return ret;
  1141. return devm_rtc_register_device(rtc_dev);
  1142. }
  1143. /**
  1144. * ds1685_rtc_remove - removes rtc driver.
  1145. * @pdev: pointer to platform_device structure.
  1146. */
  1147. static int
  1148. ds1685_rtc_remove(struct platform_device *pdev)
  1149. {
  1150. struct ds1685_priv *rtc = platform_get_drvdata(pdev);
  1151. /* Read Ctrl B and clear PIE/AIE/UIE. */
  1152. rtc->write(rtc, RTC_CTRL_B,
  1153. (rtc->read(rtc, RTC_CTRL_B) &
  1154. ~(RTC_CTRL_B_PAU_MASK)));
  1155. /* Reading Ctrl C auto-clears PF/AF/UF. */
  1156. rtc->read(rtc, RTC_CTRL_C);
  1157. /* Read Ctrl 4B and clear RIE/WIE/KSE. */
  1158. rtc->write(rtc, RTC_EXT_CTRL_4B,
  1159. (rtc->read(rtc, RTC_EXT_CTRL_4B) &
  1160. ~(RTC_CTRL_4B_RWK_MASK)));
  1161. /* Manually clear RF/WF/KF in Ctrl 4A. */
  1162. rtc->write(rtc, RTC_EXT_CTRL_4A,
  1163. (rtc->read(rtc, RTC_EXT_CTRL_4A) &
  1164. ~(RTC_CTRL_4A_RWK_MASK)));
  1165. return 0;
  1166. }
  1167. /*
  1168. * ds1685_rtc_driver - rtc driver properties.
  1169. */
  1170. static struct platform_driver ds1685_rtc_driver = {
  1171. .driver = {
  1172. .name = "rtc-ds1685",
  1173. },
  1174. .probe = ds1685_rtc_probe,
  1175. .remove = ds1685_rtc_remove,
  1176. };
  1177. module_platform_driver(ds1685_rtc_driver);
  1178. /* ----------------------------------------------------------------------- */
  1179. /* ----------------------------------------------------------------------- */
  1180. /* Poweroff function */
  1181. /**
  1182. * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
  1183. * @pdev: pointer to platform_device structure.
  1184. */
  1185. void __noreturn
  1186. ds1685_rtc_poweroff(struct platform_device *pdev)
  1187. {
  1188. u8 ctrla, ctrl4a, ctrl4b;
  1189. struct ds1685_priv *rtc;
  1190. /* Check for valid RTC data, else, spin forever. */
  1191. if (unlikely(!pdev)) {
  1192. pr_emerg("platform device data not available, spinning forever ...\n");
  1193. while(1);
  1194. unreachable();
  1195. } else {
  1196. /* Get the rtc data. */
  1197. rtc = platform_get_drvdata(pdev);
  1198. /*
  1199. * Disable our IRQ. We're powering down, so we're not
  1200. * going to worry about cleaning up. Most of that should
  1201. * have been taken care of by the shutdown scripts and this
  1202. * is the final function call.
  1203. */
  1204. if (rtc->irq_num)
  1205. disable_irq_nosync(rtc->irq_num);
  1206. /* Oscillator must be on and the countdown chain enabled. */
  1207. ctrla = rtc->read(rtc, RTC_CTRL_A);
  1208. ctrla |= RTC_CTRL_A_DV1;
  1209. ctrla &= ~(RTC_CTRL_A_DV2);
  1210. rtc->write(rtc, RTC_CTRL_A, ctrla);
  1211. /*
  1212. * Read Control 4A and check the status of the auxillary
  1213. * battery. This must be present and working (VRT2 = 1)
  1214. * for wakeup and kickstart functionality to be useful.
  1215. */
  1216. ds1685_rtc_switch_to_bank1(rtc);
  1217. ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
  1218. if (ctrl4a & RTC_CTRL_4A_VRT2) {
  1219. /* Clear all of the interrupt flags on Control 4A. */
  1220. ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
  1221. rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
  1222. /*
  1223. * The auxillary battery is present and working.
  1224. * Enable extended functions (ABE=1), enable
  1225. * wake-up (WIE=1), and enable kickstart (KSE=1)
  1226. * in Control 4B.
  1227. */
  1228. ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
  1229. ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
  1230. RTC_CTRL_4B_KSE);
  1231. rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
  1232. }
  1233. /* Set PAB to 1 in Control 4A to power the system down. */
  1234. dev_warn(&pdev->dev, "Powerdown.\n");
  1235. msleep(20);
  1236. rtc->write(rtc, RTC_EXT_CTRL_4A,
  1237. (ctrl4a | RTC_CTRL_4A_PAB));
  1238. /* Spin ... we do not switch back to bank0. */
  1239. while(1);
  1240. unreachable();
  1241. }
  1242. }
  1243. EXPORT_SYMBOL_GPL(ds1685_rtc_poweroff);
  1244. /* ----------------------------------------------------------------------- */
  1245. MODULE_AUTHOR("Joshua Kinard <[email protected]>");
  1246. MODULE_AUTHOR("Matthias Fuchs <[email protected]>");
  1247. MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
  1248. MODULE_LICENSE("GPL");
  1249. MODULE_ALIAS("platform:rtc-ds1685");