rtc-at91rm9200.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Real Time Clock interface for Linux on Atmel AT91RM9200
  4. *
  5. * Copyright (C) 2002 Rick Bronson
  6. *
  7. * Converted to RTC class model by Andrew Victor
  8. *
  9. * Ported to Linux 2.6 by Steven Scholz
  10. * Based on s3c2410-rtc.c Simtec Electronics
  11. *
  12. * Based on sa1100-rtc.c by Nils Faerber
  13. * Based on rtc.c by Paul Gortmaker
  14. */
  15. #include <linux/bcd.h>
  16. #include <linux/bitfield.h>
  17. #include <linux/clk.h>
  18. #include <linux/completion.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioctl.h>
  21. #include <linux/io.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/of_device.h>
  25. #include <linux/of.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/rtc.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/suspend.h>
  30. #include <linux/time.h>
  31. #include <linux/uaccess.h>
  32. #define AT91_RTC_CR 0x00 /* Control Register */
  33. #define AT91_RTC_UPDTIM BIT(0) /* Update Request Time Register */
  34. #define AT91_RTC_UPDCAL BIT(1) /* Update Request Calendar Register */
  35. #define AT91_RTC_MR 0x04 /* Mode Register */
  36. #define AT91_RTC_HRMOD BIT(0) /* 12/24 hour mode */
  37. #define AT91_RTC_NEGPPM BIT(4) /* Negative PPM correction */
  38. #define AT91_RTC_CORRECTION GENMASK(14, 8) /* Slow clock correction */
  39. #define AT91_RTC_HIGHPPM BIT(15) /* High PPM correction */
  40. #define AT91_RTC_TIMR 0x08 /* Time Register */
  41. #define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */
  42. #define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */
  43. #define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */
  44. #define AT91_RTC_AMPM BIT(22) /* Ante Meridiem Post Meridiem Indicator */
  45. #define AT91_RTC_CALR 0x0c /* Calendar Register */
  46. #define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */
  47. #define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */
  48. #define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */
  49. #define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */
  50. #define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */
  51. #define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */
  52. #define AT91_RTC_SECEN BIT(7) /* Second Alarm Enable */
  53. #define AT91_RTC_MINEN BIT(15) /* Minute Alarm Enable */
  54. #define AT91_RTC_HOUREN BIT(23) /* Hour Alarm Enable */
  55. #define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */
  56. #define AT91_RTC_MTHEN BIT(23) /* Month Alarm Enable */
  57. #define AT91_RTC_DATEEN BIT(31) /* Date Alarm Enable */
  58. #define AT91_RTC_SR 0x18 /* Status Register */
  59. #define AT91_RTC_ACKUPD BIT(0) /* Acknowledge for Update */
  60. #define AT91_RTC_ALARM BIT(1) /* Alarm Flag */
  61. #define AT91_RTC_SECEV BIT(2) /* Second Event */
  62. #define AT91_RTC_TIMEV BIT(3) /* Time Event */
  63. #define AT91_RTC_CALEV BIT(4) /* Calendar Event */
  64. #define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */
  65. #define AT91_RTC_IER 0x20 /* Interrupt Enable Register */
  66. #define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
  67. #define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
  68. #define AT91_RTC_VER 0x2c /* Valid Entry Register */
  69. #define AT91_RTC_NVTIM BIT(0) /* Non valid Time */
  70. #define AT91_RTC_NVCAL BIT(1) /* Non valid Calendar */
  71. #define AT91_RTC_NVTIMALR BIT(2) /* Non valid Time Alarm */
  72. #define AT91_RTC_NVCALALR BIT(3) /* Non valid Calendar Alarm */
  73. #define AT91_RTC_CORR_DIVIDEND 3906000
  74. #define AT91_RTC_CORR_LOW_RATIO 20
  75. #define at91_rtc_read(field) \
  76. readl_relaxed(at91_rtc_regs + field)
  77. #define at91_rtc_write(field, val) \
  78. writel_relaxed((val), at91_rtc_regs + field)
  79. struct at91_rtc_config {
  80. bool use_shadow_imr;
  81. bool has_correction;
  82. };
  83. static const struct at91_rtc_config *at91_rtc_config;
  84. static DECLARE_COMPLETION(at91_rtc_updated);
  85. static DECLARE_COMPLETION(at91_rtc_upd_rdy);
  86. static void __iomem *at91_rtc_regs;
  87. static int irq;
  88. static DEFINE_SPINLOCK(at91_rtc_lock);
  89. static u32 at91_rtc_shadow_imr;
  90. static bool suspended;
  91. static DEFINE_SPINLOCK(suspended_lock);
  92. static unsigned long cached_events;
  93. static u32 at91_rtc_imr;
  94. static struct clk *sclk;
  95. static void at91_rtc_write_ier(u32 mask)
  96. {
  97. unsigned long flags;
  98. spin_lock_irqsave(&at91_rtc_lock, flags);
  99. at91_rtc_shadow_imr |= mask;
  100. at91_rtc_write(AT91_RTC_IER, mask);
  101. spin_unlock_irqrestore(&at91_rtc_lock, flags);
  102. }
  103. static void at91_rtc_write_idr(u32 mask)
  104. {
  105. unsigned long flags;
  106. spin_lock_irqsave(&at91_rtc_lock, flags);
  107. at91_rtc_write(AT91_RTC_IDR, mask);
  108. /*
  109. * Register read back (of any RTC-register) needed to make sure
  110. * IDR-register write has reached the peripheral before updating
  111. * shadow mask.
  112. *
  113. * Note that there is still a possibility that the mask is updated
  114. * before interrupts have actually been disabled in hardware. The only
  115. * way to be certain would be to poll the IMR-register, which is is
  116. * the very register we are trying to emulate. The register read back
  117. * is a reasonable heuristic.
  118. */
  119. at91_rtc_read(AT91_RTC_SR);
  120. at91_rtc_shadow_imr &= ~mask;
  121. spin_unlock_irqrestore(&at91_rtc_lock, flags);
  122. }
  123. static u32 at91_rtc_read_imr(void)
  124. {
  125. unsigned long flags;
  126. u32 mask;
  127. if (at91_rtc_config->use_shadow_imr) {
  128. spin_lock_irqsave(&at91_rtc_lock, flags);
  129. mask = at91_rtc_shadow_imr;
  130. spin_unlock_irqrestore(&at91_rtc_lock, flags);
  131. } else {
  132. mask = at91_rtc_read(AT91_RTC_IMR);
  133. }
  134. return mask;
  135. }
  136. /*
  137. * Decode time/date into rtc_time structure
  138. */
  139. static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
  140. struct rtc_time *tm)
  141. {
  142. unsigned int time, date;
  143. /* must read twice in case it changes */
  144. do {
  145. time = at91_rtc_read(timereg);
  146. date = at91_rtc_read(calreg);
  147. } while ((time != at91_rtc_read(timereg)) ||
  148. (date != at91_rtc_read(calreg)));
  149. tm->tm_sec = bcd2bin(FIELD_GET(AT91_RTC_SEC, time));
  150. tm->tm_min = bcd2bin(FIELD_GET(AT91_RTC_MIN, time));
  151. tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time));
  152. /*
  153. * The Calendar Alarm register does not have a field for
  154. * the year - so these will return an invalid value.
  155. */
  156. tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */
  157. tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */
  158. tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1; /* day of the week [0-6], Sunday=0 */
  159. tm->tm_mon = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1;
  160. tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date));
  161. }
  162. /*
  163. * Read current time and date in RTC
  164. */
  165. static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
  166. {
  167. at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
  168. tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
  169. tm->tm_year = tm->tm_year - 1900;
  170. dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
  171. return 0;
  172. }
  173. /*
  174. * Set current time and date in RTC
  175. */
  176. static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
  177. {
  178. unsigned long cr;
  179. dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
  180. wait_for_completion(&at91_rtc_upd_rdy);
  181. /* Stop Time/Calendar from counting */
  182. cr = at91_rtc_read(AT91_RTC_CR);
  183. at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
  184. at91_rtc_write_ier(AT91_RTC_ACKUPD);
  185. wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
  186. at91_rtc_write_idr(AT91_RTC_ACKUPD);
  187. at91_rtc_write(AT91_RTC_TIMR,
  188. FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec))
  189. | FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min))
  190. | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour)));
  191. at91_rtc_write(AT91_RTC_CALR,
  192. FIELD_PREP(AT91_RTC_CENT,
  193. bin2bcd((tm->tm_year + 1900) / 100))
  194. | FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100))
  195. | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1))
  196. | FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1))
  197. | FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday)));
  198. /* Restart Time/Calendar */
  199. cr = at91_rtc_read(AT91_RTC_CR);
  200. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV);
  201. at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
  202. at91_rtc_write_ier(AT91_RTC_SECEV);
  203. return 0;
  204. }
  205. /*
  206. * Read alarm time and date in RTC
  207. */
  208. static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
  209. {
  210. struct rtc_time *tm = &alrm->time;
  211. at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
  212. tm->tm_year = -1;
  213. alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
  214. ? 1 : 0;
  215. dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm,
  216. alrm->enabled ? "en" : "dis");
  217. return 0;
  218. }
  219. /*
  220. * Set alarm time and date in RTC
  221. */
  222. static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  223. {
  224. struct rtc_time tm = alrm->time;
  225. at91_rtc_write_idr(AT91_RTC_ALARM);
  226. at91_rtc_write(AT91_RTC_TIMALR,
  227. FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec))
  228. | FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min))
  229. | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour))
  230. | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
  231. at91_rtc_write(AT91_RTC_CALALR,
  232. FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1))
  233. | FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday))
  234. | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
  235. if (alrm->enabled) {
  236. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
  237. at91_rtc_write_ier(AT91_RTC_ALARM);
  238. }
  239. dev_dbg(dev, "%s(): %ptR\n", __func__, &tm);
  240. return 0;
  241. }
  242. static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  243. {
  244. dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled);
  245. if (enabled) {
  246. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
  247. at91_rtc_write_ier(AT91_RTC_ALARM);
  248. } else
  249. at91_rtc_write_idr(AT91_RTC_ALARM);
  250. return 0;
  251. }
  252. static int at91_rtc_readoffset(struct device *dev, long *offset)
  253. {
  254. u32 mr = at91_rtc_read(AT91_RTC_MR);
  255. long val = FIELD_GET(AT91_RTC_CORRECTION, mr);
  256. if (!val) {
  257. *offset = 0;
  258. return 0;
  259. }
  260. val++;
  261. if (!(mr & AT91_RTC_NEGPPM))
  262. val = -val;
  263. if (!(mr & AT91_RTC_HIGHPPM))
  264. val *= AT91_RTC_CORR_LOW_RATIO;
  265. *offset = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, val);
  266. return 0;
  267. }
  268. static int at91_rtc_setoffset(struct device *dev, long offset)
  269. {
  270. long corr;
  271. u32 mr;
  272. if (offset > AT91_RTC_CORR_DIVIDEND / 2)
  273. return -ERANGE;
  274. if (offset < -AT91_RTC_CORR_DIVIDEND / 2)
  275. return -ERANGE;
  276. mr = at91_rtc_read(AT91_RTC_MR);
  277. mr &= ~(AT91_RTC_NEGPPM | AT91_RTC_CORRECTION | AT91_RTC_HIGHPPM);
  278. if (offset > 0)
  279. mr |= AT91_RTC_NEGPPM;
  280. else
  281. offset = -offset;
  282. /* offset less than 764 ppb, disable correction*/
  283. if (offset < 764) {
  284. at91_rtc_write(AT91_RTC_MR, mr & ~AT91_RTC_NEGPPM);
  285. return 0;
  286. }
  287. /*
  288. * 29208 ppb is the perfect cutoff between low range and high range
  289. * low range values are never better than high range value after that.
  290. */
  291. if (offset < 29208) {
  292. corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset * AT91_RTC_CORR_LOW_RATIO);
  293. } else {
  294. corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset);
  295. mr |= AT91_RTC_HIGHPPM;
  296. }
  297. if (corr > 128)
  298. corr = 128;
  299. mr |= FIELD_PREP(AT91_RTC_CORRECTION, corr - 1);
  300. at91_rtc_write(AT91_RTC_MR, mr);
  301. return 0;
  302. }
  303. /*
  304. * IRQ handler for the RTC
  305. */
  306. static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
  307. {
  308. struct platform_device *pdev = dev_id;
  309. struct rtc_device *rtc = platform_get_drvdata(pdev);
  310. unsigned int rtsr;
  311. unsigned long events = 0;
  312. int ret = IRQ_NONE;
  313. spin_lock(&suspended_lock);
  314. rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
  315. if (rtsr) { /* this interrupt is shared! Is it ours? */
  316. if (rtsr & AT91_RTC_ALARM)
  317. events |= (RTC_AF | RTC_IRQF);
  318. if (rtsr & AT91_RTC_SECEV) {
  319. complete(&at91_rtc_upd_rdy);
  320. at91_rtc_write_idr(AT91_RTC_SECEV);
  321. }
  322. if (rtsr & AT91_RTC_ACKUPD)
  323. complete(&at91_rtc_updated);
  324. at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */
  325. if (!suspended) {
  326. rtc_update_irq(rtc, 1, events);
  327. dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n",
  328. __func__, events >> 8, events & 0x000000FF);
  329. } else {
  330. cached_events |= events;
  331. at91_rtc_write_idr(at91_rtc_imr);
  332. pm_system_wakeup();
  333. }
  334. ret = IRQ_HANDLED;
  335. }
  336. spin_unlock(&suspended_lock);
  337. return ret;
  338. }
  339. static const struct at91_rtc_config at91rm9200_config = {
  340. };
  341. static const struct at91_rtc_config at91sam9x5_config = {
  342. .use_shadow_imr = true,
  343. };
  344. static const struct at91_rtc_config sama5d4_config = {
  345. .has_correction = true,
  346. };
  347. static const struct of_device_id at91_rtc_dt_ids[] = {
  348. {
  349. .compatible = "atmel,at91rm9200-rtc",
  350. .data = &at91rm9200_config,
  351. }, {
  352. .compatible = "atmel,at91sam9x5-rtc",
  353. .data = &at91sam9x5_config,
  354. }, {
  355. .compatible = "atmel,sama5d4-rtc",
  356. .data = &sama5d4_config,
  357. }, {
  358. .compatible = "atmel,sama5d2-rtc",
  359. .data = &sama5d4_config,
  360. }, {
  361. .compatible = "microchip,sam9x60-rtc",
  362. .data = &sama5d4_config,
  363. }, {
  364. /* sentinel */
  365. }
  366. };
  367. MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
  368. static const struct rtc_class_ops at91_rtc_ops = {
  369. .read_time = at91_rtc_readtime,
  370. .set_time = at91_rtc_settime,
  371. .read_alarm = at91_rtc_readalarm,
  372. .set_alarm = at91_rtc_setalarm,
  373. .alarm_irq_enable = at91_rtc_alarm_irq_enable,
  374. };
  375. static const struct rtc_class_ops sama5d4_rtc_ops = {
  376. .read_time = at91_rtc_readtime,
  377. .set_time = at91_rtc_settime,
  378. .read_alarm = at91_rtc_readalarm,
  379. .set_alarm = at91_rtc_setalarm,
  380. .alarm_irq_enable = at91_rtc_alarm_irq_enable,
  381. .set_offset = at91_rtc_setoffset,
  382. .read_offset = at91_rtc_readoffset,
  383. };
  384. /*
  385. * Initialize and install RTC driver
  386. */
  387. static int __init at91_rtc_probe(struct platform_device *pdev)
  388. {
  389. struct rtc_device *rtc;
  390. struct resource *regs;
  391. int ret = 0;
  392. at91_rtc_config = of_device_get_match_data(&pdev->dev);
  393. if (!at91_rtc_config)
  394. return -ENODEV;
  395. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  396. if (!regs) {
  397. dev_err(&pdev->dev, "no mmio resource defined\n");
  398. return -ENXIO;
  399. }
  400. irq = platform_get_irq(pdev, 0);
  401. if (irq < 0)
  402. return -ENXIO;
  403. at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start,
  404. resource_size(regs));
  405. if (!at91_rtc_regs) {
  406. dev_err(&pdev->dev, "failed to map registers, aborting.\n");
  407. return -ENOMEM;
  408. }
  409. rtc = devm_rtc_allocate_device(&pdev->dev);
  410. if (IS_ERR(rtc))
  411. return PTR_ERR(rtc);
  412. platform_set_drvdata(pdev, rtc);
  413. sclk = devm_clk_get(&pdev->dev, NULL);
  414. if (IS_ERR(sclk))
  415. return PTR_ERR(sclk);
  416. ret = clk_prepare_enable(sclk);
  417. if (ret) {
  418. dev_err(&pdev->dev, "Could not enable slow clock\n");
  419. return ret;
  420. }
  421. at91_rtc_write(AT91_RTC_CR, 0);
  422. at91_rtc_write(AT91_RTC_MR, at91_rtc_read(AT91_RTC_MR) & ~AT91_RTC_HRMOD);
  423. /* Disable all interrupts */
  424. at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
  425. AT91_RTC_SECEV | AT91_RTC_TIMEV |
  426. AT91_RTC_CALEV);
  427. ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt,
  428. IRQF_SHARED | IRQF_COND_SUSPEND,
  429. "at91_rtc", pdev);
  430. if (ret) {
  431. dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
  432. goto err_clk;
  433. }
  434. /* cpu init code should really have flagged this device as
  435. * being wake-capable; if it didn't, do that here.
  436. */
  437. if (!device_can_wakeup(&pdev->dev))
  438. device_init_wakeup(&pdev->dev, 1);
  439. if (at91_rtc_config->has_correction)
  440. rtc->ops = &sama5d4_rtc_ops;
  441. else
  442. rtc->ops = &at91_rtc_ops;
  443. rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
  444. rtc->range_max = RTC_TIMESTAMP_END_2099;
  445. ret = devm_rtc_register_device(rtc);
  446. if (ret)
  447. goto err_clk;
  448. /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
  449. * completion.
  450. */
  451. at91_rtc_write_ier(AT91_RTC_SECEV);
  452. dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
  453. return 0;
  454. err_clk:
  455. clk_disable_unprepare(sclk);
  456. return ret;
  457. }
  458. /*
  459. * Disable and remove the RTC driver
  460. */
  461. static int __exit at91_rtc_remove(struct platform_device *pdev)
  462. {
  463. /* Disable all interrupts */
  464. at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
  465. AT91_RTC_SECEV | AT91_RTC_TIMEV |
  466. AT91_RTC_CALEV);
  467. clk_disable_unprepare(sclk);
  468. return 0;
  469. }
  470. static void at91_rtc_shutdown(struct platform_device *pdev)
  471. {
  472. /* Disable all interrupts */
  473. at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
  474. AT91_RTC_SECEV | AT91_RTC_TIMEV |
  475. AT91_RTC_CALEV);
  476. }
  477. #ifdef CONFIG_PM_SLEEP
  478. /* AT91RM9200 RTC Power management control */
  479. static int at91_rtc_suspend(struct device *dev)
  480. {
  481. /* this IRQ is shared with DBGU and other hardware which isn't
  482. * necessarily doing PM like we are...
  483. */
  484. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
  485. at91_rtc_imr = at91_rtc_read_imr()
  486. & (AT91_RTC_ALARM|AT91_RTC_SECEV);
  487. if (at91_rtc_imr) {
  488. if (device_may_wakeup(dev)) {
  489. unsigned long flags;
  490. enable_irq_wake(irq);
  491. spin_lock_irqsave(&suspended_lock, flags);
  492. suspended = true;
  493. spin_unlock_irqrestore(&suspended_lock, flags);
  494. } else {
  495. at91_rtc_write_idr(at91_rtc_imr);
  496. }
  497. }
  498. return 0;
  499. }
  500. static int at91_rtc_resume(struct device *dev)
  501. {
  502. struct rtc_device *rtc = dev_get_drvdata(dev);
  503. if (at91_rtc_imr) {
  504. if (device_may_wakeup(dev)) {
  505. unsigned long flags;
  506. spin_lock_irqsave(&suspended_lock, flags);
  507. if (cached_events) {
  508. rtc_update_irq(rtc, 1, cached_events);
  509. cached_events = 0;
  510. }
  511. suspended = false;
  512. spin_unlock_irqrestore(&suspended_lock, flags);
  513. disable_irq_wake(irq);
  514. }
  515. at91_rtc_write_ier(at91_rtc_imr);
  516. }
  517. return 0;
  518. }
  519. #endif
  520. static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
  521. static struct platform_driver at91_rtc_driver = {
  522. .remove = __exit_p(at91_rtc_remove),
  523. .shutdown = at91_rtc_shutdown,
  524. .driver = {
  525. .name = "at91_rtc",
  526. .pm = &at91_rtc_pm_ops,
  527. .of_match_table = of_match_ptr(at91_rtc_dt_ids),
  528. },
  529. };
  530. module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe);
  531. MODULE_AUTHOR("Rick Bronson");
  532. MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
  533. MODULE_LICENSE("GPL");
  534. MODULE_ALIAS("platform:at91_rtc");