rtc-ab-b5ze-s3.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
  4. * I2C RTC / Alarm chip
  5. *
  6. * Copyright (C) 2014, Arnaud EBALARD <[email protected]>
  7. *
  8. * Detailed datasheet of the chip is available here:
  9. *
  10. * https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
  11. *
  12. * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/rtc.h>
  17. #include <linux/i2c.h>
  18. #include <linux/bcd.h>
  19. #include <linux/of.h>
  20. #include <linux/regmap.h>
  21. #include <linux/interrupt.h>
  22. #define DRV_NAME "rtc-ab-b5ze-s3"
  23. /* Control section */
  24. #define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
  25. #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
  26. #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
  27. #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
  28. #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
  29. #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
  30. #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
  31. #define ABB5ZES3_REG_CTRL1_CAP BIT(7)
  32. #define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
  33. #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
  34. #define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
  35. #define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
  36. #define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
  37. #define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
  38. #define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
  39. #define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
  40. #define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
  41. #define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
  42. #define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
  43. #define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
  44. #define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
  45. #define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
  46. #define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
  47. #define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
  48. #define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
  49. #define ABB5ZES3_CTRL_SEC_LEN 3
  50. /* RTC section */
  51. #define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
  52. #define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
  53. #define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
  54. #define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
  55. #define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
  56. #define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
  57. #define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
  58. #define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
  59. #define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
  60. #define ABB5ZES3_RTC_SEC_LEN 7
  61. /* Alarm section (enable bits are all active low) */
  62. #define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
  63. #define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
  64. #define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
  65. #define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
  66. #define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
  67. #define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
  68. #define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
  69. #define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
  70. #define ABB5ZES3_ALRM_SEC_LEN 4
  71. /* Frequency offset section */
  72. #define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
  73. #define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
  74. /* CLOCKOUT section */
  75. #define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
  76. #define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
  77. #define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
  78. #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
  79. #define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
  80. #define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
  81. #define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
  82. #define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
  83. #define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
  84. /* Timer A Section */
  85. #define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
  86. #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
  87. #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
  88. #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
  89. #define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
  90. #define ABB5ZES3_TIMA_SEC_LEN 2
  91. /* Timer B Section */
  92. #define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
  93. #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
  94. #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
  95. #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
  96. #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
  97. #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
  98. #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
  99. #define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
  100. #define ABB5ZES3_TIMB_SEC_LEN 2
  101. #define ABB5ZES3_MEM_MAP_LEN 0x14
  102. struct abb5zes3_rtc_data {
  103. struct rtc_device *rtc;
  104. struct regmap *regmap;
  105. int irq;
  106. bool battery_low;
  107. bool timer_alarm; /* current alarm is via timer A */
  108. };
  109. /*
  110. * Try and match register bits w/ fixed null values to see whether we
  111. * are dealing with an ABB5ZES3.
  112. */
  113. static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
  114. {
  115. u8 regs[ABB5ZES3_MEM_MAP_LEN];
  116. static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
  117. 0x80, 0xc0, 0xc0, 0xf8,
  118. 0xe0, 0x00, 0x00, 0x40,
  119. 0x40, 0x78, 0x00, 0x00,
  120. 0xf8, 0x00, 0x88, 0x00 };
  121. int ret, i;
  122. ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
  123. if (ret)
  124. return ret;
  125. for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
  126. if (regs[i] & mask[i]) /* check if bits are cleared */
  127. return -ENODEV;
  128. }
  129. return 0;
  130. }
  131. /* Clear alarm status bit. */
  132. static int _abb5zes3_rtc_clear_alarm(struct device *dev)
  133. {
  134. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  135. int ret;
  136. ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
  137. ABB5ZES3_REG_CTRL2_AF, 0);
  138. if (ret)
  139. dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
  140. return ret;
  141. }
  142. /* Enable or disable alarm (i.e. alarm interrupt generation) */
  143. static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
  144. {
  145. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  146. int ret;
  147. ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
  148. ABB5ZES3_REG_CTRL1_AIE,
  149. enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
  150. if (ret)
  151. dev_err(dev, "%s: writing alarm INT failed (%d)\n",
  152. __func__, ret);
  153. return ret;
  154. }
  155. /* Enable or disable timer (watchdog timer A interrupt generation) */
  156. static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
  157. {
  158. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  159. int ret;
  160. ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
  161. ABB5ZES3_REG_CTRL2_WTAIE,
  162. enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
  163. if (ret)
  164. dev_err(dev, "%s: writing timer INT failed (%d)\n",
  165. __func__, ret);
  166. return ret;
  167. }
  168. /*
  169. * Note: we only read, so regmap inner lock protection is sufficient, i.e.
  170. * we do not need driver's main lock protection.
  171. */
  172. static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
  173. {
  174. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  175. u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
  176. int ret = 0;
  177. /*
  178. * As we need to read CTRL1 register anyway to access 24/12h
  179. * mode bit, we do a single bulk read of both control and RTC
  180. * sections (they are consecutive). This also ease indexing
  181. * of register values after bulk read.
  182. */
  183. ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
  184. sizeof(regs));
  185. if (ret) {
  186. dev_err(dev, "%s: reading RTC time failed (%d)\n",
  187. __func__, ret);
  188. return ret;
  189. }
  190. /* If clock integrity is not guaranteed, do not return a time value */
  191. if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC)
  192. return -ENODATA;
  193. tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
  194. tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
  195. if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
  196. tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
  197. if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
  198. tm->tm_hour += 12;
  199. } else { /* 24hr mode */
  200. tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
  201. }
  202. tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
  203. tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
  204. tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
  205. tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
  206. return ret;
  207. }
  208. static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
  209. {
  210. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  211. u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
  212. int ret;
  213. regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
  214. regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
  215. regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
  216. regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
  217. regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
  218. regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
  219. regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
  220. ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
  221. regs + ABB5ZES3_REG_RTC_SC,
  222. ABB5ZES3_RTC_SEC_LEN);
  223. return ret;
  224. }
  225. /*
  226. * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
  227. * given number of seconds.
  228. */
  229. static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
  230. {
  231. *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
  232. *timer_a = secs;
  233. }
  234. /*
  235. * Return current number of seconds in Timer A. As we only use
  236. * timer A with a 1Hz freq, this is what we expect to have.
  237. */
  238. static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
  239. {
  240. if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
  241. return -EINVAL;
  242. *secs = timer_a;
  243. return 0;
  244. }
  245. /*
  246. * Read alarm currently configured via a watchdog timer using timer A. This
  247. * is done by reading current RTC time and adding remaining timer time.
  248. */
  249. static int _abb5zes3_rtc_read_timer(struct device *dev,
  250. struct rtc_wkalrm *alarm)
  251. {
  252. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  253. struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
  254. u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
  255. unsigned long rtc_secs;
  256. unsigned int reg;
  257. u8 timer_secs;
  258. int ret;
  259. /*
  260. * Instead of doing two separate calls, because they are consecutive,
  261. * we grab both clockout register and Timer A section. The latter is
  262. * used to decide if timer A is enabled (as a watchdog timer).
  263. */
  264. ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
  265. ABB5ZES3_TIMA_SEC_LEN + 1);
  266. if (ret) {
  267. dev_err(dev, "%s: reading Timer A section failed (%d)\n",
  268. __func__, ret);
  269. return ret;
  270. }
  271. /* get current time ... */
  272. ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
  273. if (ret)
  274. return ret;
  275. /* ... convert to seconds ... */
  276. rtc_secs = rtc_tm_to_time64(&rtc_tm);
  277. /* ... add remaining timer A time ... */
  278. ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
  279. if (ret)
  280. return ret;
  281. /* ... and convert back. */
  282. rtc_time64_to_tm(rtc_secs + timer_secs, alarm_tm);
  283. ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, &reg);
  284. if (ret) {
  285. dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
  286. __func__, ret);
  287. return ret;
  288. }
  289. alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
  290. return 0;
  291. }
  292. /* Read alarm currently configured via a RTC alarm registers. */
  293. static int _abb5zes3_rtc_read_alarm(struct device *dev,
  294. struct rtc_wkalrm *alarm)
  295. {
  296. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  297. struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
  298. unsigned long rtc_secs, alarm_secs;
  299. u8 regs[ABB5ZES3_ALRM_SEC_LEN];
  300. unsigned int reg;
  301. int ret;
  302. ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
  303. ABB5ZES3_ALRM_SEC_LEN);
  304. if (ret) {
  305. dev_err(dev, "%s: reading alarm section failed (%d)\n",
  306. __func__, ret);
  307. return ret;
  308. }
  309. alarm_tm->tm_sec = 0;
  310. alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
  311. alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
  312. alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
  313. alarm_tm->tm_wday = -1;
  314. /*
  315. * The alarm section does not store year/month. We use the ones in rtc
  316. * section as a basis and increment month and then year if needed to get
  317. * alarm after current time.
  318. */
  319. ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
  320. if (ret)
  321. return ret;
  322. alarm_tm->tm_year = rtc_tm.tm_year;
  323. alarm_tm->tm_mon = rtc_tm.tm_mon;
  324. rtc_secs = rtc_tm_to_time64(&rtc_tm);
  325. alarm_secs = rtc_tm_to_time64(alarm_tm);
  326. if (alarm_secs < rtc_secs) {
  327. if (alarm_tm->tm_mon == 11) {
  328. alarm_tm->tm_mon = 0;
  329. alarm_tm->tm_year += 1;
  330. } else {
  331. alarm_tm->tm_mon += 1;
  332. }
  333. }
  334. ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, &reg);
  335. if (ret) {
  336. dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
  337. __func__, ret);
  338. return ret;
  339. }
  340. alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
  341. return 0;
  342. }
  343. /*
  344. * As the Alarm mechanism supported by the chip is only accurate to the
  345. * minute, we use the watchdog timer mechanism provided by timer A
  346. * (up to 256 seconds w/ a second accuracy) for low alarm values (below
  347. * 4 minutes). Otherwise, we use the common alarm mechanism provided
  348. * by the chip. In order for that to work, we keep track of currently
  349. * configured timer type via 'timer_alarm' flag in our private data
  350. * structure.
  351. */
  352. static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  353. {
  354. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  355. int ret;
  356. if (data->timer_alarm)
  357. ret = _abb5zes3_rtc_read_timer(dev, alarm);
  358. else
  359. ret = _abb5zes3_rtc_read_alarm(dev, alarm);
  360. return ret;
  361. }
  362. /*
  363. * Set alarm using chip alarm mechanism. It is only accurate to the
  364. * minute (not the second). The function expects alarm interrupt to
  365. * be disabled.
  366. */
  367. static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  368. {
  369. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  370. struct rtc_time *alarm_tm = &alarm->time;
  371. u8 regs[ABB5ZES3_ALRM_SEC_LEN];
  372. struct rtc_time rtc_tm;
  373. int ret, enable = 1;
  374. if (!alarm->enabled) {
  375. enable = 0;
  376. } else {
  377. unsigned long rtc_secs, alarm_secs;
  378. /*
  379. * Chip only support alarms up to one month in the future. Let's
  380. * return an error if we get something after that limit.
  381. * Comparison is done by incrementing rtc_tm month field by one
  382. * and checking alarm value is still below.
  383. */
  384. ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
  385. if (ret)
  386. return ret;
  387. if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
  388. rtc_tm.tm_mon = 0;
  389. rtc_tm.tm_year += 1;
  390. } else {
  391. rtc_tm.tm_mon += 1;
  392. }
  393. rtc_secs = rtc_tm_to_time64(&rtc_tm);
  394. alarm_secs = rtc_tm_to_time64(alarm_tm);
  395. if (alarm_secs > rtc_secs) {
  396. dev_err(dev, "%s: alarm maximum is one month in the future (%d)\n",
  397. __func__, ret);
  398. return -EINVAL;
  399. }
  400. }
  401. /*
  402. * Program all alarm registers but DW one. For each register, setting
  403. * MSB to 0 enables associated alarm.
  404. */
  405. regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
  406. regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
  407. regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
  408. regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
  409. ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
  410. ABB5ZES3_ALRM_SEC_LEN);
  411. if (ret < 0) {
  412. dev_err(dev, "%s: writing ALARM section failed (%d)\n",
  413. __func__, ret);
  414. return ret;
  415. }
  416. /* Record currently configured alarm is not a timer */
  417. data->timer_alarm = 0;
  418. /* Enable or disable alarm interrupt generation */
  419. return _abb5zes3_rtc_update_alarm(dev, enable);
  420. }
  421. /*
  422. * Set alarm using timer watchdog (via timer A) mechanism. The function expects
  423. * timer A interrupt to be disabled.
  424. */
  425. static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
  426. u8 secs)
  427. {
  428. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  429. u8 regs[ABB5ZES3_TIMA_SEC_LEN];
  430. u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
  431. int ret = 0;
  432. /* Program given number of seconds to Timer A registers */
  433. sec_to_timer_a(secs, &regs[0], &regs[1]);
  434. ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
  435. ABB5ZES3_TIMA_SEC_LEN);
  436. if (ret < 0) {
  437. dev_err(dev, "%s: writing timer section failed\n", __func__);
  438. return ret;
  439. }
  440. /* Configure Timer A as a watchdog timer */
  441. ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
  442. mask, ABB5ZES3_REG_TIM_CLK_TAC1);
  443. if (ret)
  444. dev_err(dev, "%s: failed to update timer\n", __func__);
  445. /* Record currently configured alarm is a timer */
  446. data->timer_alarm = 1;
  447. /* Enable or disable timer interrupt generation */
  448. return _abb5zes3_rtc_update_timer(dev, alarm->enabled);
  449. }
  450. /*
  451. * The chip has an alarm which is only accurate to the minute. In order to
  452. * handle alarms below that limit, we use the watchdog timer function of
  453. * timer A. More precisely, the timer method is used for alarms below 240
  454. * seconds.
  455. */
  456. static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  457. {
  458. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  459. struct rtc_time *alarm_tm = &alarm->time;
  460. unsigned long rtc_secs, alarm_secs;
  461. struct rtc_time rtc_tm;
  462. int ret;
  463. ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
  464. if (ret)
  465. return ret;
  466. rtc_secs = rtc_tm_to_time64(&rtc_tm);
  467. alarm_secs = rtc_tm_to_time64(alarm_tm);
  468. /* Let's first disable both the alarm and the timer interrupts */
  469. ret = _abb5zes3_rtc_update_alarm(dev, false);
  470. if (ret < 0) {
  471. dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
  472. ret);
  473. return ret;
  474. }
  475. ret = _abb5zes3_rtc_update_timer(dev, false);
  476. if (ret < 0) {
  477. dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
  478. ret);
  479. return ret;
  480. }
  481. data->timer_alarm = 0;
  482. /*
  483. * Let's now configure the alarm; if we are expected to ring in
  484. * more than 240s, then we setup an alarm. Otherwise, a timer.
  485. */
  486. if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
  487. ret = _abb5zes3_rtc_set_timer(dev, alarm,
  488. alarm_secs - rtc_secs);
  489. else
  490. ret = _abb5zes3_rtc_set_alarm(dev, alarm);
  491. if (ret)
  492. dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
  493. ret);
  494. return ret;
  495. }
  496. /* Enable or disable battery low irq generation */
  497. static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
  498. bool enable)
  499. {
  500. return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
  501. ABB5ZES3_REG_CTRL3_BLIE,
  502. enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
  503. }
  504. /*
  505. * Check current RTC status and enable/disable what needs to be. Return 0 if
  506. * everything went ok and a negative value upon error.
  507. */
  508. static int abb5zes3_rtc_check_setup(struct device *dev)
  509. {
  510. struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
  511. struct regmap *regmap = data->regmap;
  512. unsigned int reg;
  513. int ret;
  514. u8 mask;
  515. /*
  516. * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
  517. * is disabled here to prevent polluting the interrupt line and
  518. * uselessly triggering the IRQ handler we install for alarm and battery
  519. * low events. Note: this is done before clearing int. status below
  520. * in this function.
  521. * We also disable all timers and set timer interrupt to permanent (not
  522. * pulsed).
  523. */
  524. mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
  525. ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
  526. ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
  527. ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
  528. ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
  529. ABB5ZES3_REG_TIM_CLK_COF0 |
  530. ABB5ZES3_REG_TIM_CLK_COF1 |
  531. ABB5ZES3_REG_TIM_CLK_COF2);
  532. if (ret < 0) {
  533. dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
  534. __func__, ret);
  535. return ret;
  536. }
  537. /*
  538. * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
  539. * individually by clearing/setting MSB of each associated register. So,
  540. * we set all alarm enable bits to disable current alarm setting.
  541. */
  542. mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
  543. ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
  544. ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
  545. if (ret < 0) {
  546. dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
  547. __func__, ret);
  548. return ret;
  549. }
  550. /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
  551. mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
  552. ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
  553. ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
  554. ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
  555. if (ret < 0) {
  556. dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
  557. __func__, ret);
  558. return ret;
  559. }
  560. /*
  561. * Set Control 2 register (timer int. disabled, alarm status cleared).
  562. * WTAF is read-only and cleared automatically by reading the register.
  563. */
  564. mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
  565. ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
  566. ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
  567. ABB5ZES3_REG_CTRL2_CTAF);
  568. ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
  569. if (ret < 0) {
  570. dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
  571. __func__, ret);
  572. return ret;
  573. }
  574. /*
  575. * Enable battery low detection function and battery switchover function
  576. * (standard mode). Disable associated interrupts. Clear battery
  577. * switchover flag but not battery low flag. The latter is checked
  578. * later below.
  579. */
  580. mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
  581. ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
  582. ABB5ZES3_REG_CTRL3_BSIE | ABB5ZES3_REG_CTRL3_BSF);
  583. ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
  584. if (ret < 0) {
  585. dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
  586. __func__, ret);
  587. return ret;
  588. }
  589. /* Check oscillator integrity flag */
  590. ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, &reg);
  591. if (ret < 0) {
  592. dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
  593. __func__, ret);
  594. return ret;
  595. }
  596. if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
  597. dev_err(dev, "clock integrity not guaranteed. Osc. has stopped or has been interrupted.\n");
  598. dev_err(dev, "change battery (if not already done) and then set time to reset osc. failure flag.\n");
  599. }
  600. /*
  601. * Check battery low flag at startup: this allows reporting battery
  602. * is low at startup when IRQ line is not connected. Note: we record
  603. * current status to avoid reenabling this interrupt later in probe
  604. * function if battery is low.
  605. */
  606. ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, &reg);
  607. if (ret < 0) {
  608. dev_err(dev, "%s: unable to read battery low flag (%d)\n",
  609. __func__, ret);
  610. return ret;
  611. }
  612. data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
  613. if (data->battery_low) {
  614. dev_err(dev, "RTC battery is low; please, consider changing it!\n");
  615. ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
  616. if (ret)
  617. dev_err(dev, "%s: disabling battery low interrupt generation failed (%d)\n",
  618. __func__, ret);
  619. }
  620. return ret;
  621. }
  622. static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
  623. unsigned int enable)
  624. {
  625. struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
  626. int ret = 0;
  627. if (rtc_data->irq) {
  628. if (rtc_data->timer_alarm)
  629. ret = _abb5zes3_rtc_update_timer(dev, enable);
  630. else
  631. ret = _abb5zes3_rtc_update_alarm(dev, enable);
  632. }
  633. return ret;
  634. }
  635. static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
  636. {
  637. struct i2c_client *client = data;
  638. struct device *dev = &client->dev;
  639. struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
  640. struct rtc_device *rtc = rtc_data->rtc;
  641. u8 regs[ABB5ZES3_CTRL_SEC_LEN];
  642. int ret, handled = IRQ_NONE;
  643. ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
  644. ABB5ZES3_CTRL_SEC_LEN);
  645. if (ret) {
  646. dev_err(dev, "%s: unable to read control section (%d)!\n",
  647. __func__, ret);
  648. return handled;
  649. }
  650. /*
  651. * Check battery low detection flag and disable battery low interrupt
  652. * generation if flag is set (interrupt can only be cleared when
  653. * battery is replaced).
  654. */
  655. if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
  656. dev_err(dev, "RTC battery is low; please change it!\n");
  657. _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
  658. handled = IRQ_HANDLED;
  659. }
  660. /* Check alarm flag */
  661. if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
  662. dev_dbg(dev, "RTC alarm!\n");
  663. rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
  664. /* Acknowledge and disable the alarm */
  665. _abb5zes3_rtc_clear_alarm(dev);
  666. _abb5zes3_rtc_update_alarm(dev, 0);
  667. handled = IRQ_HANDLED;
  668. }
  669. /* Check watchdog Timer A flag */
  670. if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
  671. dev_dbg(dev, "RTC timer!\n");
  672. rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
  673. /*
  674. * Acknowledge and disable the alarm. Note: WTAF
  675. * flag had been cleared when reading CTRL2
  676. */
  677. _abb5zes3_rtc_update_timer(dev, 0);
  678. rtc_data->timer_alarm = 0;
  679. handled = IRQ_HANDLED;
  680. }
  681. return handled;
  682. }
  683. static const struct rtc_class_ops rtc_ops = {
  684. .read_time = _abb5zes3_rtc_read_time,
  685. .set_time = abb5zes3_rtc_set_time,
  686. .read_alarm = abb5zes3_rtc_read_alarm,
  687. .set_alarm = abb5zes3_rtc_set_alarm,
  688. .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
  689. };
  690. static const struct regmap_config abb5zes3_rtc_regmap_config = {
  691. .reg_bits = 8,
  692. .val_bits = 8,
  693. };
  694. static int abb5zes3_probe(struct i2c_client *client)
  695. {
  696. struct abb5zes3_rtc_data *data = NULL;
  697. struct device *dev = &client->dev;
  698. struct regmap *regmap;
  699. int ret;
  700. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
  701. I2C_FUNC_SMBUS_BYTE_DATA |
  702. I2C_FUNC_SMBUS_I2C_BLOCK))
  703. return -ENODEV;
  704. regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
  705. if (IS_ERR(regmap)) {
  706. ret = PTR_ERR(regmap);
  707. dev_err(dev, "%s: regmap allocation failed: %d\n",
  708. __func__, ret);
  709. return ret;
  710. }
  711. ret = abb5zes3_i2c_validate_chip(regmap);
  712. if (ret)
  713. return ret;
  714. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  715. if (!data)
  716. return -ENOMEM;
  717. data->regmap = regmap;
  718. dev_set_drvdata(dev, data);
  719. ret = abb5zes3_rtc_check_setup(dev);
  720. if (ret)
  721. return ret;
  722. data->rtc = devm_rtc_allocate_device(dev);
  723. ret = PTR_ERR_OR_ZERO(data->rtc);
  724. if (ret) {
  725. dev_err(dev, "%s: unable to allocate RTC device (%d)\n",
  726. __func__, ret);
  727. return ret;
  728. }
  729. if (client->irq > 0) {
  730. ret = devm_request_threaded_irq(dev, client->irq, NULL,
  731. _abb5zes3_rtc_interrupt,
  732. IRQF_SHARED | IRQF_ONESHOT,
  733. DRV_NAME, client);
  734. if (!ret) {
  735. device_init_wakeup(dev, true);
  736. data->irq = client->irq;
  737. dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
  738. client->irq);
  739. } else {
  740. dev_err(dev, "%s: irq %d unavailable (%d)\n",
  741. __func__, client->irq, ret);
  742. goto err;
  743. }
  744. }
  745. data->rtc->ops = &rtc_ops;
  746. data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  747. data->rtc->range_max = RTC_TIMESTAMP_END_2099;
  748. /* Enable battery low detection interrupt if battery not already low */
  749. if (!data->battery_low && data->irq) {
  750. ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
  751. if (ret) {
  752. dev_err(dev, "%s: enabling battery low interrupt generation failed (%d)\n",
  753. __func__, ret);
  754. goto err;
  755. }
  756. }
  757. ret = devm_rtc_register_device(data->rtc);
  758. err:
  759. if (ret && data->irq)
  760. device_init_wakeup(dev, false);
  761. return ret;
  762. }
  763. #ifdef CONFIG_PM_SLEEP
  764. static int abb5zes3_rtc_suspend(struct device *dev)
  765. {
  766. struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
  767. if (device_may_wakeup(dev))
  768. return enable_irq_wake(rtc_data->irq);
  769. return 0;
  770. }
  771. static int abb5zes3_rtc_resume(struct device *dev)
  772. {
  773. struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
  774. if (device_may_wakeup(dev))
  775. return disable_irq_wake(rtc_data->irq);
  776. return 0;
  777. }
  778. #endif
  779. static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
  780. abb5zes3_rtc_resume);
  781. #ifdef CONFIG_OF
  782. static const struct of_device_id abb5zes3_dt_match[] = {
  783. { .compatible = "abracon,abb5zes3" },
  784. { },
  785. };
  786. MODULE_DEVICE_TABLE(of, abb5zes3_dt_match);
  787. #endif
  788. static const struct i2c_device_id abb5zes3_id[] = {
  789. { "abb5zes3", 0 },
  790. { }
  791. };
  792. MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
  793. static struct i2c_driver abb5zes3_driver = {
  794. .driver = {
  795. .name = DRV_NAME,
  796. .pm = &abb5zes3_rtc_pm_ops,
  797. .of_match_table = of_match_ptr(abb5zes3_dt_match),
  798. },
  799. .probe_new = abb5zes3_probe,
  800. .id_table = abb5zes3_id,
  801. };
  802. module_i2c_driver(abb5zes3_driver);
  803. MODULE_AUTHOR("Arnaud EBALARD <[email protected]>");
  804. MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
  805. MODULE_LICENSE("GPL");