pwm-sun4i.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Allwinner sun4i Pulse Width Modulation Controller
  4. *
  5. * Copyright (C) 2014 Alexandre Belloni <[email protected]>
  6. *
  7. * Limitations:
  8. * - When outputing the source clock directly, the PWM logic will be bypassed
  9. * and the currently running period is not guaranteed to be completed
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #include <linux/reset.h>
  23. #include <linux/slab.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/time.h>
  26. #define PWM_CTRL_REG 0x0
  27. #define PWM_CH_PRD_BASE 0x4
  28. #define PWM_CH_PRD_OFFSET 0x4
  29. #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
  30. #define PWMCH_OFFSET 15
  31. #define PWM_PRESCAL_MASK GENMASK(3, 0)
  32. #define PWM_PRESCAL_OFF 0
  33. #define PWM_EN BIT(4)
  34. #define PWM_ACT_STATE BIT(5)
  35. #define PWM_CLK_GATING BIT(6)
  36. #define PWM_MODE BIT(7)
  37. #define PWM_PULSE BIT(8)
  38. #define PWM_BYPASS BIT(9)
  39. #define PWM_RDY_BASE 28
  40. #define PWM_RDY_OFFSET 1
  41. #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
  42. #define PWM_PRD(prd) (((prd) - 1) << 16)
  43. #define PWM_PRD_MASK GENMASK(15, 0)
  44. #define PWM_DTY_MASK GENMASK(15, 0)
  45. #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
  46. #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
  47. #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
  48. #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
  49. static const u32 prescaler_table[] = {
  50. 120,
  51. 180,
  52. 240,
  53. 360,
  54. 480,
  55. 0,
  56. 0,
  57. 0,
  58. 12000,
  59. 24000,
  60. 36000,
  61. 48000,
  62. 72000,
  63. 0,
  64. 0,
  65. 0, /* Actually 1 but tested separately */
  66. };
  67. struct sun4i_pwm_data {
  68. bool has_prescaler_bypass;
  69. bool has_direct_mod_clk_output;
  70. unsigned int npwm;
  71. };
  72. struct sun4i_pwm_chip {
  73. struct pwm_chip chip;
  74. struct clk *bus_clk;
  75. struct clk *clk;
  76. struct reset_control *rst;
  77. void __iomem *base;
  78. spinlock_t ctrl_lock;
  79. const struct sun4i_pwm_data *data;
  80. };
  81. static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
  82. {
  83. return container_of(chip, struct sun4i_pwm_chip, chip);
  84. }
  85. static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
  86. unsigned long offset)
  87. {
  88. return readl(chip->base + offset);
  89. }
  90. static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
  91. u32 val, unsigned long offset)
  92. {
  93. writel(val, chip->base + offset);
  94. }
  95. static int sun4i_pwm_get_state(struct pwm_chip *chip,
  96. struct pwm_device *pwm,
  97. struct pwm_state *state)
  98. {
  99. struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
  100. u64 clk_rate, tmp;
  101. u32 val;
  102. unsigned int prescaler;
  103. clk_rate = clk_get_rate(sun4i_pwm->clk);
  104. val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  105. /*
  106. * PWM chapter in H6 manual has a diagram which explains that if bypass
  107. * bit is set, no other setting has any meaning. Even more, experiment
  108. * proved that also enable bit is ignored in this case.
  109. */
  110. if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
  111. sun4i_pwm->data->has_direct_mod_clk_output) {
  112. state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
  113. state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
  114. state->polarity = PWM_POLARITY_NORMAL;
  115. state->enabled = true;
  116. return 0;
  117. }
  118. if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
  119. sun4i_pwm->data->has_prescaler_bypass)
  120. prescaler = 1;
  121. else
  122. prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
  123. if (prescaler == 0)
  124. return 0;
  125. if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
  126. state->polarity = PWM_POLARITY_NORMAL;
  127. else
  128. state->polarity = PWM_POLARITY_INVERSED;
  129. if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
  130. BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
  131. state->enabled = true;
  132. else
  133. state->enabled = false;
  134. val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
  135. tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
  136. state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  137. tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
  138. state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  139. return 0;
  140. }
  141. static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
  142. const struct pwm_state *state,
  143. u32 *dty, u32 *prd, unsigned int *prsclr,
  144. bool *bypass)
  145. {
  146. u64 clk_rate, div = 0;
  147. unsigned int prescaler = 0;
  148. clk_rate = clk_get_rate(sun4i_pwm->clk);
  149. *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
  150. state->enabled &&
  151. (state->period * clk_rate >= NSEC_PER_SEC) &&
  152. (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
  153. (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
  154. /* Skip calculation of other parameters if we bypass them */
  155. if (*bypass)
  156. return 0;
  157. if (sun4i_pwm->data->has_prescaler_bypass) {
  158. /* First, test without any prescaler when available */
  159. prescaler = PWM_PRESCAL_MASK;
  160. /*
  161. * When not using any prescaler, the clock period in nanoseconds
  162. * is not an integer so round it half up instead of
  163. * truncating to get less surprising values.
  164. */
  165. div = clk_rate * state->period + NSEC_PER_SEC / 2;
  166. do_div(div, NSEC_PER_SEC);
  167. if (div - 1 > PWM_PRD_MASK)
  168. prescaler = 0;
  169. }
  170. if (prescaler == 0) {
  171. /* Go up from the first divider */
  172. for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
  173. unsigned int pval = prescaler_table[prescaler];
  174. if (!pval)
  175. continue;
  176. div = clk_rate;
  177. do_div(div, pval);
  178. div = div * state->period;
  179. do_div(div, NSEC_PER_SEC);
  180. if (div - 1 <= PWM_PRD_MASK)
  181. break;
  182. }
  183. if (div - 1 > PWM_PRD_MASK)
  184. return -EINVAL;
  185. }
  186. *prd = div;
  187. div *= state->duty_cycle;
  188. do_div(div, state->period);
  189. *dty = div;
  190. *prsclr = prescaler;
  191. return 0;
  192. }
  193. static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  194. const struct pwm_state *state)
  195. {
  196. struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
  197. struct pwm_state cstate;
  198. u32 ctrl, duty = 0, period = 0, val;
  199. int ret;
  200. unsigned int delay_us, prescaler = 0;
  201. bool bypass;
  202. pwm_get_state(pwm, &cstate);
  203. if (!cstate.enabled) {
  204. ret = clk_prepare_enable(sun4i_pwm->clk);
  205. if (ret) {
  206. dev_err(chip->dev, "failed to enable PWM clock\n");
  207. return ret;
  208. }
  209. }
  210. ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
  211. &bypass);
  212. if (ret) {
  213. dev_err(chip->dev, "period exceeds the maximum value\n");
  214. if (!cstate.enabled)
  215. clk_disable_unprepare(sun4i_pwm->clk);
  216. return ret;
  217. }
  218. spin_lock(&sun4i_pwm->ctrl_lock);
  219. ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  220. if (sun4i_pwm->data->has_direct_mod_clk_output) {
  221. if (bypass) {
  222. ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
  223. /* We can skip other parameter */
  224. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  225. spin_unlock(&sun4i_pwm->ctrl_lock);
  226. return 0;
  227. }
  228. ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
  229. }
  230. if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
  231. /* Prescaler changed, the clock has to be gated */
  232. ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
  233. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  234. ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
  235. ctrl |= BIT_CH(prescaler, pwm->hwpwm);
  236. }
  237. val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
  238. sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
  239. if (state->polarity != PWM_POLARITY_NORMAL)
  240. ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
  241. else
  242. ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
  243. ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
  244. if (state->enabled)
  245. ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
  246. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  247. spin_unlock(&sun4i_pwm->ctrl_lock);
  248. if (state->enabled)
  249. return 0;
  250. /* We need a full period to elapse before disabling the channel. */
  251. delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
  252. if ((delay_us / 500) > MAX_UDELAY_MS)
  253. msleep(delay_us / 1000 + 1);
  254. else
  255. usleep_range(delay_us, delay_us * 2);
  256. spin_lock(&sun4i_pwm->ctrl_lock);
  257. ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  258. ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
  259. ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
  260. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  261. spin_unlock(&sun4i_pwm->ctrl_lock);
  262. clk_disable_unprepare(sun4i_pwm->clk);
  263. return 0;
  264. }
  265. static const struct pwm_ops sun4i_pwm_ops = {
  266. .apply = sun4i_pwm_apply,
  267. .get_state = sun4i_pwm_get_state,
  268. .owner = THIS_MODULE,
  269. };
  270. static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
  271. .has_prescaler_bypass = false,
  272. .npwm = 2,
  273. };
  274. static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
  275. .has_prescaler_bypass = true,
  276. .npwm = 2,
  277. };
  278. static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
  279. .has_prescaler_bypass = true,
  280. .npwm = 1,
  281. };
  282. static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
  283. .has_prescaler_bypass = true,
  284. .has_direct_mod_clk_output = true,
  285. .npwm = 1,
  286. };
  287. static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
  288. .has_prescaler_bypass = true,
  289. .has_direct_mod_clk_output = true,
  290. .npwm = 2,
  291. };
  292. static const struct of_device_id sun4i_pwm_dt_ids[] = {
  293. {
  294. .compatible = "allwinner,sun4i-a10-pwm",
  295. .data = &sun4i_pwm_dual_nobypass,
  296. }, {
  297. .compatible = "allwinner,sun5i-a10s-pwm",
  298. .data = &sun4i_pwm_dual_bypass,
  299. }, {
  300. .compatible = "allwinner,sun5i-a13-pwm",
  301. .data = &sun4i_pwm_single_bypass,
  302. }, {
  303. .compatible = "allwinner,sun7i-a20-pwm",
  304. .data = &sun4i_pwm_dual_bypass,
  305. }, {
  306. .compatible = "allwinner,sun8i-h3-pwm",
  307. .data = &sun4i_pwm_single_bypass,
  308. }, {
  309. .compatible = "allwinner,sun50i-a64-pwm",
  310. .data = &sun50i_a64_pwm_data,
  311. }, {
  312. .compatible = "allwinner,sun50i-h6-pwm",
  313. .data = &sun50i_h6_pwm_data,
  314. }, {
  315. /* sentinel */
  316. },
  317. };
  318. MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
  319. static int sun4i_pwm_probe(struct platform_device *pdev)
  320. {
  321. struct sun4i_pwm_chip *sun4ichip;
  322. int ret;
  323. sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
  324. if (!sun4ichip)
  325. return -ENOMEM;
  326. sun4ichip->data = of_device_get_match_data(&pdev->dev);
  327. if (!sun4ichip->data)
  328. return -ENODEV;
  329. sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
  330. if (IS_ERR(sun4ichip->base))
  331. return PTR_ERR(sun4ichip->base);
  332. /*
  333. * All hardware variants need a source clock that is divided and
  334. * then feeds the counter that defines the output wave form. In the
  335. * device tree this clock is either unnamed or called "mod".
  336. * Some variants (e.g. H6) need another clock to access the
  337. * hardware registers; this is called "bus".
  338. * So we request "mod" first (and ignore the corner case that a
  339. * parent provides a "mod" clock while the right one would be the
  340. * unnamed one of the PWM device) and if this is not found we fall
  341. * back to the first clock of the PWM.
  342. */
  343. sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
  344. if (IS_ERR(sun4ichip->clk))
  345. return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
  346. "get mod clock failed\n");
  347. if (!sun4ichip->clk) {
  348. sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
  349. if (IS_ERR(sun4ichip->clk))
  350. return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
  351. "get unnamed clock failed\n");
  352. }
  353. sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
  354. if (IS_ERR(sun4ichip->bus_clk))
  355. return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
  356. "get bus clock failed\n");
  357. sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  358. if (IS_ERR(sun4ichip->rst))
  359. return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
  360. "get reset failed\n");
  361. /* Deassert reset */
  362. ret = reset_control_deassert(sun4ichip->rst);
  363. if (ret) {
  364. dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
  365. ERR_PTR(ret));
  366. return ret;
  367. }
  368. /*
  369. * We're keeping the bus clock on for the sake of simplicity.
  370. * Actually it only needs to be on for hardware register accesses.
  371. */
  372. ret = clk_prepare_enable(sun4ichip->bus_clk);
  373. if (ret) {
  374. dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
  375. ERR_PTR(ret));
  376. goto err_bus;
  377. }
  378. sun4ichip->chip.dev = &pdev->dev;
  379. sun4ichip->chip.ops = &sun4i_pwm_ops;
  380. sun4ichip->chip.npwm = sun4ichip->data->npwm;
  381. spin_lock_init(&sun4ichip->ctrl_lock);
  382. ret = pwmchip_add(&sun4ichip->chip);
  383. if (ret < 0) {
  384. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  385. goto err_pwm_add;
  386. }
  387. platform_set_drvdata(pdev, sun4ichip);
  388. return 0;
  389. err_pwm_add:
  390. clk_disable_unprepare(sun4ichip->bus_clk);
  391. err_bus:
  392. reset_control_assert(sun4ichip->rst);
  393. return ret;
  394. }
  395. static int sun4i_pwm_remove(struct platform_device *pdev)
  396. {
  397. struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);
  398. pwmchip_remove(&sun4ichip->chip);
  399. clk_disable_unprepare(sun4ichip->bus_clk);
  400. reset_control_assert(sun4ichip->rst);
  401. return 0;
  402. }
  403. static struct platform_driver sun4i_pwm_driver = {
  404. .driver = {
  405. .name = "sun4i-pwm",
  406. .of_match_table = sun4i_pwm_dt_ids,
  407. },
  408. .probe = sun4i_pwm_probe,
  409. .remove = sun4i_pwm_remove,
  410. };
  411. module_platform_driver(sun4i_pwm_driver);
  412. MODULE_ALIAS("platform:sun4i-pwm");
  413. MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
  414. MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
  415. MODULE_LICENSE("GPL v2");