pwm-lpc32xx.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2012 Alexandre Pereira da Silva <[email protected]>
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/err.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pwm.h>
  14. #include <linux/slab.h>
  15. struct lpc32xx_pwm_chip {
  16. struct pwm_chip chip;
  17. struct clk *clk;
  18. void __iomem *base;
  19. };
  20. #define PWM_ENABLE BIT(31)
  21. #define PWM_PIN_LEVEL BIT(30)
  22. #define to_lpc32xx_pwm_chip(_chip) \
  23. container_of(_chip, struct lpc32xx_pwm_chip, chip)
  24. static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  25. int duty_ns, int period_ns)
  26. {
  27. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  28. unsigned long long c;
  29. int period_cycles, duty_cycles;
  30. u32 val;
  31. c = clk_get_rate(lpc32xx->clk);
  32. /* The highest acceptable divisor is 256, which is represented by 0 */
  33. period_cycles = div64_u64(c * period_ns,
  34. (unsigned long long)NSEC_PER_SEC * 256);
  35. if (!period_cycles || period_cycles > 256)
  36. return -ERANGE;
  37. if (period_cycles == 256)
  38. period_cycles = 0;
  39. /* Compute 256 x #duty/period value and care for corner cases */
  40. duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
  41. period_ns);
  42. if (!duty_cycles)
  43. duty_cycles = 1;
  44. if (duty_cycles > 255)
  45. duty_cycles = 255;
  46. val = readl(lpc32xx->base);
  47. val &= ~0xFFFF;
  48. val |= (period_cycles << 8) | duty_cycles;
  49. writel(val, lpc32xx->base);
  50. return 0;
  51. }
  52. static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  53. {
  54. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  55. u32 val;
  56. int ret;
  57. ret = clk_prepare_enable(lpc32xx->clk);
  58. if (ret)
  59. return ret;
  60. val = readl(lpc32xx->base);
  61. val |= PWM_ENABLE;
  62. writel(val, lpc32xx->base);
  63. return 0;
  64. }
  65. static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  66. {
  67. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  68. u32 val;
  69. val = readl(lpc32xx->base);
  70. val &= ~PWM_ENABLE;
  71. writel(val, lpc32xx->base);
  72. clk_disable_unprepare(lpc32xx->clk);
  73. }
  74. static int lpc32xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  75. const struct pwm_state *state)
  76. {
  77. int err;
  78. if (state->polarity != PWM_POLARITY_NORMAL)
  79. return -EINVAL;
  80. if (!state->enabled) {
  81. if (pwm->state.enabled)
  82. lpc32xx_pwm_disable(chip, pwm);
  83. return 0;
  84. }
  85. err = lpc32xx_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
  86. if (err)
  87. return err;
  88. if (!pwm->state.enabled)
  89. err = lpc32xx_pwm_enable(chip, pwm);
  90. return err;
  91. }
  92. static const struct pwm_ops lpc32xx_pwm_ops = {
  93. .apply = lpc32xx_pwm_apply,
  94. .owner = THIS_MODULE,
  95. };
  96. static int lpc32xx_pwm_probe(struct platform_device *pdev)
  97. {
  98. struct lpc32xx_pwm_chip *lpc32xx;
  99. int ret;
  100. u32 val;
  101. lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
  102. if (!lpc32xx)
  103. return -ENOMEM;
  104. lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
  105. if (IS_ERR(lpc32xx->base))
  106. return PTR_ERR(lpc32xx->base);
  107. lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
  108. if (IS_ERR(lpc32xx->clk))
  109. return PTR_ERR(lpc32xx->clk);
  110. lpc32xx->chip.dev = &pdev->dev;
  111. lpc32xx->chip.ops = &lpc32xx_pwm_ops;
  112. lpc32xx->chip.npwm = 1;
  113. /* If PWM is disabled, configure the output to the default value */
  114. val = readl(lpc32xx->base);
  115. val &= ~PWM_PIN_LEVEL;
  116. writel(val, lpc32xx->base);
  117. ret = devm_pwmchip_add(&pdev->dev, &lpc32xx->chip);
  118. if (ret < 0) {
  119. dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
  125. { .compatible = "nxp,lpc3220-pwm", },
  126. { /* sentinel */ }
  127. };
  128. MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
  129. static struct platform_driver lpc32xx_pwm_driver = {
  130. .driver = {
  131. .name = "lpc32xx-pwm",
  132. .of_match_table = lpc32xx_pwm_dt_ids,
  133. },
  134. .probe = lpc32xx_pwm_probe,
  135. };
  136. module_platform_driver(lpc32xx_pwm_driver);
  137. MODULE_ALIAS("platform:lpc32xx-pwm");
  138. MODULE_AUTHOR("Alexandre Pereira da Silva <[email protected]>");
  139. MODULE_DESCRIPTION("LPC32XX PWM Driver");
  140. MODULE_LICENSE("GPL v2");