pwm-imx27.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * simple driver for PWM (Pulse Width Modulator) controller
  4. *
  5. * Derived from pxa PWM driver by eric miao <[email protected]>
  6. *
  7. * Limitations:
  8. * - When disabled the output is driven to 0 independent of the configured
  9. * polarity.
  10. */
  11. #include <linux/bitfield.h>
  12. #include <linux/bitops.h>
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #include <linux/slab.h>
  23. #define MX3_PWMCR 0x00 /* PWM Control Register */
  24. #define MX3_PWMSR 0x04 /* PWM Status Register */
  25. #define MX3_PWMSAR 0x0C /* PWM Sample Register */
  26. #define MX3_PWMPR 0x10 /* PWM Period Register */
  27. #define MX3_PWMCR_FWM GENMASK(27, 26)
  28. #define MX3_PWMCR_STOPEN BIT(25)
  29. #define MX3_PWMCR_DOZEN BIT(24)
  30. #define MX3_PWMCR_WAITEN BIT(23)
  31. #define MX3_PWMCR_DBGEN BIT(22)
  32. #define MX3_PWMCR_BCTR BIT(21)
  33. #define MX3_PWMCR_HCTR BIT(20)
  34. #define MX3_PWMCR_POUTC GENMASK(19, 18)
  35. #define MX3_PWMCR_POUTC_NORMAL 0
  36. #define MX3_PWMCR_POUTC_INVERTED 1
  37. #define MX3_PWMCR_POUTC_OFF 2
  38. #define MX3_PWMCR_CLKSRC GENMASK(17, 16)
  39. #define MX3_PWMCR_CLKSRC_OFF 0
  40. #define MX3_PWMCR_CLKSRC_IPG 1
  41. #define MX3_PWMCR_CLKSRC_IPG_HIGH 2
  42. #define MX3_PWMCR_CLKSRC_IPG_32K 3
  43. #define MX3_PWMCR_PRESCALER GENMASK(15, 4)
  44. #define MX3_PWMCR_SWR BIT(3)
  45. #define MX3_PWMCR_REPEAT GENMASK(2, 1)
  46. #define MX3_PWMCR_REPEAT_1X 0
  47. #define MX3_PWMCR_REPEAT_2X 1
  48. #define MX3_PWMCR_REPEAT_4X 2
  49. #define MX3_PWMCR_REPEAT_8X 3
  50. #define MX3_PWMCR_EN BIT(0)
  51. #define MX3_PWMSR_FWE BIT(6)
  52. #define MX3_PWMSR_CMP BIT(5)
  53. #define MX3_PWMSR_ROV BIT(4)
  54. #define MX3_PWMSR_FE BIT(3)
  55. #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
  56. #define MX3_PWMSR_FIFOAV_EMPTY 0
  57. #define MX3_PWMSR_FIFOAV_1WORD 1
  58. #define MX3_PWMSR_FIFOAV_2WORDS 2
  59. #define MX3_PWMSR_FIFOAV_3WORDS 3
  60. #define MX3_PWMSR_FIFOAV_4WORDS 4
  61. #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
  62. #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
  63. (x)) + 1)
  64. #define MX3_PWM_SWR_LOOP 5
  65. /* PWMPR register value of 0xffff has the same effect as 0xfffe */
  66. #define MX3_PWMPR_MAX 0xfffe
  67. struct pwm_imx27_chip {
  68. struct clk *clk_ipg;
  69. struct clk *clk_per;
  70. void __iomem *mmio_base;
  71. struct pwm_chip chip;
  72. /*
  73. * The driver cannot read the current duty cycle from the hardware if
  74. * the hardware is disabled. Cache the last programmed duty cycle
  75. * value to return in that case.
  76. */
  77. unsigned int duty_cycle;
  78. };
  79. #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
  80. static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
  81. {
  82. int ret;
  83. ret = clk_prepare_enable(imx->clk_ipg);
  84. if (ret)
  85. return ret;
  86. ret = clk_prepare_enable(imx->clk_per);
  87. if (ret) {
  88. clk_disable_unprepare(imx->clk_ipg);
  89. return ret;
  90. }
  91. return 0;
  92. }
  93. static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
  94. {
  95. clk_disable_unprepare(imx->clk_per);
  96. clk_disable_unprepare(imx->clk_ipg);
  97. }
  98. static int pwm_imx27_get_state(struct pwm_chip *chip,
  99. struct pwm_device *pwm, struct pwm_state *state)
  100. {
  101. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  102. u32 period, prescaler, pwm_clk, val;
  103. u64 tmp;
  104. int ret;
  105. ret = pwm_imx27_clk_prepare_enable(imx);
  106. if (ret < 0)
  107. return 0;
  108. val = readl(imx->mmio_base + MX3_PWMCR);
  109. if (val & MX3_PWMCR_EN)
  110. state->enabled = true;
  111. else
  112. state->enabled = false;
  113. switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
  114. case MX3_PWMCR_POUTC_NORMAL:
  115. state->polarity = PWM_POLARITY_NORMAL;
  116. break;
  117. case MX3_PWMCR_POUTC_INVERTED:
  118. state->polarity = PWM_POLARITY_INVERSED;
  119. break;
  120. default:
  121. dev_warn(chip->dev, "can't set polarity, output disconnected");
  122. }
  123. prescaler = MX3_PWMCR_PRESCALER_GET(val);
  124. pwm_clk = clk_get_rate(imx->clk_per);
  125. val = readl(imx->mmio_base + MX3_PWMPR);
  126. period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
  127. /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
  128. tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
  129. state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
  130. /*
  131. * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
  132. * use the cached value.
  133. */
  134. if (state->enabled)
  135. val = readl(imx->mmio_base + MX3_PWMSAR);
  136. else
  137. val = imx->duty_cycle;
  138. tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
  139. state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
  140. pwm_imx27_clk_disable_unprepare(imx);
  141. return 0;
  142. }
  143. static void pwm_imx27_sw_reset(struct pwm_chip *chip)
  144. {
  145. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  146. struct device *dev = chip->dev;
  147. int wait_count = 0;
  148. u32 cr;
  149. writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
  150. do {
  151. usleep_range(200, 1000);
  152. cr = readl(imx->mmio_base + MX3_PWMCR);
  153. } while ((cr & MX3_PWMCR_SWR) &&
  154. (wait_count++ < MX3_PWM_SWR_LOOP));
  155. if (cr & MX3_PWMCR_SWR)
  156. dev_warn(dev, "software reset timeout\n");
  157. }
  158. static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
  159. struct pwm_device *pwm)
  160. {
  161. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  162. struct device *dev = chip->dev;
  163. unsigned int period_ms;
  164. int fifoav;
  165. u32 sr;
  166. sr = readl(imx->mmio_base + MX3_PWMSR);
  167. fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
  168. if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
  169. period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
  170. NSEC_PER_MSEC);
  171. msleep(period_ms);
  172. sr = readl(imx->mmio_base + MX3_PWMSR);
  173. if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
  174. dev_warn(dev, "there is no free FIFO slot\n");
  175. }
  176. }
  177. static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  178. const struct pwm_state *state)
  179. {
  180. unsigned long period_cycles, duty_cycles, prescale;
  181. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  182. struct pwm_state cstate;
  183. unsigned long long c;
  184. unsigned long long clkrate;
  185. int ret;
  186. u32 cr;
  187. pwm_get_state(pwm, &cstate);
  188. clkrate = clk_get_rate(imx->clk_per);
  189. c = clkrate * state->period;
  190. do_div(c, NSEC_PER_SEC);
  191. period_cycles = c;
  192. prescale = period_cycles / 0x10000 + 1;
  193. period_cycles /= prescale;
  194. c = clkrate * state->duty_cycle;
  195. do_div(c, NSEC_PER_SEC);
  196. duty_cycles = c;
  197. duty_cycles /= prescale;
  198. /*
  199. * according to imx pwm RM, the real period value should be PERIOD
  200. * value in PWMPR plus 2.
  201. */
  202. if (period_cycles > 2)
  203. period_cycles -= 2;
  204. else
  205. period_cycles = 0;
  206. /*
  207. * Wait for a free FIFO slot if the PWM is already enabled, and flush
  208. * the FIFO if the PWM was disabled and is about to be enabled.
  209. */
  210. if (cstate.enabled) {
  211. pwm_imx27_wait_fifo_slot(chip, pwm);
  212. } else {
  213. ret = pwm_imx27_clk_prepare_enable(imx);
  214. if (ret)
  215. return ret;
  216. pwm_imx27_sw_reset(chip);
  217. }
  218. writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
  219. writel(period_cycles, imx->mmio_base + MX3_PWMPR);
  220. /*
  221. * Store the duty cycle for future reference in cases where the
  222. * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
  223. */
  224. imx->duty_cycle = duty_cycles;
  225. cr = MX3_PWMCR_PRESCALER_SET(prescale) |
  226. MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
  227. FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
  228. MX3_PWMCR_DBGEN;
  229. if (state->polarity == PWM_POLARITY_INVERSED)
  230. cr |= FIELD_PREP(MX3_PWMCR_POUTC,
  231. MX3_PWMCR_POUTC_INVERTED);
  232. if (state->enabled)
  233. cr |= MX3_PWMCR_EN;
  234. writel(cr, imx->mmio_base + MX3_PWMCR);
  235. if (!state->enabled)
  236. pwm_imx27_clk_disable_unprepare(imx);
  237. return 0;
  238. }
  239. static const struct pwm_ops pwm_imx27_ops = {
  240. .apply = pwm_imx27_apply,
  241. .get_state = pwm_imx27_get_state,
  242. .owner = THIS_MODULE,
  243. };
  244. static const struct of_device_id pwm_imx27_dt_ids[] = {
  245. { .compatible = "fsl,imx27-pwm", },
  246. { /* sentinel */ }
  247. };
  248. MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
  249. static int pwm_imx27_probe(struct platform_device *pdev)
  250. {
  251. struct pwm_imx27_chip *imx;
  252. int ret;
  253. u32 pwmcr;
  254. imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
  255. if (imx == NULL)
  256. return -ENOMEM;
  257. imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  258. if (IS_ERR(imx->clk_ipg))
  259. return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
  260. "getting ipg clock failed\n");
  261. imx->clk_per = devm_clk_get(&pdev->dev, "per");
  262. if (IS_ERR(imx->clk_per))
  263. return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
  264. "failed to get peripheral clock\n");
  265. imx->chip.ops = &pwm_imx27_ops;
  266. imx->chip.dev = &pdev->dev;
  267. imx->chip.npwm = 1;
  268. imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
  269. if (IS_ERR(imx->mmio_base))
  270. return PTR_ERR(imx->mmio_base);
  271. ret = pwm_imx27_clk_prepare_enable(imx);
  272. if (ret)
  273. return ret;
  274. /* keep clks on if pwm is running */
  275. pwmcr = readl(imx->mmio_base + MX3_PWMCR);
  276. if (!(pwmcr & MX3_PWMCR_EN))
  277. pwm_imx27_clk_disable_unprepare(imx);
  278. return devm_pwmchip_add(&pdev->dev, &imx->chip);
  279. }
  280. static struct platform_driver imx_pwm_driver = {
  281. .driver = {
  282. .name = "pwm-imx27",
  283. .of_match_table = pwm_imx27_dt_ids,
  284. },
  285. .probe = pwm_imx27_probe,
  286. };
  287. module_platform_driver(imx_pwm_driver);
  288. MODULE_LICENSE("GPL v2");
  289. MODULE_AUTHOR("Sascha Hauer <[email protected]>");