pwm-imx-tpm.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2018-2019 NXP.
  4. *
  5. * Limitations:
  6. * - The TPM counter and period counter are shared between
  7. * multiple channels, so all channels should use same period
  8. * settings.
  9. * - Changes to polarity cannot be latched at the time of the
  10. * next period start.
  11. * - Changing period and duty cycle together isn't atomic,
  12. * with the wrong timing it might happen that a period is
  13. * produced with old duty cycle but new period settings.
  14. */
  15. #include <linux/bitfield.h>
  16. #include <linux/bitops.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pwm.h>
  24. #include <linux/slab.h>
  25. #define PWM_IMX_TPM_PARAM 0x4
  26. #define PWM_IMX_TPM_GLOBAL 0x8
  27. #define PWM_IMX_TPM_SC 0x10
  28. #define PWM_IMX_TPM_CNT 0x14
  29. #define PWM_IMX_TPM_MOD 0x18
  30. #define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8)
  31. #define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8)
  32. #define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)
  33. #define PWM_IMX_TPM_SC_PS GENMASK(2, 0)
  34. #define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)
  35. #define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
  36. #define PWM_IMX_TPM_SC_CPWMS BIT(5)
  37. #define PWM_IMX_TPM_CnSC_CHF BIT(7)
  38. #define PWM_IMX_TPM_CnSC_MSB BIT(5)
  39. #define PWM_IMX_TPM_CnSC_MSA BIT(4)
  40. /*
  41. * The reference manual describes this field as two separate bits. The
  42. * semantic of the two bits isn't orthogonal though, so they are treated
  43. * together as a 2-bit field here.
  44. */
  45. #define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)
  46. #define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
  47. #define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
  48. #define PWM_IMX_TPM_MOD_WIDTH 16
  49. #define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
  50. struct imx_tpm_pwm_chip {
  51. struct pwm_chip chip;
  52. struct clk *clk;
  53. void __iomem *base;
  54. struct mutex lock;
  55. u32 user_count;
  56. u32 enable_count;
  57. u32 real_period;
  58. };
  59. struct imx_tpm_pwm_param {
  60. u8 prescale;
  61. u32 mod;
  62. u32 val;
  63. };
  64. static inline struct imx_tpm_pwm_chip *
  65. to_imx_tpm_pwm_chip(struct pwm_chip *chip)
  66. {
  67. return container_of(chip, struct imx_tpm_pwm_chip, chip);
  68. }
  69. /*
  70. * This function determines for a given pwm_state *state that a consumer
  71. * might request the pwm_state *real_state that eventually is implemented
  72. * by the hardware and the necessary register values (in *p) to achieve
  73. * this.
  74. */
  75. static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
  76. struct imx_tpm_pwm_param *p,
  77. struct pwm_state *real_state,
  78. const struct pwm_state *state)
  79. {
  80. struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  81. u32 rate, prescale, period_count, clock_unit;
  82. u64 tmp;
  83. rate = clk_get_rate(tpm->clk);
  84. tmp = (u64)state->period * rate;
  85. clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
  86. if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
  87. prescale = 0;
  88. else
  89. prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
  90. if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
  91. return -ERANGE;
  92. p->prescale = prescale;
  93. period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
  94. p->mod = period_count;
  95. /* calculate real period HW can support */
  96. tmp = (u64)period_count << prescale;
  97. tmp *= NSEC_PER_SEC;
  98. real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
  99. /*
  100. * if eventually the PWM output is inactive, either
  101. * duty cycle is 0 or status is disabled, need to
  102. * make sure the output pin is inactive.
  103. */
  104. if (!state->enabled)
  105. real_state->duty_cycle = 0;
  106. else
  107. real_state->duty_cycle = state->duty_cycle;
  108. tmp = (u64)p->mod * real_state->duty_cycle;
  109. p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
  110. real_state->polarity = state->polarity;
  111. real_state->enabled = state->enabled;
  112. return 0;
  113. }
  114. static int pwm_imx_tpm_get_state(struct pwm_chip *chip,
  115. struct pwm_device *pwm,
  116. struct pwm_state *state)
  117. {
  118. struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  119. u32 rate, val, prescale;
  120. u64 tmp;
  121. /* get period */
  122. state->period = tpm->real_period;
  123. /* get duty cycle */
  124. rate = clk_get_rate(tpm->clk);
  125. val = readl(tpm->base + PWM_IMX_TPM_SC);
  126. prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
  127. tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
  128. tmp = (tmp << prescale) * NSEC_PER_SEC;
  129. state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
  130. /* get polarity */
  131. val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
  132. if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
  133. state->polarity = PWM_POLARITY_INVERSED;
  134. else
  135. /*
  136. * Assume reserved values (2b00 and 2b11) to yield
  137. * normal polarity.
  138. */
  139. state->polarity = PWM_POLARITY_NORMAL;
  140. /* get channel status */
  141. state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
  142. return 0;
  143. }
  144. /* this function is supposed to be called with mutex hold */
  145. static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
  146. struct imx_tpm_pwm_param *p,
  147. struct pwm_state *state,
  148. struct pwm_device *pwm)
  149. {
  150. struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  151. bool period_update = false;
  152. bool duty_update = false;
  153. u32 val, cmod, cur_prescale;
  154. unsigned long timeout;
  155. struct pwm_state c;
  156. if (state->period != tpm->real_period) {
  157. /*
  158. * TPM counter is shared by multiple channels, so
  159. * prescale and period can NOT be modified when
  160. * there are multiple channels in use with different
  161. * period settings.
  162. */
  163. if (tpm->user_count > 1)
  164. return -EBUSY;
  165. val = readl(tpm->base + PWM_IMX_TPM_SC);
  166. cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
  167. cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
  168. if (cmod && cur_prescale != p->prescale)
  169. return -EBUSY;
  170. /* set TPM counter prescale */
  171. val &= ~PWM_IMX_TPM_SC_PS;
  172. val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
  173. writel(val, tpm->base + PWM_IMX_TPM_SC);
  174. /*
  175. * set period count:
  176. * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
  177. * is updated when MOD register is written.
  178. *
  179. * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
  180. * is latched into hardware when the next period starts.
  181. */
  182. writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
  183. tpm->real_period = state->period;
  184. period_update = true;
  185. }
  186. pwm_imx_tpm_get_state(chip, pwm, &c);
  187. /* polarity is NOT allowed to be changed if PWM is active */
  188. if (c.enabled && c.polarity != state->polarity)
  189. return -EBUSY;
  190. if (state->duty_cycle != c.duty_cycle) {
  191. /*
  192. * set channel value:
  193. * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
  194. * is updated when CnV register is written.
  195. *
  196. * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
  197. * is latched into hardware when the next period starts.
  198. */
  199. writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
  200. duty_update = true;
  201. }
  202. /* make sure MOD & CnV registers are updated */
  203. if (period_update || duty_update) {
  204. timeout = jiffies + msecs_to_jiffies(tpm->real_period /
  205. NSEC_PER_MSEC + 1);
  206. while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
  207. || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
  208. != p->val) {
  209. if (time_after(jiffies, timeout))
  210. return -ETIME;
  211. cpu_relax();
  212. }
  213. }
  214. /*
  215. * polarity settings will enabled/disable output status
  216. * immediately, so if the channel is disabled, need to
  217. * make sure MSA/MSB/ELS are set to 0 which means channel
  218. * disabled.
  219. */
  220. val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
  221. val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
  222. PWM_IMX_TPM_CnSC_MSB);
  223. if (state->enabled) {
  224. /*
  225. * set polarity (for edge-aligned PWM modes)
  226. *
  227. * ELS[1:0] = 2b10 yields normal polarity behaviour,
  228. * ELS[1:0] = 2b01 yields inversed polarity.
  229. * The other values are reserved.
  230. */
  231. val |= PWM_IMX_TPM_CnSC_MSB;
  232. val |= (state->polarity == PWM_POLARITY_NORMAL) ?
  233. PWM_IMX_TPM_CnSC_ELS_NORMAL :
  234. PWM_IMX_TPM_CnSC_ELS_INVERSED;
  235. }
  236. writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
  237. /* control the counter status */
  238. if (state->enabled != c.enabled) {
  239. val = readl(tpm->base + PWM_IMX_TPM_SC);
  240. if (state->enabled) {
  241. if (++tpm->enable_count == 1)
  242. val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
  243. } else {
  244. if (--tpm->enable_count == 0)
  245. val &= ~PWM_IMX_TPM_SC_CMOD;
  246. }
  247. writel(val, tpm->base + PWM_IMX_TPM_SC);
  248. }
  249. return 0;
  250. }
  251. static int pwm_imx_tpm_apply(struct pwm_chip *chip,
  252. struct pwm_device *pwm,
  253. const struct pwm_state *state)
  254. {
  255. struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  256. struct imx_tpm_pwm_param param;
  257. struct pwm_state real_state;
  258. int ret;
  259. ret = pwm_imx_tpm_round_state(chip, &param, &real_state, state);
  260. if (ret)
  261. return ret;
  262. mutex_lock(&tpm->lock);
  263. ret = pwm_imx_tpm_apply_hw(chip, &param, &real_state, pwm);
  264. mutex_unlock(&tpm->lock);
  265. return ret;
  266. }
  267. static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  268. {
  269. struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  270. mutex_lock(&tpm->lock);
  271. tpm->user_count++;
  272. mutex_unlock(&tpm->lock);
  273. return 0;
  274. }
  275. static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  276. {
  277. struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  278. mutex_lock(&tpm->lock);
  279. tpm->user_count--;
  280. mutex_unlock(&tpm->lock);
  281. }
  282. static const struct pwm_ops imx_tpm_pwm_ops = {
  283. .request = pwm_imx_tpm_request,
  284. .free = pwm_imx_tpm_free,
  285. .get_state = pwm_imx_tpm_get_state,
  286. .apply = pwm_imx_tpm_apply,
  287. .owner = THIS_MODULE,
  288. };
  289. static int pwm_imx_tpm_probe(struct platform_device *pdev)
  290. {
  291. struct imx_tpm_pwm_chip *tpm;
  292. int ret;
  293. u32 val;
  294. tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL);
  295. if (!tpm)
  296. return -ENOMEM;
  297. platform_set_drvdata(pdev, tpm);
  298. tpm->base = devm_platform_ioremap_resource(pdev, 0);
  299. if (IS_ERR(tpm->base))
  300. return PTR_ERR(tpm->base);
  301. tpm->clk = devm_clk_get(&pdev->dev, NULL);
  302. if (IS_ERR(tpm->clk))
  303. return dev_err_probe(&pdev->dev, PTR_ERR(tpm->clk),
  304. "failed to get PWM clock\n");
  305. ret = clk_prepare_enable(tpm->clk);
  306. if (ret) {
  307. dev_err(&pdev->dev,
  308. "failed to prepare or enable clock: %d\n", ret);
  309. return ret;
  310. }
  311. tpm->chip.dev = &pdev->dev;
  312. tpm->chip.ops = &imx_tpm_pwm_ops;
  313. /* get number of channels */
  314. val = readl(tpm->base + PWM_IMX_TPM_PARAM);
  315. tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
  316. mutex_init(&tpm->lock);
  317. ret = pwmchip_add(&tpm->chip);
  318. if (ret) {
  319. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  320. clk_disable_unprepare(tpm->clk);
  321. }
  322. return ret;
  323. }
  324. static int pwm_imx_tpm_remove(struct platform_device *pdev)
  325. {
  326. struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev);
  327. pwmchip_remove(&tpm->chip);
  328. clk_disable_unprepare(tpm->clk);
  329. return 0;
  330. }
  331. static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev)
  332. {
  333. struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
  334. if (tpm->enable_count > 0)
  335. return -EBUSY;
  336. /*
  337. * Force 'real_period' to be zero to force period update code
  338. * can be executed after system resume back, since suspend causes
  339. * the period related registers to become their reset values.
  340. */
  341. tpm->real_period = 0;
  342. clk_disable_unprepare(tpm->clk);
  343. return 0;
  344. }
  345. static int __maybe_unused pwm_imx_tpm_resume(struct device *dev)
  346. {
  347. struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
  348. int ret = 0;
  349. ret = clk_prepare_enable(tpm->clk);
  350. if (ret)
  351. dev_err(dev, "failed to prepare or enable clock: %d\n", ret);
  352. return ret;
  353. }
  354. static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
  355. pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
  356. static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
  357. { .compatible = "fsl,imx7ulp-pwm", },
  358. { /* sentinel */ }
  359. };
  360. MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
  361. static struct platform_driver imx_tpm_pwm_driver = {
  362. .driver = {
  363. .name = "imx7ulp-tpm-pwm",
  364. .of_match_table = imx_tpm_pwm_dt_ids,
  365. .pm = &imx_tpm_pwm_pm,
  366. },
  367. .probe = pwm_imx_tpm_probe,
  368. .remove = pwm_imx_tpm_remove,
  369. };
  370. module_platform_driver(imx_tpm_pwm_driver);
  371. MODULE_AUTHOR("Anson Huang <[email protected]>");
  372. MODULE_DESCRIPTION("i.MX TPM PWM Driver");
  373. MODULE_LICENSE("GPL v2");