pwm-bcm2835.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2014 Bart Tanghe <[email protected]>
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/err.h>
  7. #include <linux/io.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pwm.h>
  12. #define PWM_CONTROL 0x000
  13. #define PWM_CONTROL_SHIFT(x) ((x) * 8)
  14. #define PWM_CONTROL_MASK 0xff
  15. #define PWM_MODE 0x80 /* set timer in PWM mode */
  16. #define PWM_ENABLE (1 << 0)
  17. #define PWM_POLARITY (1 << 4)
  18. #define PERIOD(x) (((x) * 0x10) + 0x10)
  19. #define DUTY(x) (((x) * 0x10) + 0x14)
  20. #define PERIOD_MIN 0x2
  21. struct bcm2835_pwm {
  22. struct pwm_chip chip;
  23. struct device *dev;
  24. void __iomem *base;
  25. struct clk *clk;
  26. };
  27. static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
  28. {
  29. return container_of(chip, struct bcm2835_pwm, chip);
  30. }
  31. static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  32. {
  33. struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  34. u32 value;
  35. value = readl(pc->base + PWM_CONTROL);
  36. value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
  37. value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
  38. writel(value, pc->base + PWM_CONTROL);
  39. return 0;
  40. }
  41. static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  42. {
  43. struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  44. u32 value;
  45. value = readl(pc->base + PWM_CONTROL);
  46. value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
  47. writel(value, pc->base + PWM_CONTROL);
  48. }
  49. static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  50. const struct pwm_state *state)
  51. {
  52. struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  53. unsigned long rate = clk_get_rate(pc->clk);
  54. unsigned long long period_cycles;
  55. u64 max_period;
  56. u32 val;
  57. if (!rate) {
  58. dev_err(pc->dev, "failed to get clock rate\n");
  59. return -EINVAL;
  60. }
  61. /*
  62. * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
  63. * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
  64. * multiplication period * rate doesn't overflow.
  65. * To calculate the maximal possible period that guarantees the
  66. * above inequality:
  67. *
  68. * round(period * rate / NSEC_PER_SEC) <= U32_MAX
  69. * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
  70. * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
  71. * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
  72. * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
  73. * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
  74. */
  75. max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, rate) - 1;
  76. if (state->period > max_period)
  77. return -EINVAL;
  78. /* set period */
  79. period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * rate, NSEC_PER_SEC);
  80. /* don't accept a period that is too small */
  81. if (period_cycles < PERIOD_MIN)
  82. return -EINVAL;
  83. writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
  84. /* set duty cycle */
  85. val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * rate, NSEC_PER_SEC);
  86. writel(val, pc->base + DUTY(pwm->hwpwm));
  87. /* set polarity */
  88. val = readl(pc->base + PWM_CONTROL);
  89. if (state->polarity == PWM_POLARITY_NORMAL)
  90. val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
  91. else
  92. val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
  93. /* enable/disable */
  94. if (state->enabled)
  95. val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
  96. else
  97. val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
  98. writel(val, pc->base + PWM_CONTROL);
  99. return 0;
  100. }
  101. static const struct pwm_ops bcm2835_pwm_ops = {
  102. .request = bcm2835_pwm_request,
  103. .free = bcm2835_pwm_free,
  104. .apply = bcm2835_pwm_apply,
  105. .owner = THIS_MODULE,
  106. };
  107. static int bcm2835_pwm_probe(struct platform_device *pdev)
  108. {
  109. struct bcm2835_pwm *pc;
  110. int ret;
  111. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  112. if (!pc)
  113. return -ENOMEM;
  114. pc->dev = &pdev->dev;
  115. pc->base = devm_platform_ioremap_resource(pdev, 0);
  116. if (IS_ERR(pc->base))
  117. return PTR_ERR(pc->base);
  118. pc->clk = devm_clk_get(&pdev->dev, NULL);
  119. if (IS_ERR(pc->clk))
  120. return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
  121. "clock not found\n");
  122. ret = clk_prepare_enable(pc->clk);
  123. if (ret)
  124. return ret;
  125. pc->chip.dev = &pdev->dev;
  126. pc->chip.ops = &bcm2835_pwm_ops;
  127. pc->chip.npwm = 2;
  128. platform_set_drvdata(pdev, pc);
  129. ret = pwmchip_add(&pc->chip);
  130. if (ret < 0)
  131. goto add_fail;
  132. return 0;
  133. add_fail:
  134. clk_disable_unprepare(pc->clk);
  135. return ret;
  136. }
  137. static int bcm2835_pwm_remove(struct platform_device *pdev)
  138. {
  139. struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
  140. pwmchip_remove(&pc->chip);
  141. clk_disable_unprepare(pc->clk);
  142. return 0;
  143. }
  144. static const struct of_device_id bcm2835_pwm_of_match[] = {
  145. { .compatible = "brcm,bcm2835-pwm", },
  146. { /* sentinel */ }
  147. };
  148. MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
  149. static struct platform_driver bcm2835_pwm_driver = {
  150. .driver = {
  151. .name = "bcm2835-pwm",
  152. .of_match_table = bcm2835_pwm_of_match,
  153. },
  154. .probe = bcm2835_pwm_probe,
  155. .remove = bcm2835_pwm_remove,
  156. };
  157. module_platform_driver(bcm2835_pwm_driver);
  158. MODULE_AUTHOR("Bart Tanghe <[email protected]>");
  159. MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
  160. MODULE_LICENSE("GPL v2");