sparx5_serdes.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+
  2. * Microchip Sparx5 SerDes driver
  3. *
  4. * Copyright (c) 2020 Microchip Technology Inc.
  5. */
  6. #ifndef _SPARX5_SERDES_H_
  7. #define _SPARX5_SERDES_H_
  8. #include "sparx5_serdes_regs.h"
  9. #define SPX5_SERDES_MAX 33
  10. enum sparx5_serdes_type {
  11. SPX5_SDT_6G = 6,
  12. SPX5_SDT_10G = 10,
  13. SPX5_SDT_25G = 25,
  14. };
  15. enum sparx5_serdes_mode {
  16. SPX5_SD_MODE_NONE,
  17. SPX5_SD_MODE_2G5,
  18. SPX5_SD_MODE_QSGMII,
  19. SPX5_SD_MODE_100FX,
  20. SPX5_SD_MODE_1000BASEX,
  21. SPX5_SD_MODE_SFI,
  22. };
  23. struct sparx5_serdes_private {
  24. struct device *dev;
  25. void __iomem *regs[NUM_TARGETS];
  26. struct phy *phys[SPX5_SERDES_MAX];
  27. bool cmu_enabled;
  28. unsigned long coreclock;
  29. };
  30. struct sparx5_serdes_macro {
  31. struct sparx5_serdes_private *priv;
  32. u32 sidx;
  33. u32 stpidx;
  34. enum sparx5_serdes_type serdestype;
  35. enum sparx5_serdes_mode serdesmode;
  36. phy_interface_t portmode;
  37. int speed;
  38. enum phy_media media;
  39. };
  40. /* Read, Write and modify registers content.
  41. * The register definition macros start at the id
  42. */
  43. static inline void __iomem *sdx5_addr(void __iomem *base[],
  44. int id, int tinst, int tcnt,
  45. int gbase, int ginst,
  46. int gcnt, int gwidth,
  47. int raddr, int rinst,
  48. int rcnt, int rwidth)
  49. {
  50. WARN_ON((tinst) >= tcnt);
  51. WARN_ON((ginst) >= gcnt);
  52. WARN_ON((rinst) >= rcnt);
  53. return base[id + (tinst)] +
  54. gbase + ((ginst) * gwidth) +
  55. raddr + ((rinst) * rwidth);
  56. }
  57. static inline void __iomem *sdx5_inst_baseaddr(void __iomem *base,
  58. int gbase, int ginst,
  59. int gcnt, int gwidth,
  60. int raddr, int rinst,
  61. int rcnt, int rwidth)
  62. {
  63. WARN_ON((ginst) >= gcnt);
  64. WARN_ON((rinst) >= rcnt);
  65. return base +
  66. gbase + ((ginst) * gwidth) +
  67. raddr + ((rinst) * rwidth);
  68. }
  69. static inline void sdx5_rmw(u32 val, u32 mask, struct sparx5_serdes_private *priv,
  70. int id, int tinst, int tcnt,
  71. int gbase, int ginst, int gcnt, int gwidth,
  72. int raddr, int rinst, int rcnt, int rwidth)
  73. {
  74. u32 nval;
  75. void __iomem *addr =
  76. sdx5_addr(priv->regs, id, tinst, tcnt,
  77. gbase, ginst, gcnt, gwidth,
  78. raddr, rinst, rcnt, rwidth);
  79. nval = readl(addr);
  80. nval = (nval & ~mask) | (val & mask);
  81. writel(nval, addr);
  82. }
  83. static inline void sdx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
  84. int id, int tinst, int tcnt,
  85. int gbase, int ginst, int gcnt, int gwidth,
  86. int raddr, int rinst, int rcnt, int rwidth)
  87. {
  88. u32 nval;
  89. void __iomem *addr =
  90. sdx5_inst_baseaddr(iomem,
  91. gbase, ginst, gcnt, gwidth,
  92. raddr, rinst, rcnt, rwidth);
  93. nval = readl(addr);
  94. nval = (nval & ~mask) | (val & mask);
  95. writel(nval, addr);
  96. }
  97. static inline void sdx5_rmw_addr(u32 val, u32 mask, void __iomem *addr)
  98. {
  99. u32 nval;
  100. nval = readl(addr);
  101. nval = (nval & ~mask) | (val & mask);
  102. writel(nval, addr);
  103. }
  104. static inline void __iomem *sdx5_inst_get(struct sparx5_serdes_private *priv,
  105. int id, int tinst)
  106. {
  107. return priv->regs[id + tinst];
  108. }
  109. static inline void __iomem *sdx5_inst_addr(void __iomem *iomem,
  110. int id, int tinst, int tcnt,
  111. int gbase,
  112. int ginst, int gcnt, int gwidth,
  113. int raddr,
  114. int rinst, int rcnt, int rwidth)
  115. {
  116. return sdx5_inst_baseaddr(iomem, gbase, ginst, gcnt, gwidth,
  117. raddr, rinst, rcnt, rwidth);
  118. }
  119. #endif /* _SPARX5_SERDES_REGS_H_ */