sparx5_serdes.c 76 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Microchip Sparx5 Switch SerDes driver
  3. *
  4. * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
  5. *
  6. * The Sparx5 Chip Register Model can be browsed at this location:
  7. * https://github.com/microchip-ung/sparx-5_reginfo
  8. * and the datasheet is available here:
  9. * https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf
  10. */
  11. #include <linux/printk.h>
  12. #include <linux/module.h>
  13. #include <linux/device.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of.h>
  17. #include <linux/io.h>
  18. #include <linux/clk.h>
  19. #include <linux/phy.h>
  20. #include <linux/phy/phy.h>
  21. #include "sparx5_serdes.h"
  22. #define SPX5_CMU_MAX 14
  23. #define SPX5_SERDES_10G_START 13
  24. #define SPX5_SERDES_25G_START 25
  25. enum sparx5_10g28cmu_mode {
  26. SPX5_SD10G28_CMU_MAIN = 0,
  27. SPX5_SD10G28_CMU_AUX1 = 1,
  28. SPX5_SD10G28_CMU_AUX2 = 3,
  29. SPX5_SD10G28_CMU_NONE = 4,
  30. };
  31. enum sparx5_sd25g28_mode_preset_type {
  32. SPX5_SD25G28_MODE_PRESET_25000,
  33. SPX5_SD25G28_MODE_PRESET_10000,
  34. SPX5_SD25G28_MODE_PRESET_5000,
  35. SPX5_SD25G28_MODE_PRESET_SD_2G5,
  36. SPX5_SD25G28_MODE_PRESET_1000BASEX,
  37. };
  38. enum sparx5_sd10g28_mode_preset_type {
  39. SPX5_SD10G28_MODE_PRESET_10000,
  40. SPX5_SD10G28_MODE_PRESET_SFI_5000_6G,
  41. SPX5_SD10G28_MODE_PRESET_SFI_5000_10G,
  42. SPX5_SD10G28_MODE_PRESET_QSGMII,
  43. SPX5_SD10G28_MODE_PRESET_SD_2G5,
  44. SPX5_SD10G28_MODE_PRESET_1000BASEX,
  45. };
  46. struct sparx5_serdes_io_resource {
  47. enum sparx5_serdes_target id;
  48. phys_addr_t offset;
  49. };
  50. struct sparx5_sd25g28_mode_preset {
  51. u8 bitwidth;
  52. u8 tx_pre_div;
  53. u8 fifo_ck_div;
  54. u8 pre_divsel;
  55. u8 vco_div_mode;
  56. u8 sel_div;
  57. u8 ck_bitwidth;
  58. u8 subrate;
  59. u8 com_txcal_en;
  60. u8 com_tx_reserve_msb;
  61. u8 com_tx_reserve_lsb;
  62. u8 cfg_itx_ipcml_base;
  63. u8 tx_reserve_lsb;
  64. u8 tx_reserve_msb;
  65. u8 bw;
  66. u8 rxterm;
  67. u8 dfe_tap;
  68. u8 dfe_enable;
  69. bool txmargin;
  70. u8 cfg_ctle_rstn;
  71. u8 r_dfe_rstn;
  72. u8 cfg_pi_bw_3_0;
  73. u8 tx_tap_dly;
  74. u8 tx_tap_adv;
  75. };
  76. struct sparx5_sd25g28_media_preset {
  77. u8 cfg_eq_c_force_3_0;
  78. u8 cfg_vga_ctrl_byp_4_0;
  79. u8 cfg_eq_r_force_3_0;
  80. u8 cfg_en_adv;
  81. u8 cfg_en_main;
  82. u8 cfg_en_dly;
  83. u8 cfg_tap_adv_3_0;
  84. u8 cfg_tap_main;
  85. u8 cfg_tap_dly_4_0;
  86. u8 cfg_alos_thr_2_0;
  87. };
  88. struct sparx5_sd25g28_args {
  89. u8 if_width; /* UDL if-width: 10/16/20/32/64 */
  90. bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
  91. enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
  92. bool no_pwrcycle:1; /* Omit initial power-cycle */
  93. bool txinvert:1; /* Enable inversion of output data */
  94. bool rxinvert:1; /* Enable inversion of input data */
  95. u16 txswing; /* Set output level */
  96. u8 rate; /* Rate of network interface */
  97. u8 pi_bw_gen1;
  98. u8 duty_cycle; /* Set output level to half/full */
  99. bool mute:1; /* Mute Output Buffer */
  100. bool reg_rst:1;
  101. u8 com_pll_reserve;
  102. };
  103. struct sparx5_sd25g28_params {
  104. u8 reg_rst;
  105. u8 cfg_jc_byp;
  106. u8 cfg_common_reserve_7_0;
  107. u8 r_reg_manual;
  108. u8 r_d_width_ctrl_from_hwt;
  109. u8 r_d_width_ctrl_2_0;
  110. u8 r_txfifo_ck_div_pmad_2_0;
  111. u8 r_rxfifo_ck_div_pmad_2_0;
  112. u8 cfg_pll_lol_set;
  113. u8 cfg_vco_div_mode_1_0;
  114. u8 cfg_pre_divsel_1_0;
  115. u8 cfg_sel_div_3_0;
  116. u8 cfg_vco_start_code_3_0;
  117. u8 cfg_pma_tx_ck_bitwidth_2_0;
  118. u8 cfg_tx_prediv_1_0;
  119. u8 cfg_rxdiv_sel_2_0;
  120. u8 cfg_tx_subrate_2_0;
  121. u8 cfg_rx_subrate_2_0;
  122. u8 r_multi_lane_mode;
  123. u8 cfg_cdrck_en;
  124. u8 cfg_dfeck_en;
  125. u8 cfg_dfe_pd;
  126. u8 cfg_dfedmx_pd;
  127. u8 cfg_dfetap_en_5_1;
  128. u8 cfg_dmux_pd;
  129. u8 cfg_dmux_clk_pd;
  130. u8 cfg_erramp_pd;
  131. u8 cfg_pi_dfe_en;
  132. u8 cfg_pi_en;
  133. u8 cfg_pd_ctle;
  134. u8 cfg_summer_en;
  135. u8 cfg_pmad_ck_pd;
  136. u8 cfg_pd_clk;
  137. u8 cfg_pd_cml;
  138. u8 cfg_pd_driver;
  139. u8 cfg_rx_reg_pu;
  140. u8 cfg_pd_rms_det;
  141. u8 cfg_dcdr_pd;
  142. u8 cfg_ecdr_pd;
  143. u8 cfg_pd_sq;
  144. u8 cfg_itx_ipdriver_base_2_0;
  145. u8 cfg_tap_dly_4_0;
  146. u8 cfg_tap_main;
  147. u8 cfg_en_main;
  148. u8 cfg_tap_adv_3_0;
  149. u8 cfg_en_adv;
  150. u8 cfg_en_dly;
  151. u8 cfg_iscan_en;
  152. u8 l1_pcs_en_fast_iscan;
  153. u8 l0_cfg_bw_1_0;
  154. u8 l0_cfg_txcal_en;
  155. u8 cfg_en_dummy;
  156. u8 cfg_pll_reserve_3_0;
  157. u8 l0_cfg_tx_reserve_15_8;
  158. u8 l0_cfg_tx_reserve_7_0;
  159. u8 cfg_tx_reserve_15_8;
  160. u8 cfg_tx_reserve_7_0;
  161. u8 cfg_bw_1_0;
  162. u8 cfg_txcal_man_en;
  163. u8 cfg_phase_man_4_0;
  164. u8 cfg_quad_man_1_0;
  165. u8 cfg_txcal_shift_code_5_0;
  166. u8 cfg_txcal_valid_sel_3_0;
  167. u8 cfg_txcal_en;
  168. u8 cfg_cdr_kf_2_0;
  169. u8 cfg_cdr_m_7_0;
  170. u8 cfg_pi_bw_3_0;
  171. u8 cfg_pi_steps_1_0;
  172. u8 cfg_dis_2ndorder;
  173. u8 cfg_ctle_rstn;
  174. u8 r_dfe_rstn;
  175. u8 cfg_alos_thr_2_0;
  176. u8 cfg_itx_ipcml_base_1_0;
  177. u8 cfg_rx_reserve_7_0;
  178. u8 cfg_rx_reserve_15_8;
  179. u8 cfg_rxterm_2_0;
  180. u8 cfg_fom_selm;
  181. u8 cfg_rx_sp_ctle_1_0;
  182. u8 cfg_isel_ctle_1_0;
  183. u8 cfg_vga_ctrl_byp_4_0;
  184. u8 cfg_vga_byp;
  185. u8 cfg_agc_adpt_byp;
  186. u8 cfg_eqr_byp;
  187. u8 cfg_eqr_force_3_0;
  188. u8 cfg_eqc_force_3_0;
  189. u8 cfg_sum_setcm_en;
  190. u8 cfg_init_pos_iscan_6_0;
  191. u8 cfg_init_pos_ipi_6_0;
  192. u8 cfg_dfedig_m_2_0;
  193. u8 cfg_en_dfedig;
  194. u8 cfg_pi_DFE_en;
  195. u8 cfg_tx2rx_lp_en;
  196. u8 cfg_txlb_en;
  197. u8 cfg_rx2tx_lp_en;
  198. u8 cfg_rxlb_en;
  199. u8 r_tx_pol_inv;
  200. u8 r_rx_pol_inv;
  201. };
  202. struct sparx5_sd10g28_media_preset {
  203. u8 cfg_en_adv;
  204. u8 cfg_en_main;
  205. u8 cfg_en_dly;
  206. u8 cfg_tap_adv_3_0;
  207. u8 cfg_tap_main;
  208. u8 cfg_tap_dly_4_0;
  209. u8 cfg_vga_ctrl_3_0;
  210. u8 cfg_vga_cp_2_0;
  211. u8 cfg_eq_res_3_0;
  212. u8 cfg_eq_r_byp;
  213. u8 cfg_eq_c_force_3_0;
  214. u8 cfg_alos_thr_3_0;
  215. };
  216. struct sparx5_sd10g28_mode_preset {
  217. u8 bwidth; /* interface width: 10/16/20/32/64 */
  218. enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
  219. u8 rate; /* Rate of network interface */
  220. u8 dfe_tap;
  221. u8 dfe_enable;
  222. u8 pi_bw_gen1;
  223. u8 duty_cycle; /* Set output level to half/full */
  224. };
  225. struct sparx5_sd10g28_args {
  226. bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
  227. bool no_pwrcycle:1; /* Omit initial power-cycle */
  228. bool txinvert:1; /* Enable inversion of output data */
  229. bool rxinvert:1; /* Enable inversion of input data */
  230. bool txmargin:1; /* Set output level to half/full */
  231. u16 txswing; /* Set output level */
  232. bool mute:1; /* Mute Output Buffer */
  233. bool is_6g:1;
  234. bool reg_rst:1;
  235. };
  236. struct sparx5_sd10g28_params {
  237. u8 cmu_sel;
  238. u8 is_6g;
  239. u8 skip_cmu_cfg;
  240. u8 cfg_lane_reserve_7_0;
  241. u8 cfg_ssc_rtl_clk_sel;
  242. u8 cfg_lane_reserve_15_8;
  243. u8 cfg_txrate_1_0;
  244. u8 cfg_rxrate_1_0;
  245. u8 r_d_width_ctrl_2_0;
  246. u8 cfg_pma_tx_ck_bitwidth_2_0;
  247. u8 cfg_rxdiv_sel_2_0;
  248. u8 r_pcs2pma_phymode_4_0;
  249. u8 cfg_lane_id_2_0;
  250. u8 cfg_cdrck_en;
  251. u8 cfg_dfeck_en;
  252. u8 cfg_dfe_pd;
  253. u8 cfg_dfetap_en_5_1;
  254. u8 cfg_erramp_pd;
  255. u8 cfg_pi_DFE_en;
  256. u8 cfg_pi_en;
  257. u8 cfg_pd_ctle;
  258. u8 cfg_summer_en;
  259. u8 cfg_pd_rx_cktree;
  260. u8 cfg_pd_clk;
  261. u8 cfg_pd_cml;
  262. u8 cfg_pd_driver;
  263. u8 cfg_rx_reg_pu;
  264. u8 cfg_d_cdr_pd;
  265. u8 cfg_pd_sq;
  266. u8 cfg_rxdet_en;
  267. u8 cfg_rxdet_str;
  268. u8 r_multi_lane_mode;
  269. u8 cfg_en_adv;
  270. u8 cfg_en_main;
  271. u8 cfg_en_dly;
  272. u8 cfg_tap_adv_3_0;
  273. u8 cfg_tap_main;
  274. u8 cfg_tap_dly_4_0;
  275. u8 cfg_vga_ctrl_3_0;
  276. u8 cfg_vga_cp_2_0;
  277. u8 cfg_eq_res_3_0;
  278. u8 cfg_eq_r_byp;
  279. u8 cfg_eq_c_force_3_0;
  280. u8 cfg_en_dfedig;
  281. u8 cfg_sum_setcm_en;
  282. u8 cfg_en_preemph;
  283. u8 cfg_itx_ippreemp_base_1_0;
  284. u8 cfg_itx_ipdriver_base_2_0;
  285. u8 cfg_ibias_tune_reserve_5_0;
  286. u8 cfg_txswing_half;
  287. u8 cfg_dis_2nd_order;
  288. u8 cfg_rx_ssc_lh;
  289. u8 cfg_pi_floop_steps_1_0;
  290. u8 cfg_pi_ext_dac_23_16;
  291. u8 cfg_pi_ext_dac_15_8;
  292. u8 cfg_iscan_ext_dac_7_0;
  293. u8 cfg_cdr_kf_gen1_2_0;
  294. u8 cfg_cdr_kf_gen2_2_0;
  295. u8 cfg_cdr_kf_gen3_2_0;
  296. u8 cfg_cdr_kf_gen4_2_0;
  297. u8 r_cdr_m_gen1_7_0;
  298. u8 cfg_pi_bw_gen1_3_0;
  299. u8 cfg_pi_bw_gen2;
  300. u8 cfg_pi_bw_gen3;
  301. u8 cfg_pi_bw_gen4;
  302. u8 cfg_pi_ext_dac_7_0;
  303. u8 cfg_pi_steps;
  304. u8 cfg_mp_max_3_0;
  305. u8 cfg_rstn_dfedig;
  306. u8 cfg_alos_thr_3_0;
  307. u8 cfg_predrv_slewrate_1_0;
  308. u8 cfg_itx_ipcml_base_1_0;
  309. u8 cfg_ip_pre_base_1_0;
  310. u8 r_cdr_m_gen2_7_0;
  311. u8 r_cdr_m_gen3_7_0;
  312. u8 r_cdr_m_gen4_7_0;
  313. u8 r_en_auto_cdr_rstn;
  314. u8 cfg_oscal_afe;
  315. u8 cfg_pd_osdac_afe;
  316. u8 cfg_resetb_oscal_afe[2];
  317. u8 cfg_center_spreading;
  318. u8 cfg_m_cnt_maxval_4_0;
  319. u8 cfg_ncnt_maxval_7_0;
  320. u8 cfg_ncnt_maxval_10_8;
  321. u8 cfg_ssc_en;
  322. u8 cfg_tx2rx_lp_en;
  323. u8 cfg_txlb_en;
  324. u8 cfg_rx2tx_lp_en;
  325. u8 cfg_rxlb_en;
  326. u8 r_tx_pol_inv;
  327. u8 r_rx_pol_inv;
  328. u8 fx_100;
  329. };
  330. static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
  331. { /* ETH_MEDIA_DEFAULT */
  332. .cfg_en_adv = 0,
  333. .cfg_en_main = 1,
  334. .cfg_en_dly = 0,
  335. .cfg_tap_adv_3_0 = 0,
  336. .cfg_tap_main = 1,
  337. .cfg_tap_dly_4_0 = 0,
  338. .cfg_eq_c_force_3_0 = 0xf,
  339. .cfg_vga_ctrl_byp_4_0 = 4,
  340. .cfg_eq_r_force_3_0 = 12,
  341. .cfg_alos_thr_2_0 = 7,
  342. },
  343. { /* ETH_MEDIA_SR */
  344. .cfg_en_adv = 1,
  345. .cfg_en_main = 1,
  346. .cfg_en_dly = 1,
  347. .cfg_tap_adv_3_0 = 0,
  348. .cfg_tap_main = 1,
  349. .cfg_tap_dly_4_0 = 0x10,
  350. .cfg_eq_c_force_3_0 = 0xf,
  351. .cfg_vga_ctrl_byp_4_0 = 8,
  352. .cfg_eq_r_force_3_0 = 4,
  353. .cfg_alos_thr_2_0 = 0,
  354. },
  355. { /* ETH_MEDIA_DAC */
  356. .cfg_en_adv = 0,
  357. .cfg_en_main = 1,
  358. .cfg_en_dly = 0,
  359. .cfg_tap_adv_3_0 = 0,
  360. .cfg_tap_main = 1,
  361. .cfg_tap_dly_4_0 = 0,
  362. .cfg_eq_c_force_3_0 = 0xf,
  363. .cfg_vga_ctrl_byp_4_0 = 8,
  364. .cfg_eq_r_force_3_0 = 0xc,
  365. .cfg_alos_thr_2_0 = 0,
  366. },
  367. };
  368. static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = {
  369. { /* SPX5_SD25G28_MODE_PRESET_25000 */
  370. .bitwidth = 40,
  371. .tx_pre_div = 0,
  372. .fifo_ck_div = 0,
  373. .pre_divsel = 1,
  374. .vco_div_mode = 0,
  375. .sel_div = 15,
  376. .ck_bitwidth = 3,
  377. .subrate = 0,
  378. .com_txcal_en = 0,
  379. .com_tx_reserve_msb = (0x26 << 1),
  380. .com_tx_reserve_lsb = 0xf0,
  381. .cfg_itx_ipcml_base = 0,
  382. .tx_reserve_msb = 0xcc,
  383. .tx_reserve_lsb = 0xfe,
  384. .bw = 3,
  385. .rxterm = 0,
  386. .dfe_enable = 1,
  387. .dfe_tap = 0x1f,
  388. .txmargin = 1,
  389. .cfg_ctle_rstn = 1,
  390. .r_dfe_rstn = 1,
  391. .cfg_pi_bw_3_0 = 0,
  392. .tx_tap_dly = 8,
  393. .tx_tap_adv = 0xc,
  394. },
  395. { /* SPX5_SD25G28_MODE_PRESET_10000 */
  396. .bitwidth = 64,
  397. .tx_pre_div = 0,
  398. .fifo_ck_div = 2,
  399. .pre_divsel = 0,
  400. .vco_div_mode = 1,
  401. .sel_div = 9,
  402. .ck_bitwidth = 0,
  403. .subrate = 0,
  404. .com_txcal_en = 1,
  405. .com_tx_reserve_msb = (0x20 << 1),
  406. .com_tx_reserve_lsb = 0x40,
  407. .cfg_itx_ipcml_base = 0,
  408. .tx_reserve_msb = 0x4c,
  409. .tx_reserve_lsb = 0x44,
  410. .bw = 3,
  411. .cfg_pi_bw_3_0 = 0,
  412. .rxterm = 3,
  413. .dfe_enable = 1,
  414. .dfe_tap = 0x1f,
  415. .txmargin = 0,
  416. .cfg_ctle_rstn = 1,
  417. .r_dfe_rstn = 1,
  418. .tx_tap_dly = 0,
  419. .tx_tap_adv = 0,
  420. },
  421. { /* SPX5_SD25G28_MODE_PRESET_5000 */
  422. .bitwidth = 64,
  423. .tx_pre_div = 0,
  424. .fifo_ck_div = 2,
  425. .pre_divsel = 0,
  426. .vco_div_mode = 2,
  427. .sel_div = 9,
  428. .ck_bitwidth = 0,
  429. .subrate = 0,
  430. .com_txcal_en = 1,
  431. .com_tx_reserve_msb = (0x20 << 1),
  432. .com_tx_reserve_lsb = 0,
  433. .cfg_itx_ipcml_base = 0,
  434. .tx_reserve_msb = 0xe,
  435. .tx_reserve_lsb = 0x80,
  436. .bw = 0,
  437. .rxterm = 0,
  438. .cfg_pi_bw_3_0 = 6,
  439. .dfe_enable = 0,
  440. .dfe_tap = 0,
  441. .tx_tap_dly = 0,
  442. .tx_tap_adv = 0,
  443. },
  444. { /* SPX5_SD25G28_MODE_PRESET_SD_2G5 */
  445. .bitwidth = 10,
  446. .tx_pre_div = 0,
  447. .fifo_ck_div = 0,
  448. .pre_divsel = 0,
  449. .vco_div_mode = 1,
  450. .sel_div = 6,
  451. .ck_bitwidth = 3,
  452. .subrate = 2,
  453. .com_txcal_en = 1,
  454. .com_tx_reserve_msb = (0x26 << 1),
  455. .com_tx_reserve_lsb = (0xf << 4),
  456. .cfg_itx_ipcml_base = 2,
  457. .tx_reserve_msb = 0x8,
  458. .tx_reserve_lsb = 0x8a,
  459. .bw = 0,
  460. .cfg_pi_bw_3_0 = 0,
  461. .rxterm = (1 << 2),
  462. .dfe_enable = 0,
  463. .dfe_tap = 0,
  464. .tx_tap_dly = 0,
  465. .tx_tap_adv = 0,
  466. },
  467. { /* SPX5_SD25G28_MODE_PRESET_1000BASEX */
  468. .bitwidth = 10,
  469. .tx_pre_div = 0,
  470. .fifo_ck_div = 1,
  471. .pre_divsel = 0,
  472. .vco_div_mode = 1,
  473. .sel_div = 8,
  474. .ck_bitwidth = 3,
  475. .subrate = 3,
  476. .com_txcal_en = 1,
  477. .com_tx_reserve_msb = (0x26 << 1),
  478. .com_tx_reserve_lsb = 0xf0,
  479. .cfg_itx_ipcml_base = 0,
  480. .tx_reserve_msb = 0x8,
  481. .tx_reserve_lsb = 0xce,
  482. .bw = 0,
  483. .rxterm = 0,
  484. .cfg_pi_bw_3_0 = 0,
  485. .dfe_enable = 0,
  486. .dfe_tap = 0,
  487. .tx_tap_dly = 0,
  488. .tx_tap_adv = 0,
  489. },
  490. };
  491. static struct sparx5_sd10g28_media_preset media_presets_10g[] = {
  492. { /* ETH_MEDIA_DEFAULT */
  493. .cfg_en_adv = 0,
  494. .cfg_en_main = 1,
  495. .cfg_en_dly = 0,
  496. .cfg_tap_adv_3_0 = 0,
  497. .cfg_tap_main = 1,
  498. .cfg_tap_dly_4_0 = 0,
  499. .cfg_vga_ctrl_3_0 = 5,
  500. .cfg_vga_cp_2_0 = 0,
  501. .cfg_eq_res_3_0 = 0xa,
  502. .cfg_eq_r_byp = 1,
  503. .cfg_eq_c_force_3_0 = 0x8,
  504. .cfg_alos_thr_3_0 = 0x3,
  505. },
  506. { /* ETH_MEDIA_SR */
  507. .cfg_en_adv = 1,
  508. .cfg_en_main = 1,
  509. .cfg_en_dly = 1,
  510. .cfg_tap_adv_3_0 = 0,
  511. .cfg_tap_main = 1,
  512. .cfg_tap_dly_4_0 = 0xc,
  513. .cfg_vga_ctrl_3_0 = 0xa,
  514. .cfg_vga_cp_2_0 = 0x4,
  515. .cfg_eq_res_3_0 = 0xa,
  516. .cfg_eq_r_byp = 1,
  517. .cfg_eq_c_force_3_0 = 0xF,
  518. .cfg_alos_thr_3_0 = 0x3,
  519. },
  520. { /* ETH_MEDIA_DAC */
  521. .cfg_en_adv = 1,
  522. .cfg_en_main = 1,
  523. .cfg_en_dly = 1,
  524. .cfg_tap_adv_3_0 = 12,
  525. .cfg_tap_main = 1,
  526. .cfg_tap_dly_4_0 = 8,
  527. .cfg_vga_ctrl_3_0 = 0xa,
  528. .cfg_vga_cp_2_0 = 4,
  529. .cfg_eq_res_3_0 = 0xa,
  530. .cfg_eq_r_byp = 1,
  531. .cfg_eq_c_force_3_0 = 0xf,
  532. .cfg_alos_thr_3_0 = 0x0,
  533. }
  534. };
  535. static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = {
  536. { /* SPX5_SD10G28_MODE_PRESET_10000 */
  537. .bwidth = 64,
  538. .cmu_sel = SPX5_SD10G28_CMU_MAIN,
  539. .rate = 0x0,
  540. .dfe_enable = 1,
  541. .dfe_tap = 0x1f,
  542. .pi_bw_gen1 = 0x0,
  543. .duty_cycle = 0x2,
  544. },
  545. { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */
  546. .bwidth = 16,
  547. .cmu_sel = SPX5_SD10G28_CMU_MAIN,
  548. .rate = 0x1,
  549. .dfe_enable = 0,
  550. .dfe_tap = 0,
  551. .pi_bw_gen1 = 0x5,
  552. .duty_cycle = 0x0,
  553. },
  554. { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */
  555. .bwidth = 64,
  556. .cmu_sel = SPX5_SD10G28_CMU_MAIN,
  557. .rate = 0x1,
  558. .dfe_enable = 0,
  559. .dfe_tap = 0,
  560. .pi_bw_gen1 = 0x5,
  561. .duty_cycle = 0x0,
  562. },
  563. { /* SPX5_SD10G28_MODE_PRESET_QSGMII */
  564. .bwidth = 20,
  565. .cmu_sel = SPX5_SD10G28_CMU_AUX1,
  566. .rate = 0x1,
  567. .dfe_enable = 0,
  568. .dfe_tap = 0,
  569. .pi_bw_gen1 = 0x5,
  570. .duty_cycle = 0x0,
  571. },
  572. { /* SPX5_SD10G28_MODE_PRESET_SD_2G5 */
  573. .bwidth = 10,
  574. .cmu_sel = SPX5_SD10G28_CMU_AUX2,
  575. .rate = 0x2,
  576. .dfe_enable = 0,
  577. .dfe_tap = 0,
  578. .pi_bw_gen1 = 0x7,
  579. .duty_cycle = 0x0,
  580. },
  581. { /* SPX5_SD10G28_MODE_PRESET_1000BASEX */
  582. .bwidth = 10,
  583. .cmu_sel = SPX5_SD10G28_CMU_AUX1,
  584. .rate = 0x3,
  585. .dfe_enable = 0,
  586. .dfe_tap = 0,
  587. .pi_bw_gen1 = 0x7,
  588. .duty_cycle = 0x0,
  589. },
  590. };
  591. /* map from SD25G28 interface width to configuration value */
  592. static u8 sd25g28_get_iw_setting(struct device *dev, const u8 interface_width)
  593. {
  594. switch (interface_width) {
  595. case 10: return 0;
  596. case 16: return 1;
  597. case 32: return 3;
  598. case 40: return 4;
  599. case 64: return 5;
  600. default:
  601. dev_err(dev, "%s: Illegal value %d for interface width\n",
  602. __func__, interface_width);
  603. }
  604. return 0;
  605. }
  606. /* map from SD10G28 interface width to configuration value */
  607. static u8 sd10g28_get_iw_setting(struct device *dev, const u8 interface_width)
  608. {
  609. switch (interface_width) {
  610. case 10: return 0;
  611. case 16: return 1;
  612. case 20: return 2;
  613. case 32: return 3;
  614. case 40: return 4;
  615. case 64: return 7;
  616. default:
  617. dev_err(dev, "%s: Illegal value %d for interface width\n", __func__,
  618. interface_width);
  619. return 0;
  620. }
  621. }
  622. static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro,
  623. struct sparx5_sd25g28_mode_preset *mode)
  624. {
  625. switch (macro->serdesmode) {
  626. case SPX5_SD_MODE_SFI:
  627. if (macro->speed == SPEED_25000)
  628. *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];
  629. else if (macro->speed == SPEED_10000)
  630. *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_10000];
  631. else if (macro->speed == SPEED_5000)
  632. *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_5000];
  633. break;
  634. case SPX5_SD_MODE_2G5:
  635. *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_SD_2G5];
  636. break;
  637. case SPX5_SD_MODE_1000BASEX:
  638. *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_1000BASEX];
  639. break;
  640. case SPX5_SD_MODE_100FX:
  641. /* Not supported */
  642. return -EINVAL;
  643. default:
  644. *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];
  645. break;
  646. }
  647. return 0;
  648. }
  649. static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro,
  650. struct sparx5_sd10g28_mode_preset *mode,
  651. struct sparx5_sd10g28_args *args)
  652. {
  653. switch (macro->serdesmode) {
  654. case SPX5_SD_MODE_SFI:
  655. if (macro->speed == SPEED_10000) {
  656. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];
  657. } else if (macro->speed == SPEED_5000) {
  658. if (args->is_6g)
  659. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_6G];
  660. else
  661. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_10G];
  662. } else {
  663. dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)",
  664. __func__, macro->speed, macro->sidx,
  665. macro->serdesmode);
  666. return -EINVAL;
  667. }
  668. break;
  669. case SPX5_SD_MODE_QSGMII:
  670. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_QSGMII];
  671. break;
  672. case SPX5_SD_MODE_2G5:
  673. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SD_2G5];
  674. break;
  675. case SPX5_SD_MODE_100FX:
  676. case SPX5_SD_MODE_1000BASEX:
  677. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_1000BASEX];
  678. break;
  679. default:
  680. *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];
  681. break;
  682. }
  683. return 0;
  684. }
  685. static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,
  686. struct sparx5_sd25g28_media_preset *media,
  687. struct sparx5_sd25g28_mode_preset *mode,
  688. struct sparx5_sd25g28_args *args,
  689. struct sparx5_sd25g28_params *params)
  690. {
  691. u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth);
  692. struct sparx5_sd25g28_params init = {
  693. .r_d_width_ctrl_2_0 = iw,
  694. .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
  695. .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
  696. .cfg_vco_div_mode_1_0 = mode->vco_div_mode,
  697. .cfg_pre_divsel_1_0 = mode->pre_divsel,
  698. .cfg_sel_div_3_0 = mode->sel_div,
  699. .cfg_vco_start_code_3_0 = 0,
  700. .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth,
  701. .cfg_tx_prediv_1_0 = mode->tx_pre_div,
  702. .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth,
  703. .cfg_tx_subrate_2_0 = mode->subrate,
  704. .cfg_rx_subrate_2_0 = mode->subrate,
  705. .r_multi_lane_mode = 0,
  706. .cfg_cdrck_en = 1,
  707. .cfg_dfeck_en = mode->dfe_enable,
  708. .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1,
  709. .cfg_dfedmx_pd = 1,
  710. .cfg_dfetap_en_5_1 = mode->dfe_tap,
  711. .cfg_dmux_pd = 0,
  712. .cfg_dmux_clk_pd = 1,
  713. .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1,
  714. .cfg_pi_DFE_en = mode->dfe_enable,
  715. .cfg_pi_en = 1,
  716. .cfg_pd_ctle = 0,
  717. .cfg_summer_en = 1,
  718. .cfg_pmad_ck_pd = 0,
  719. .cfg_pd_clk = 0,
  720. .cfg_pd_cml = 0,
  721. .cfg_pd_driver = 0,
  722. .cfg_rx_reg_pu = 1,
  723. .cfg_pd_rms_det = 1,
  724. .cfg_dcdr_pd = 0,
  725. .cfg_ecdr_pd = 1,
  726. .cfg_pd_sq = 1,
  727. .cfg_itx_ipdriver_base_2_0 = mode->txmargin,
  728. .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
  729. .cfg_tap_main = media->cfg_tap_main,
  730. .cfg_en_main = media->cfg_en_main,
  731. .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
  732. .cfg_en_adv = media->cfg_en_adv,
  733. .cfg_en_dly = media->cfg_en_dly,
  734. .cfg_iscan_en = 0,
  735. .l1_pcs_en_fast_iscan = 0,
  736. .l0_cfg_bw_1_0 = 0,
  737. .cfg_en_dummy = 0,
  738. .cfg_pll_reserve_3_0 = args->com_pll_reserve,
  739. .l0_cfg_txcal_en = mode->com_txcal_en,
  740. .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb,
  741. .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb,
  742. .cfg_tx_reserve_15_8 = mode->tx_reserve_msb,
  743. .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb,
  744. .cfg_bw_1_0 = mode->bw,
  745. .cfg_txcal_man_en = 1,
  746. .cfg_phase_man_4_0 = 0,
  747. .cfg_quad_man_1_0 = 0,
  748. .cfg_txcal_shift_code_5_0 = 2,
  749. .cfg_txcal_valid_sel_3_0 = 4,
  750. .cfg_txcal_en = 0,
  751. .cfg_cdr_kf_2_0 = 1,
  752. .cfg_cdr_m_7_0 = 6,
  753. .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0,
  754. .cfg_pi_steps_1_0 = 0,
  755. .cfg_dis_2ndorder = 1,
  756. .cfg_ctle_rstn = mode->cfg_ctle_rstn,
  757. .r_dfe_rstn = mode->r_dfe_rstn,
  758. .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0,
  759. .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base,
  760. .cfg_rx_reserve_7_0 = 0xbf,
  761. .cfg_rx_reserve_15_8 = 0x61,
  762. .cfg_rxterm_2_0 = mode->rxterm,
  763. .cfg_fom_selm = 0,
  764. .cfg_rx_sp_ctle_1_0 = 0,
  765. .cfg_isel_ctle_1_0 = 0,
  766. .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0,
  767. .cfg_vga_byp = 1,
  768. .cfg_agc_adpt_byp = 1,
  769. .cfg_eqr_byp = 1,
  770. .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0,
  771. .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0,
  772. .cfg_sum_setcm_en = 1,
  773. .cfg_pi_dfe_en = 1,
  774. .cfg_init_pos_iscan_6_0 = 6,
  775. .cfg_init_pos_ipi_6_0 = 9,
  776. .cfg_dfedig_m_2_0 = 6,
  777. .cfg_en_dfedig = mode->dfe_enable,
  778. .r_d_width_ctrl_from_hwt = 0,
  779. .r_reg_manual = 1,
  780. .reg_rst = args->reg_rst,
  781. .cfg_jc_byp = 1,
  782. .cfg_common_reserve_7_0 = 1,
  783. .cfg_pll_lol_set = 1,
  784. .cfg_tx2rx_lp_en = 0,
  785. .cfg_txlb_en = 0,
  786. .cfg_rx2tx_lp_en = 0,
  787. .cfg_rxlb_en = 0,
  788. .r_tx_pol_inv = args->txinvert,
  789. .r_rx_pol_inv = args->rxinvert,
  790. };
  791. *params = init;
  792. }
  793. static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,
  794. struct sparx5_sd10g28_media_preset *media,
  795. struct sparx5_sd10g28_mode_preset *mode,
  796. struct sparx5_sd10g28_args *args,
  797. struct sparx5_sd10g28_params *params)
  798. {
  799. u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth);
  800. struct sparx5_sd10g28_params init = {
  801. .skip_cmu_cfg = args->skip_cmu_cfg,
  802. .is_6g = args->is_6g,
  803. .cmu_sel = mode->cmu_sel,
  804. .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6,
  805. .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2),
  806. .cfg_lane_reserve_15_8 = mode->duty_cycle,
  807. .cfg_txrate_1_0 = mode->rate,
  808. .cfg_rxrate_1_0 = mode->rate,
  809. .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX,
  810. .r_d_width_ctrl_2_0 = iw,
  811. .cfg_pma_tx_ck_bitwidth_2_0 = iw,
  812. .cfg_rxdiv_sel_2_0 = iw,
  813. .r_pcs2pma_phymode_4_0 = 0,
  814. .cfg_lane_id_2_0 = 0,
  815. .cfg_cdrck_en = 1,
  816. .cfg_dfeck_en = mode->dfe_enable,
  817. .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1,
  818. .cfg_dfetap_en_5_1 = mode->dfe_tap,
  819. .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1,
  820. .cfg_pi_DFE_en = mode->dfe_enable,
  821. .cfg_pi_en = 1,
  822. .cfg_pd_ctle = 0,
  823. .cfg_summer_en = 1,
  824. .cfg_pd_rx_cktree = 0,
  825. .cfg_pd_clk = 0,
  826. .cfg_pd_cml = 0,
  827. .cfg_pd_driver = 0,
  828. .cfg_rx_reg_pu = 1,
  829. .cfg_d_cdr_pd = 0,
  830. .cfg_pd_sq = mode->dfe_enable,
  831. .cfg_rxdet_en = 0,
  832. .cfg_rxdet_str = 0,
  833. .r_multi_lane_mode = 0,
  834. .cfg_en_adv = media->cfg_en_adv,
  835. .cfg_en_main = 1,
  836. .cfg_en_dly = media->cfg_en_dly,
  837. .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
  838. .cfg_tap_main = media->cfg_tap_main,
  839. .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
  840. .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0,
  841. .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0,
  842. .cfg_eq_res_3_0 = media->cfg_eq_res_3_0,
  843. .cfg_eq_r_byp = media->cfg_eq_r_byp,
  844. .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0,
  845. .cfg_en_dfedig = mode->dfe_enable,
  846. .cfg_sum_setcm_en = 1,
  847. .cfg_en_preemph = 0,
  848. .cfg_itx_ippreemp_base_1_0 = 0,
  849. .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6),
  850. .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63),
  851. .cfg_txswing_half = (args->txmargin),
  852. .cfg_dis_2nd_order = 0x1,
  853. .cfg_rx_ssc_lh = 0x0,
  854. .cfg_pi_floop_steps_1_0 = 0x0,
  855. .cfg_pi_ext_dac_23_16 = (1 << 5),
  856. .cfg_pi_ext_dac_15_8 = (0 << 6),
  857. .cfg_iscan_ext_dac_7_0 = (1 << 7) + 9,
  858. .cfg_cdr_kf_gen1_2_0 = 1,
  859. .cfg_cdr_kf_gen2_2_0 = 1,
  860. .cfg_cdr_kf_gen3_2_0 = 1,
  861. .cfg_cdr_kf_gen4_2_0 = 1,
  862. .r_cdr_m_gen1_7_0 = 4,
  863. .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1,
  864. .cfg_pi_bw_gen2 = mode->pi_bw_gen1,
  865. .cfg_pi_bw_gen3 = mode->pi_bw_gen1,
  866. .cfg_pi_bw_gen4 = mode->pi_bw_gen1,
  867. .cfg_pi_ext_dac_7_0 = 3,
  868. .cfg_pi_steps = 0,
  869. .cfg_mp_max_3_0 = 1,
  870. .cfg_rstn_dfedig = mode->dfe_enable,
  871. .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0,
  872. .cfg_predrv_slewrate_1_0 = 3,
  873. .cfg_itx_ipcml_base_1_0 = 0,
  874. .cfg_ip_pre_base_1_0 = 0,
  875. .r_cdr_m_gen2_7_0 = 2,
  876. .r_cdr_m_gen3_7_0 = 2,
  877. .r_cdr_m_gen4_7_0 = 2,
  878. .r_en_auto_cdr_rstn = 0,
  879. .cfg_oscal_afe = 1,
  880. .cfg_pd_osdac_afe = 0,
  881. .cfg_resetb_oscal_afe[0] = 0,
  882. .cfg_resetb_oscal_afe[1] = 1,
  883. .cfg_center_spreading = 0,
  884. .cfg_m_cnt_maxval_4_0 = 15,
  885. .cfg_ncnt_maxval_7_0 = 32,
  886. .cfg_ncnt_maxval_10_8 = 6,
  887. .cfg_ssc_en = 1,
  888. .cfg_tx2rx_lp_en = 0,
  889. .cfg_txlb_en = 0,
  890. .cfg_rx2tx_lp_en = 0,
  891. .cfg_rxlb_en = 0,
  892. .r_tx_pol_inv = args->txinvert,
  893. .r_rx_pol_inv = args->rxinvert,
  894. };
  895. *params = init;
  896. }
  897. static void sparx5_sd25g28_reset(void __iomem *regs[],
  898. struct sparx5_sd25g28_params *params,
  899. u32 sd_index)
  900. {
  901. if (params->reg_rst == 1) {
  902. sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1),
  903. SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
  904. sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index)));
  905. usleep_range(1000, 2000);
  906. sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),
  907. SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
  908. sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index)));
  909. }
  910. }
  911. static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
  912. struct sparx5_sd25g28_params *params)
  913. {
  914. struct sparx5_serdes_private *priv = macro->priv;
  915. void __iomem **regs = priv->regs;
  916. struct device *dev = priv->dev;
  917. u32 sd_index = macro->stpidx;
  918. u32 value;
  919. sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),
  920. SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
  921. priv,
  922. SD_LANE_25G_SD_LANE_CFG(sd_index));
  923. sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),
  924. SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
  925. priv,
  926. SD25G_LANE_CMU_FF(sd_index));
  927. sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET
  928. (params->r_d_width_ctrl_from_hwt) |
  929. SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
  930. SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |
  931. SD25G_LANE_CMU_1A_R_REG_MANUAL,
  932. priv,
  933. SD25G_LANE_CMU_1A(sd_index));
  934. sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET
  935. (params->cfg_common_reserve_7_0),
  936. SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
  937. priv,
  938. SD25G_LANE_CMU_31(sd_index));
  939. sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
  940. SD25G_LANE_CMU_09_CFG_EN_DUMMY,
  941. priv,
  942. SD25G_LANE_CMU_09(sd_index));
  943. sdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET
  944. (params->cfg_pll_reserve_3_0),
  945. SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,
  946. priv,
  947. SD25G_LANE_CMU_13(sd_index));
  948. sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
  949. SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,
  950. priv,
  951. SD25G_LANE_CMU_40(sd_index));
  952. sdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET
  953. (params->l0_cfg_tx_reserve_15_8),
  954. SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,
  955. priv,
  956. SD25G_LANE_CMU_46(sd_index));
  957. sdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET
  958. (params->l0_cfg_tx_reserve_7_0),
  959. SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,
  960. priv,
  961. SD25G_LANE_CMU_45(sd_index));
  962. sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),
  963. SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
  964. priv,
  965. SD25G_LANE_CMU_0B(sd_index));
  966. sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),
  967. SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
  968. priv,
  969. SD25G_LANE_CMU_0B(sd_index));
  970. sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),
  971. SD25G_LANE_CMU_19_R_CK_RESETB,
  972. priv,
  973. SD25G_LANE_CMU_19(sd_index));
  974. sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),
  975. SD25G_LANE_CMU_19_R_CK_RESETB,
  976. priv,
  977. SD25G_LANE_CMU_19(sd_index));
  978. sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0),
  979. SD25G_LANE_CMU_18_R_PLL_RSTN,
  980. priv,
  981. SD25G_LANE_CMU_18(sd_index));
  982. sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1),
  983. SD25G_LANE_CMU_18_R_PLL_RSTN,
  984. priv,
  985. SD25G_LANE_CMU_18(sd_index));
  986. sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0),
  987. SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0,
  988. priv,
  989. SD25G_LANE_CMU_1A(sd_index));
  990. sdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET
  991. (params->r_txfifo_ck_div_pmad_2_0) |
  992. SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET
  993. (params->r_rxfifo_ck_div_pmad_2_0),
  994. SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 |
  995. SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0,
  996. priv,
  997. SD25G_LANE_CMU_30(sd_index));
  998. sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) |
  999. SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET
  1000. (params->cfg_vco_div_mode_1_0),
  1001. SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET |
  1002. SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0,
  1003. priv,
  1004. SD25G_LANE_CMU_0C(sd_index));
  1005. sdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET
  1006. (params->cfg_pre_divsel_1_0),
  1007. SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0,
  1008. priv,
  1009. SD25G_LANE_CMU_0D(sd_index));
  1010. sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0),
  1011. SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0,
  1012. priv,
  1013. SD25G_LANE_CMU_0E(sd_index));
  1014. sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00),
  1015. SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
  1016. priv,
  1017. SD25G_LANE_CMU_FF(sd_index));
  1018. sdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET
  1019. (params->cfg_pma_tx_ck_bitwidth_2_0),
  1020. SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0,
  1021. priv,
  1022. SD25G_LANE_LANE_0C(sd_index));
  1023. sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET
  1024. (params->cfg_tx_prediv_1_0),
  1025. SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0,
  1026. priv,
  1027. SD25G_LANE_LANE_01(sd_index));
  1028. sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET
  1029. (params->cfg_rxdiv_sel_2_0),
  1030. SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0,
  1031. priv,
  1032. SD25G_LANE_LANE_18(sd_index));
  1033. sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET
  1034. (params->cfg_tx_subrate_2_0),
  1035. SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0,
  1036. priv,
  1037. SD25G_LANE_LANE_2C(sd_index));
  1038. sdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET
  1039. (params->cfg_rx_subrate_2_0),
  1040. SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0,
  1041. priv,
  1042. SD25G_LANE_LANE_28(sd_index));
  1043. sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
  1044. SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN,
  1045. priv,
  1046. SD25G_LANE_LANE_18(sd_index));
  1047. sdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET
  1048. (params->cfg_dfetap_en_5_1),
  1049. SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1,
  1050. priv,
  1051. SD25G_LANE_LANE_0F(sd_index));
  1052. sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
  1053. SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,
  1054. priv,
  1055. SD25G_LANE_LANE_18(sd_index));
  1056. sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en),
  1057. SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN,
  1058. priv,
  1059. SD25G_LANE_LANE_1D(sd_index));
  1060. sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd),
  1061. SD25G_LANE_LANE_19_LN_CFG_ECDR_PD,
  1062. priv,
  1063. SD25G_LANE_LANE_19(sd_index));
  1064. sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET
  1065. (params->cfg_itx_ipdriver_base_2_0),
  1066. SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0,
  1067. priv,
  1068. SD25G_LANE_LANE_01(sd_index));
  1069. sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0),
  1070. SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0,
  1071. priv,
  1072. SD25G_LANE_LANE_03(sd_index));
  1073. sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0),
  1074. SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0,
  1075. priv,
  1076. SD25G_LANE_LANE_06(sd_index));
  1077. sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) |
  1078. SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly),
  1079. SD25G_LANE_LANE_07_LN_CFG_EN_ADV |
  1080. SD25G_LANE_LANE_07_LN_CFG_EN_DLY,
  1081. priv,
  1082. SD25G_LANE_LANE_07(sd_index));
  1083. sdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET
  1084. (params->cfg_tx_reserve_15_8),
  1085. SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8,
  1086. priv,
  1087. SD25G_LANE_LANE_43(sd_index));
  1088. sdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET
  1089. (params->cfg_tx_reserve_7_0),
  1090. SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0,
  1091. priv,
  1092. SD25G_LANE_LANE_42(sd_index));
  1093. sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0),
  1094. SD25G_LANE_LANE_05_LN_CFG_BW_1_0,
  1095. priv,
  1096. SD25G_LANE_LANE_05(sd_index));
  1097. sdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET
  1098. (params->cfg_txcal_man_en),
  1099. SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN,
  1100. priv,
  1101. SD25G_LANE_LANE_0B(sd_index));
  1102. sdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET
  1103. (params->cfg_txcal_shift_code_5_0),
  1104. SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0,
  1105. priv,
  1106. SD25G_LANE_LANE_0A(sd_index));
  1107. sdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET
  1108. (params->cfg_txcal_valid_sel_3_0),
  1109. SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0,
  1110. priv,
  1111. SD25G_LANE_LANE_09(sd_index));
  1112. sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0),
  1113. SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0,
  1114. priv,
  1115. SD25G_LANE_LANE_1A(sd_index));
  1116. sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0),
  1117. SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0,
  1118. priv,
  1119. SD25G_LANE_LANE_1B(sd_index));
  1120. sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0),
  1121. SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0,
  1122. priv,
  1123. SD25G_LANE_LANE_2B(sd_index));
  1124. sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET
  1125. (params->cfg_dis_2ndorder),
  1126. SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER,
  1127. priv,
  1128. SD25G_LANE_LANE_2C(sd_index));
  1129. sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn),
  1130. SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN,
  1131. priv,
  1132. SD25G_LANE_LANE_2E(sd_index));
  1133. sdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET
  1134. (params->cfg_itx_ipcml_base_1_0),
  1135. SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0,
  1136. priv,
  1137. SD25G_LANE_LANE_00(sd_index));
  1138. sdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET
  1139. (params->cfg_rx_reserve_7_0),
  1140. SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0,
  1141. priv,
  1142. SD25G_LANE_LANE_44(sd_index));
  1143. sdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET
  1144. (params->cfg_rx_reserve_15_8),
  1145. SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8,
  1146. priv,
  1147. SD25G_LANE_LANE_45(sd_index));
  1148. sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) |
  1149. SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0),
  1150. SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN |
  1151. SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0,
  1152. priv,
  1153. SD25G_LANE_LANE_0D(sd_index));
  1154. sdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET
  1155. (params->cfg_vga_ctrl_byp_4_0),
  1156. SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0,
  1157. priv,
  1158. SD25G_LANE_LANE_21(sd_index));
  1159. sdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET
  1160. (params->cfg_eqr_force_3_0),
  1161. SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0,
  1162. priv,
  1163. SD25G_LANE_LANE_22(sd_index));
  1164. sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET
  1165. (params->cfg_eqc_force_3_0) |
  1166. SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd),
  1167. SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 |
  1168. SD25G_LANE_LANE_1C_LN_CFG_DFE_PD,
  1169. priv,
  1170. SD25G_LANE_LANE_1C(sd_index));
  1171. sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET
  1172. (params->cfg_sum_setcm_en),
  1173. SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN,
  1174. priv,
  1175. SD25G_LANE_LANE_1E(sd_index));
  1176. sdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET
  1177. (params->cfg_init_pos_iscan_6_0),
  1178. SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0,
  1179. priv,
  1180. SD25G_LANE_LANE_25(sd_index));
  1181. sdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET
  1182. (params->cfg_init_pos_ipi_6_0),
  1183. SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0,
  1184. priv,
  1185. SD25G_LANE_LANE_26(sd_index));
  1186. sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
  1187. SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,
  1188. priv,
  1189. SD25G_LANE_LANE_18(sd_index));
  1190. sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET
  1191. (params->cfg_dfedig_m_2_0),
  1192. SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0,
  1193. priv,
  1194. SD25G_LANE_LANE_0E(sd_index));
  1195. sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig),
  1196. SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG,
  1197. priv,
  1198. SD25G_LANE_LANE_0E(sd_index));
  1199. sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) |
  1200. SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv),
  1201. SD25G_LANE_LANE_40_LN_R_TX_POL_INV |
  1202. SD25G_LANE_LANE_40_LN_R_RX_POL_INV,
  1203. priv,
  1204. SD25G_LANE_LANE_40(sd_index));
  1205. sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) |
  1206. SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en),
  1207. SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN |
  1208. SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN,
  1209. priv,
  1210. SD25G_LANE_LANE_04(sd_index));
  1211. sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en),
  1212. SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN,
  1213. priv,
  1214. SD25G_LANE_LANE_1E(sd_index));
  1215. sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en),
  1216. SD25G_LANE_LANE_19_LN_CFG_TXLB_EN,
  1217. priv,
  1218. SD25G_LANE_LANE_19(sd_index));
  1219. sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0),
  1220. SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,
  1221. priv,
  1222. SD25G_LANE_LANE_2E(sd_index));
  1223. sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1),
  1224. SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,
  1225. priv,
  1226. SD25G_LANE_LANE_2E(sd_index));
  1227. sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0),
  1228. SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
  1229. priv,
  1230. SD_LANE_25G_SD_LANE_CFG(sd_index));
  1231. sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0),
  1232. SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,
  1233. priv,
  1234. SD25G_LANE_LANE_1C(sd_index));
  1235. usleep_range(1000, 2000);
  1236. sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1),
  1237. SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,
  1238. priv,
  1239. SD25G_LANE_LANE_1C(sd_index));
  1240. usleep_range(10000, 20000);
  1241. sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff),
  1242. SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
  1243. priv,
  1244. SD25G_LANE_CMU_FF(sd_index));
  1245. value = readl(sdx5_addr(regs, SD25G_LANE_CMU_C0(sd_index)));
  1246. value = SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(value);
  1247. if (value) {
  1248. dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value);
  1249. return -EINVAL;
  1250. }
  1251. value = readl(sdx5_addr(regs, SD_LANE_25G_SD_LANE_STAT(sd_index)));
  1252. value = SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(value);
  1253. if (value != 0x1) {
  1254. dev_err(dev, "25G PMA Reset failed: 0x%x\n", value);
  1255. return -EINVAL;
  1256. }
  1257. sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1),
  1258. SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS,
  1259. priv,
  1260. SD25G_LANE_CMU_2A(sd_index));
  1261. sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0),
  1262. SD_LANE_25G_SD_SER_RST_SER_RST,
  1263. priv,
  1264. SD_LANE_25G_SD_SER_RST(sd_index));
  1265. sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0),
  1266. SD_LANE_25G_SD_DES_RST_DES_RST,
  1267. priv,
  1268. SD_LANE_25G_SD_DES_RST(sd_index));
  1269. sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0),
  1270. SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
  1271. priv,
  1272. SD25G_LANE_CMU_FF(sd_index));
  1273. sdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET
  1274. (params->cfg_alos_thr_2_0),
  1275. SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0,
  1276. priv,
  1277. SD25G_LANE_LANE_2D(sd_index));
  1278. sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0),
  1279. SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ,
  1280. priv,
  1281. SD25G_LANE_LANE_2E(sd_index));
  1282. sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0),
  1283. SD25G_LANE_LANE_2E_LN_CFG_PD_SQ,
  1284. priv,
  1285. SD25G_LANE_LANE_2E(sd_index));
  1286. return 0;
  1287. }
  1288. static void sparx5_sd10g28_reset(void __iomem *regs[], u32 lane_index)
  1289. {
  1290. /* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */
  1291. sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(1),
  1292. SD_LANE_SD_LANE_CFG_EXT_CFG_RST,
  1293. sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index)));
  1294. usleep_range(1000, 2000);
  1295. sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0),
  1296. SD_LANE_SD_LANE_CFG_EXT_CFG_RST,
  1297. sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index)));
  1298. }
  1299. static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro,
  1300. struct sparx5_sd10g28_params *params)
  1301. {
  1302. struct sparx5_serdes_private *priv = macro->priv;
  1303. void __iomem **regs = priv->regs;
  1304. struct device *dev = priv->dev;
  1305. u32 lane_index = macro->sidx;
  1306. u32 sd_index = macro->stpidx;
  1307. void __iomem *sd_inst;
  1308. u32 value;
  1309. if (params->is_6g)
  1310. sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index);
  1311. else
  1312. sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, sd_index);
  1313. sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1),
  1314. SD_LANE_SD_LANE_CFG_MACRO_RST,
  1315. priv,
  1316. SD_LANE_SD_LANE_CFG(lane_index));
  1317. sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) |
  1318. SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) |
  1319. SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) |
  1320. SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) |
  1321. SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0),
  1322. SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT |
  1323. SD10G_LANE_LANE_93_R_REG_MANUAL |
  1324. SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT |
  1325. SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT |
  1326. SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL,
  1327. sd_inst,
  1328. SD10G_LANE_LANE_93(sd_index));
  1329. sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) |
  1330. SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) |
  1331. SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) |
  1332. SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1),
  1333. SD10G_LANE_LANE_94_R_ISCAN_REG |
  1334. SD10G_LANE_LANE_94_R_TXEQ_REG |
  1335. SD10G_LANE_LANE_94_R_MISC_REG |
  1336. SD10G_LANE_LANE_94_R_SWING_REG,
  1337. sd_inst,
  1338. SD10G_LANE_LANE_94(sd_index));
  1339. sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1),
  1340. SD10G_LANE_LANE_9E_R_RXEQ_REG,
  1341. sd_inst,
  1342. SD10G_LANE_LANE_9E(sd_index));
  1343. sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) |
  1344. SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) |
  1345. SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1),
  1346. SD10G_LANE_LANE_A1_R_SSC_FROM_HWT |
  1347. SD10G_LANE_LANE_A1_R_CDR_FROM_HWT |
  1348. SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT,
  1349. sd_inst,
  1350. SD10G_LANE_LANE_A1(sd_index));
  1351. sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) |
  1352. SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel),
  1353. SD_LANE_SD_LANE_CFG_RX_REF_SEL |
  1354. SD_LANE_SD_LANE_CFG_TX_REF_SEL,
  1355. priv,
  1356. SD_LANE_SD_LANE_CFG(lane_index));
  1357. sdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET
  1358. (params->cfg_lane_reserve_7_0),
  1359. SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0,
  1360. sd_inst,
  1361. SD10G_LANE_LANE_40(sd_index));
  1362. sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET
  1363. (params->cfg_ssc_rtl_clk_sel),
  1364. SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL,
  1365. sd_inst,
  1366. SD10G_LANE_LANE_50(sd_index));
  1367. sdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET
  1368. (params->cfg_txrate_1_0) |
  1369. SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET
  1370. (params->cfg_rxrate_1_0),
  1371. SD10G_LANE_LANE_35_CFG_TXRATE_1_0 |
  1372. SD10G_LANE_LANE_35_CFG_RXRATE_1_0,
  1373. sd_inst,
  1374. SD10G_LANE_LANE_35(sd_index));
  1375. sdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET
  1376. (params->r_d_width_ctrl_2_0),
  1377. SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0,
  1378. sd_inst,
  1379. SD10G_LANE_LANE_94(sd_index));
  1380. sdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET
  1381. (params->cfg_pma_tx_ck_bitwidth_2_0),
  1382. SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0,
  1383. sd_inst,
  1384. SD10G_LANE_LANE_01(sd_index));
  1385. sdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET
  1386. (params->cfg_rxdiv_sel_2_0),
  1387. SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0,
  1388. sd_inst,
  1389. SD10G_LANE_LANE_30(sd_index));
  1390. sdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET
  1391. (params->r_pcs2pma_phymode_4_0),
  1392. SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0,
  1393. sd_inst,
  1394. SD10G_LANE_LANE_A2(sd_index));
  1395. sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
  1396. SD10G_LANE_LANE_13_CFG_CDRCK_EN,
  1397. sd_inst,
  1398. SD10G_LANE_LANE_13(sd_index));
  1399. sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET
  1400. (params->cfg_dfeck_en) |
  1401. SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) |
  1402. SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET
  1403. (params->cfg_erramp_pd),
  1404. SD10G_LANE_LANE_23_CFG_DFECK_EN |
  1405. SD10G_LANE_LANE_23_CFG_DFE_PD |
  1406. SD10G_LANE_LANE_23_CFG_ERRAMP_PD,
  1407. sd_inst,
  1408. SD10G_LANE_LANE_23(sd_index));
  1409. sdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET
  1410. (params->cfg_dfetap_en_5_1),
  1411. SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1,
  1412. sd_inst,
  1413. SD10G_LANE_LANE_22(sd_index));
  1414. sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET
  1415. (params->cfg_pi_DFE_en),
  1416. SD10G_LANE_LANE_1A_CFG_PI_DFE_EN,
  1417. sd_inst,
  1418. SD10G_LANE_LANE_1A(sd_index));
  1419. sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) |
  1420. SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) |
  1421. SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) |
  1422. SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET
  1423. (params->cfg_tap_adv_3_0),
  1424. SD10G_LANE_LANE_02_CFG_EN_ADV |
  1425. SD10G_LANE_LANE_02_CFG_EN_MAIN |
  1426. SD10G_LANE_LANE_02_CFG_EN_DLY |
  1427. SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0,
  1428. sd_inst,
  1429. SD10G_LANE_LANE_02(sd_index));
  1430. sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main),
  1431. SD10G_LANE_LANE_03_CFG_TAP_MAIN,
  1432. sd_inst,
  1433. SD10G_LANE_LANE_03(sd_index));
  1434. sdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET
  1435. (params->cfg_tap_dly_4_0),
  1436. SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0,
  1437. sd_inst,
  1438. SD10G_LANE_LANE_04(sd_index));
  1439. sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET
  1440. (params->cfg_vga_ctrl_3_0),
  1441. SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0,
  1442. sd_inst,
  1443. SD10G_LANE_LANE_2F(sd_index));
  1444. sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET
  1445. (params->cfg_vga_cp_2_0),
  1446. SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0,
  1447. sd_inst,
  1448. SD10G_LANE_LANE_2F(sd_index));
  1449. sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET
  1450. (params->cfg_eq_res_3_0),
  1451. SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0,
  1452. sd_inst,
  1453. SD10G_LANE_LANE_0B(sd_index));
  1454. sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp),
  1455. SD10G_LANE_LANE_0D_CFG_EQR_BYP,
  1456. sd_inst,
  1457. SD10G_LANE_LANE_0D(sd_index));
  1458. sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET
  1459. (params->cfg_eq_c_force_3_0) |
  1460. SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET
  1461. (params->cfg_sum_setcm_en),
  1462. SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 |
  1463. SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN,
  1464. sd_inst,
  1465. SD10G_LANE_LANE_0E(sd_index));
  1466. sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET
  1467. (params->cfg_en_dfedig),
  1468. SD10G_LANE_LANE_23_CFG_EN_DFEDIG,
  1469. sd_inst,
  1470. SD10G_LANE_LANE_23(sd_index));
  1471. sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET
  1472. (params->cfg_en_preemph),
  1473. SD10G_LANE_LANE_06_CFG_EN_PREEMPH,
  1474. sd_inst,
  1475. SD10G_LANE_LANE_06(sd_index));
  1476. sdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET
  1477. (params->cfg_itx_ippreemp_base_1_0) |
  1478. SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET
  1479. (params->cfg_itx_ipdriver_base_2_0),
  1480. SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 |
  1481. SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0,
  1482. sd_inst,
  1483. SD10G_LANE_LANE_33(sd_index));
  1484. sdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET
  1485. (params->cfg_ibias_tune_reserve_5_0),
  1486. SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0,
  1487. sd_inst,
  1488. SD10G_LANE_LANE_52(sd_index));
  1489. sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET
  1490. (params->cfg_txswing_half),
  1491. SD10G_LANE_LANE_37_CFG_TXSWING_HALF,
  1492. sd_inst,
  1493. SD10G_LANE_LANE_37(sd_index));
  1494. sdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET
  1495. (params->cfg_dis_2nd_order),
  1496. SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER,
  1497. sd_inst,
  1498. SD10G_LANE_LANE_3C(sd_index));
  1499. sdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET
  1500. (params->cfg_rx_ssc_lh),
  1501. SD10G_LANE_LANE_39_CFG_RX_SSC_LH,
  1502. sd_inst,
  1503. SD10G_LANE_LANE_39(sd_index));
  1504. sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET
  1505. (params->cfg_pi_floop_steps_1_0),
  1506. SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0,
  1507. sd_inst,
  1508. SD10G_LANE_LANE_1A(sd_index));
  1509. sdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET
  1510. (params->cfg_pi_ext_dac_23_16),
  1511. SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16,
  1512. sd_inst,
  1513. SD10G_LANE_LANE_16(sd_index));
  1514. sdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET
  1515. (params->cfg_pi_ext_dac_15_8),
  1516. SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8,
  1517. sd_inst,
  1518. SD10G_LANE_LANE_15(sd_index));
  1519. sdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET
  1520. (params->cfg_iscan_ext_dac_7_0),
  1521. SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0,
  1522. sd_inst,
  1523. SD10G_LANE_LANE_26(sd_index));
  1524. sdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET
  1525. (params->cfg_cdr_kf_gen1_2_0),
  1526. SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0,
  1527. sd_inst,
  1528. SD10G_LANE_LANE_42(sd_index));
  1529. sdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET
  1530. (params->r_cdr_m_gen1_7_0),
  1531. SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0,
  1532. sd_inst,
  1533. SD10G_LANE_LANE_0F(sd_index));
  1534. sdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET
  1535. (params->cfg_pi_bw_gen1_3_0),
  1536. SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0,
  1537. sd_inst,
  1538. SD10G_LANE_LANE_24(sd_index));
  1539. sdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET
  1540. (params->cfg_pi_ext_dac_7_0),
  1541. SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0,
  1542. sd_inst,
  1543. SD10G_LANE_LANE_14(sd_index));
  1544. sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps),
  1545. SD10G_LANE_LANE_1A_CFG_PI_STEPS,
  1546. sd_inst,
  1547. SD10G_LANE_LANE_1A(sd_index));
  1548. sdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET
  1549. (params->cfg_mp_max_3_0),
  1550. SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0,
  1551. sd_inst,
  1552. SD10G_LANE_LANE_3A(sd_index));
  1553. sdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET
  1554. (params->cfg_rstn_dfedig),
  1555. SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG,
  1556. sd_inst,
  1557. SD10G_LANE_LANE_31(sd_index));
  1558. sdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET
  1559. (params->cfg_alos_thr_3_0),
  1560. SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0,
  1561. sd_inst,
  1562. SD10G_LANE_LANE_48(sd_index));
  1563. sdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET
  1564. (params->cfg_predrv_slewrate_1_0),
  1565. SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0,
  1566. sd_inst,
  1567. SD10G_LANE_LANE_36(sd_index));
  1568. sdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET
  1569. (params->cfg_itx_ipcml_base_1_0),
  1570. SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0,
  1571. sd_inst,
  1572. SD10G_LANE_LANE_32(sd_index));
  1573. sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET
  1574. (params->cfg_ip_pre_base_1_0),
  1575. SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0,
  1576. sd_inst,
  1577. SD10G_LANE_LANE_37(sd_index));
  1578. sdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET
  1579. (params->cfg_lane_reserve_15_8),
  1580. SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8,
  1581. sd_inst,
  1582. SD10G_LANE_LANE_41(sd_index));
  1583. sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET
  1584. (params->r_en_auto_cdr_rstn),
  1585. SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN,
  1586. sd_inst,
  1587. SD10G_LANE_LANE_9E(sd_index));
  1588. sdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET
  1589. (params->cfg_oscal_afe) |
  1590. SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET
  1591. (params->cfg_pd_osdac_afe),
  1592. SD10G_LANE_LANE_0C_CFG_OSCAL_AFE |
  1593. SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE,
  1594. sd_inst,
  1595. SD10G_LANE_LANE_0C(sd_index));
  1596. sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET
  1597. (params->cfg_resetb_oscal_afe[0]),
  1598. SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,
  1599. sd_inst,
  1600. SD10G_LANE_LANE_0B(sd_index));
  1601. sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET
  1602. (params->cfg_resetb_oscal_afe[1]),
  1603. SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,
  1604. sd_inst,
  1605. SD10G_LANE_LANE_0B(sd_index));
  1606. sdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET
  1607. (params->r_tx_pol_inv) |
  1608. SD10G_LANE_LANE_83_R_RX_POL_INV_SET
  1609. (params->r_rx_pol_inv),
  1610. SD10G_LANE_LANE_83_R_TX_POL_INV |
  1611. SD10G_LANE_LANE_83_R_RX_POL_INV,
  1612. sd_inst,
  1613. SD10G_LANE_LANE_83(sd_index));
  1614. sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET
  1615. (params->cfg_rx2tx_lp_en) |
  1616. SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET
  1617. (params->cfg_tx2rx_lp_en),
  1618. SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN |
  1619. SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN,
  1620. sd_inst,
  1621. SD10G_LANE_LANE_06(sd_index));
  1622. sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) |
  1623. SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en),
  1624. SD10G_LANE_LANE_0E_CFG_RXLB_EN |
  1625. SD10G_LANE_LANE_0E_CFG_TXLB_EN,
  1626. sd_inst,
  1627. SD10G_LANE_LANE_0E(sd_index));
  1628. sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0),
  1629. SD_LANE_SD_LANE_CFG_MACRO_RST,
  1630. priv,
  1631. SD_LANE_SD_LANE_CFG(lane_index));
  1632. sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),
  1633. SD10G_LANE_LANE_50_CFG_SSC_RESETB,
  1634. sd_inst,
  1635. SD10G_LANE_LANE_50(sd_index));
  1636. sdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),
  1637. SD10G_LANE_LANE_50_CFG_SSC_RESETB,
  1638. priv,
  1639. SD10G_LANE_LANE_50(sd_index));
  1640. sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100),
  1641. SD_LANE_MISC_SD_125_RST_DIS,
  1642. priv,
  1643. SD_LANE_MISC(lane_index));
  1644. sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100),
  1645. SD_LANE_MISC_RX_ENA,
  1646. priv,
  1647. SD_LANE_MISC(lane_index));
  1648. sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100),
  1649. SD_LANE_MISC_MUX_ENA,
  1650. priv,
  1651. SD_LANE_MISC(lane_index));
  1652. usleep_range(3000, 6000);
  1653. value = readl(sdx5_addr(regs, SD_LANE_SD_LANE_STAT(lane_index)));
  1654. value = SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(value);
  1655. if (value != 1) {
  1656. dev_err(dev, "10G PMA Reset failed: 0x%x\n", value);
  1657. return -EINVAL;
  1658. }
  1659. sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0),
  1660. SD_LANE_SD_SER_RST_SER_RST,
  1661. priv,
  1662. SD_LANE_SD_SER_RST(lane_index));
  1663. sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0),
  1664. SD_LANE_SD_DES_RST_DES_RST,
  1665. priv,
  1666. SD_LANE_SD_DES_RST(lane_index));
  1667. return 0;
  1668. }
  1669. static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset)
  1670. {
  1671. struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media];
  1672. struct sparx5_sd25g28_mode_preset mode;
  1673. struct sparx5_sd25g28_args args = {
  1674. .rxinvert = 1,
  1675. .txinvert = 0,
  1676. .txswing = 240,
  1677. .com_pll_reserve = 0xf,
  1678. .reg_rst = reset,
  1679. };
  1680. struct sparx5_sd25g28_params params;
  1681. int err;
  1682. err = sparx5_sd10g25_get_mode_preset(macro, &mode);
  1683. if (err)
  1684. return err;
  1685. sparx5_sd25g28_get_params(macro, &media, &mode, &args, &params);
  1686. sparx5_sd25g28_reset(macro->priv->regs, &params, macro->stpidx);
  1687. return sparx5_sd25g28_apply_params(macro, &params);
  1688. }
  1689. static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset)
  1690. {
  1691. struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media];
  1692. struct sparx5_sd10g28_mode_preset mode;
  1693. struct sparx5_sd10g28_params params;
  1694. struct sparx5_sd10g28_args args = {
  1695. .is_6g = (macro->serdestype == SPX5_SDT_6G),
  1696. .txinvert = 0,
  1697. .rxinvert = 1,
  1698. .txswing = 240,
  1699. .reg_rst = reset,
  1700. };
  1701. int err;
  1702. err = sparx5_sd10g28_get_mode_preset(macro, &mode, &args);
  1703. if (err)
  1704. return err;
  1705. sparx5_sd10g28_get_params(macro, &media, &mode, &args, &params);
  1706. sparx5_sd10g28_reset(macro->priv->regs, macro->sidx);
  1707. return sparx5_sd10g28_apply_params(macro, &params);
  1708. }
  1709. /* Power down serdes TX driver */
  1710. static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn)
  1711. {
  1712. struct sparx5_serdes_private *priv = macro->priv;
  1713. void __iomem *sd_inst;
  1714. if (macro->serdestype == SPX5_SDT_6G)
  1715. sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx);
  1716. else if (macro->serdestype == SPX5_SDT_10G)
  1717. sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, macro->stpidx);
  1718. else
  1719. sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx);
  1720. if (macro->serdestype == SPX5_SDT_25G) {
  1721. sdx5_inst_rmw(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(pwdn),
  1722. SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER,
  1723. sd_inst,
  1724. SD25G_LANE_LANE_04(0));
  1725. } else {
  1726. /* 6G and 10G */
  1727. sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(pwdn),
  1728. SD10G_LANE_LANE_06_CFG_PD_DRIVER,
  1729. sd_inst,
  1730. SD10G_LANE_LANE_06(0));
  1731. }
  1732. return 0;
  1733. }
  1734. static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro)
  1735. {
  1736. struct sparx5_serdes_private *priv = macro->priv;
  1737. if (macro->serdesmode == SPX5_SD_MODE_100FX) {
  1738. u32 freq = priv->coreclock == 250000000 ? 2 :
  1739. priv->coreclock == 500000000 ? 1 : 0;
  1740. sdx5_rmw(SD_LANE_MISC_CORE_CLK_FREQ_SET(freq),
  1741. SD_LANE_MISC_CORE_CLK_FREQ,
  1742. priv,
  1743. SD_LANE_MISC(macro->sidx));
  1744. }
  1745. return 0;
  1746. }
  1747. static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,
  1748. u32 cmu_idx,
  1749. void __iomem *cmu_tgt,
  1750. void __iomem *cmu_cfg_tgt,
  1751. u32 spd10g)
  1752. {
  1753. void __iomem **regs = priv->regs;
  1754. struct device *dev = priv->dev;
  1755. int value;
  1756. cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
  1757. cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
  1758. if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
  1759. cmu_idx == 10 || cmu_idx == 13) {
  1760. spd10g = 0;
  1761. }
  1762. sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),
  1763. SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
  1764. cmu_cfg_tgt,
  1765. SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
  1766. sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
  1767. SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
  1768. cmu_cfg_tgt,
  1769. SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
  1770. sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),
  1771. SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
  1772. cmu_cfg_tgt,
  1773. SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
  1774. sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |
  1775. SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) |
  1776. SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) |
  1777. SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) |
  1778. SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0),
  1779. SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT |
  1780. SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT |
  1781. SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT |
  1782. SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT |
  1783. SD_CMU_CMU_45_R_EN_RATECHG_CTRL,
  1784. cmu_tgt,
  1785. SD_CMU_CMU_45(cmu_idx));
  1786. sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),
  1787. SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0,
  1788. cmu_tgt,
  1789. SD_CMU_CMU_47(cmu_idx));
  1790. sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),
  1791. SD_CMU_CMU_1B_CFG_RESERVE_7_0,
  1792. cmu_tgt,
  1793. SD_CMU_CMU_1B(cmu_idx));
  1794. sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),
  1795. SD_CMU_CMU_0D_CFG_JC_BYP,
  1796. cmu_tgt,
  1797. SD_CMU_CMU_0D(cmu_idx));
  1798. sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),
  1799. SD_CMU_CMU_1F_CFG_VTUNE_SEL,
  1800. cmu_tgt,
  1801. SD_CMU_CMU_1F(cmu_idx));
  1802. sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),
  1803. SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0,
  1804. cmu_tgt,
  1805. SD_CMU_CMU_00(cmu_idx));
  1806. sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3),
  1807. SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0,
  1808. cmu_tgt,
  1809. SD_CMU_CMU_05(cmu_idx));
  1810. sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1),
  1811. SD_CMU_CMU_30_R_PLL_DLOL_EN,
  1812. cmu_tgt,
  1813. SD_CMU_CMU_30(cmu_idx));
  1814. sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g),
  1815. SD_CMU_CMU_09_CFG_SW_10G,
  1816. cmu_tgt,
  1817. SD_CMU_CMU_09(cmu_idx));
  1818. sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0),
  1819. SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
  1820. cmu_cfg_tgt,
  1821. SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
  1822. msleep(20);
  1823. sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0),
  1824. SD_CMU_CMU_44_R_PLL_RSTN,
  1825. cmu_tgt,
  1826. SD_CMU_CMU_44(cmu_idx));
  1827. sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1),
  1828. SD_CMU_CMU_44_R_PLL_RSTN,
  1829. cmu_tgt,
  1830. SD_CMU_CMU_44(cmu_idx));
  1831. msleep(20);
  1832. value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx)));
  1833. value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value);
  1834. if (value) {
  1835. dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value);
  1836. return -EINVAL;
  1837. }
  1838. sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0),
  1839. SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD,
  1840. cmu_tgt,
  1841. SD_CMU_CMU_0D(cmu_idx));
  1842. return 0;
  1843. }
  1844. static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)
  1845. {
  1846. void __iomem *cmu_tgt, *cmu_cfg_tgt;
  1847. u32 spd10g = 1;
  1848. if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
  1849. cmu_idx == 10 || cmu_idx == 13) {
  1850. spd10g = 0;
  1851. }
  1852. cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
  1853. cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
  1854. return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);
  1855. }
  1856. static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv)
  1857. {
  1858. int idx, err = 0;
  1859. if (!priv->cmu_enabled) {
  1860. for (idx = 0; idx < SPX5_CMU_MAX; idx++) {
  1861. err = sparx5_cmu_cfg(priv, idx);
  1862. if (err) {
  1863. dev_err(priv->dev, "CMU %u, error: %d\n", idx, err);
  1864. goto leave;
  1865. }
  1866. }
  1867. priv->cmu_enabled = true;
  1868. }
  1869. leave:
  1870. return err;
  1871. }
  1872. static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed)
  1873. {
  1874. switch (portmode) {
  1875. case PHY_INTERFACE_MODE_1000BASEX:
  1876. case PHY_INTERFACE_MODE_2500BASEX:
  1877. if (speed == SPEED_2500)
  1878. return SPX5_SD_MODE_2G5;
  1879. if (speed == SPEED_100)
  1880. return SPX5_SD_MODE_100FX;
  1881. return SPX5_SD_MODE_1000BASEX;
  1882. case PHY_INTERFACE_MODE_SGMII:
  1883. /* The same Serdes mode is used for both SGMII and 1000BaseX */
  1884. return SPX5_SD_MODE_1000BASEX;
  1885. case PHY_INTERFACE_MODE_QSGMII:
  1886. return SPX5_SD_MODE_QSGMII;
  1887. case PHY_INTERFACE_MODE_10GBASER:
  1888. return SPX5_SD_MODE_SFI;
  1889. default:
  1890. return -EINVAL;
  1891. }
  1892. }
  1893. static int sparx5_serdes_config(struct sparx5_serdes_macro *macro)
  1894. {
  1895. struct device *dev = macro->priv->dev;
  1896. int serdesmode;
  1897. int err;
  1898. err = sparx5_serdes_cmu_enable(macro->priv);
  1899. if (err)
  1900. return err;
  1901. serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed);
  1902. if (serdesmode < 0) {
  1903. dev_err(dev, "SerDes %u, interface not supported: %s\n",
  1904. macro->sidx,
  1905. phy_modes(macro->portmode));
  1906. return serdesmode;
  1907. }
  1908. macro->serdesmode = serdesmode;
  1909. sparx5_serdes_clock_config(macro);
  1910. if (macro->serdestype == SPX5_SDT_25G)
  1911. err = sparx5_sd25g28_config(macro, false);
  1912. else
  1913. err = sparx5_sd10g28_config(macro, false);
  1914. if (err) {
  1915. dev_err(dev, "SerDes %u, config error: %d\n",
  1916. macro->sidx, err);
  1917. }
  1918. return err;
  1919. }
  1920. static int sparx5_serdes_power_on(struct phy *phy)
  1921. {
  1922. struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
  1923. return sparx5_serdes_power_save(macro, false);
  1924. }
  1925. static int sparx5_serdes_power_off(struct phy *phy)
  1926. {
  1927. struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
  1928. return sparx5_serdes_power_save(macro, true);
  1929. }
  1930. static int sparx5_serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
  1931. {
  1932. struct sparx5_serdes_macro *macro;
  1933. if (mode != PHY_MODE_ETHERNET)
  1934. return -EINVAL;
  1935. switch (submode) {
  1936. case PHY_INTERFACE_MODE_1000BASEX:
  1937. case PHY_INTERFACE_MODE_2500BASEX:
  1938. case PHY_INTERFACE_MODE_SGMII:
  1939. case PHY_INTERFACE_MODE_QSGMII:
  1940. case PHY_INTERFACE_MODE_10GBASER:
  1941. macro = phy_get_drvdata(phy);
  1942. macro->portmode = submode;
  1943. sparx5_serdes_config(macro);
  1944. return 0;
  1945. default:
  1946. return -EINVAL;
  1947. }
  1948. }
  1949. static int sparx5_serdes_set_media(struct phy *phy, enum phy_media media)
  1950. {
  1951. struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
  1952. if (media != macro->media) {
  1953. macro->media = media;
  1954. if (macro->serdesmode != SPX5_SD_MODE_NONE)
  1955. sparx5_serdes_config(macro);
  1956. }
  1957. return 0;
  1958. }
  1959. static int sparx5_serdes_set_speed(struct phy *phy, int speed)
  1960. {
  1961. struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
  1962. if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000)
  1963. return -EINVAL;
  1964. if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000)
  1965. return -EINVAL;
  1966. if (speed != macro->speed) {
  1967. macro->speed = speed;
  1968. if (macro->serdesmode != SPX5_SD_MODE_NONE)
  1969. sparx5_serdes_config(macro);
  1970. }
  1971. return 0;
  1972. }
  1973. static int sparx5_serdes_reset(struct phy *phy)
  1974. {
  1975. struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
  1976. int err;
  1977. err = sparx5_serdes_cmu_enable(macro->priv);
  1978. if (err)
  1979. return err;
  1980. if (macro->serdestype == SPX5_SDT_25G)
  1981. err = sparx5_sd25g28_config(macro, true);
  1982. else
  1983. err = sparx5_sd10g28_config(macro, true);
  1984. if (err) {
  1985. dev_err(&phy->dev, "SerDes %u, reset error: %d\n",
  1986. macro->sidx, err);
  1987. }
  1988. return err;
  1989. }
  1990. static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode,
  1991. int submode,
  1992. union phy_configure_opts *opts)
  1993. {
  1994. struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
  1995. if (mode != PHY_MODE_ETHERNET)
  1996. return -EINVAL;
  1997. if (macro->speed == 0)
  1998. return -EINVAL;
  1999. if (macro->sidx < SPX5_SERDES_10G_START && macro->speed > SPEED_5000)
  2000. return -EINVAL;
  2001. if (macro->sidx < SPX5_SERDES_25G_START && macro->speed > SPEED_10000)
  2002. return -EINVAL;
  2003. switch (submode) {
  2004. case PHY_INTERFACE_MODE_1000BASEX:
  2005. if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */
  2006. macro->speed != SPEED_1000)
  2007. return -EINVAL;
  2008. break;
  2009. case PHY_INTERFACE_MODE_SGMII:
  2010. case PHY_INTERFACE_MODE_2500BASEX:
  2011. case PHY_INTERFACE_MODE_QSGMII:
  2012. if (macro->speed >= SPEED_5000)
  2013. return -EINVAL;
  2014. break;
  2015. case PHY_INTERFACE_MODE_10GBASER:
  2016. if (macro->speed < SPEED_5000)
  2017. return -EINVAL;
  2018. break;
  2019. default:
  2020. return -EINVAL;
  2021. }
  2022. return 0;
  2023. }
  2024. static const struct phy_ops sparx5_serdes_ops = {
  2025. .power_on = sparx5_serdes_power_on,
  2026. .power_off = sparx5_serdes_power_off,
  2027. .set_mode = sparx5_serdes_set_mode,
  2028. .set_media = sparx5_serdes_set_media,
  2029. .set_speed = sparx5_serdes_set_speed,
  2030. .reset = sparx5_serdes_reset,
  2031. .validate = sparx5_serdes_validate,
  2032. .owner = THIS_MODULE,
  2033. };
  2034. static int sparx5_phy_create(struct sparx5_serdes_private *priv,
  2035. int idx, struct phy **phy)
  2036. {
  2037. struct sparx5_serdes_macro *macro;
  2038. *phy = devm_phy_create(priv->dev, NULL, &sparx5_serdes_ops);
  2039. if (IS_ERR(*phy))
  2040. return PTR_ERR(*phy);
  2041. macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL);
  2042. if (!macro)
  2043. return -ENOMEM;
  2044. macro->sidx = idx;
  2045. macro->priv = priv;
  2046. macro->speed = SPEED_UNKNOWN;
  2047. if (idx < SPX5_SERDES_10G_START) {
  2048. macro->serdestype = SPX5_SDT_6G;
  2049. macro->stpidx = macro->sidx;
  2050. } else if (idx < SPX5_SERDES_25G_START) {
  2051. macro->serdestype = SPX5_SDT_10G;
  2052. macro->stpidx = macro->sidx - SPX5_SERDES_10G_START;
  2053. } else {
  2054. macro->serdestype = SPX5_SDT_25G;
  2055. macro->stpidx = macro->sidx - SPX5_SERDES_25G_START;
  2056. }
  2057. phy_set_drvdata(*phy, macro);
  2058. return 0;
  2059. }
  2060. static struct sparx5_serdes_io_resource sparx5_serdes_iomap[] = {
  2061. { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */
  2062. { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */
  2063. { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */
  2064. { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */
  2065. { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */
  2066. { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */
  2067. { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */
  2068. { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */
  2069. { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */
  2070. { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */
  2071. { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */
  2072. { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */
  2073. { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */
  2074. { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */
  2075. { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */
  2076. { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */
  2077. { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */
  2078. { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */
  2079. { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */
  2080. { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */
  2081. { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */
  2082. { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */
  2083. { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */
  2084. { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */
  2085. { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */
  2086. { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */
  2087. { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */
  2088. { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */
  2089. { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */
  2090. { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */
  2091. { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */
  2092. { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */
  2093. { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */
  2094. { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */
  2095. { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */
  2096. { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */
  2097. { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */
  2098. { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */
  2099. { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */
  2100. { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */
  2101. { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */
  2102. { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */
  2103. { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */
  2104. { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */
  2105. { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */
  2106. { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */
  2107. { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */
  2108. { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */
  2109. { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */
  2110. { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */
  2111. { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */
  2112. { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */
  2113. { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */
  2114. { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */
  2115. { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */
  2116. { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */
  2117. { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */
  2118. { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */
  2119. { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */
  2120. { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */
  2121. { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */
  2122. { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */
  2123. { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */
  2124. { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */
  2125. { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */
  2126. { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */
  2127. { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */
  2128. { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */
  2129. { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */
  2130. { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */
  2131. { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */
  2132. { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */
  2133. { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */
  2134. { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */
  2135. { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */
  2136. { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */
  2137. { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */
  2138. { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */
  2139. { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */
  2140. { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */
  2141. { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */
  2142. { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */
  2143. { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */
  2144. { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */
  2145. { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */
  2146. { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */
  2147. { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */
  2148. { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */
  2149. { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */
  2150. { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */
  2151. { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */
  2152. { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */
  2153. { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */
  2154. { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */
  2155. };
  2156. /* Client lookup function, uses serdes index */
  2157. static struct phy *sparx5_serdes_xlate(struct device *dev,
  2158. struct of_phandle_args *args)
  2159. {
  2160. struct sparx5_serdes_private *priv = dev_get_drvdata(dev);
  2161. int idx;
  2162. unsigned int sidx;
  2163. if (args->args_count != 1)
  2164. return ERR_PTR(-EINVAL);
  2165. sidx = args->args[0];
  2166. /* Check validity: ERR_PTR(-ENODEV) if not valid */
  2167. for (idx = 0; idx < SPX5_SERDES_MAX; idx++) {
  2168. struct sparx5_serdes_macro *macro =
  2169. phy_get_drvdata(priv->phys[idx]);
  2170. if (sidx != macro->sidx)
  2171. continue;
  2172. return priv->phys[idx];
  2173. }
  2174. return ERR_PTR(-ENODEV);
  2175. }
  2176. static int sparx5_serdes_probe(struct platform_device *pdev)
  2177. {
  2178. struct device_node *np = pdev->dev.of_node;
  2179. struct sparx5_serdes_private *priv;
  2180. struct phy_provider *provider;
  2181. struct resource *iores;
  2182. void __iomem *iomem;
  2183. unsigned long clock;
  2184. struct clk *clk;
  2185. int idx;
  2186. int err;
  2187. if (!np && !pdev->dev.platform_data)
  2188. return -ENODEV;
  2189. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  2190. if (!priv)
  2191. return -ENOMEM;
  2192. platform_set_drvdata(pdev, priv);
  2193. priv->dev = &pdev->dev;
  2194. /* Get coreclock */
  2195. clk = devm_clk_get(priv->dev, NULL);
  2196. if (IS_ERR(clk)) {
  2197. dev_err(priv->dev, "Failed to get coreclock\n");
  2198. return PTR_ERR(clk);
  2199. }
  2200. clock = clk_get_rate(clk);
  2201. if (clock == 0) {
  2202. dev_err(priv->dev, "Invalid coreclock %lu\n", clock);
  2203. return -EINVAL;
  2204. }
  2205. priv->coreclock = clock;
  2206. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2207. if (!iores) {
  2208. dev_err(priv->dev, "Invalid resource\n");
  2209. return -EINVAL;
  2210. }
  2211. iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores));
  2212. if (!iomem) {
  2213. dev_err(priv->dev, "Unable to get serdes registers: %s\n",
  2214. iores->name);
  2215. return -ENOMEM;
  2216. }
  2217. for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) {
  2218. struct sparx5_serdes_io_resource *iomap = &sparx5_serdes_iomap[idx];
  2219. priv->regs[iomap->id] = iomem + iomap->offset;
  2220. }
  2221. for (idx = 0; idx < SPX5_SERDES_MAX; idx++) {
  2222. err = sparx5_phy_create(priv, idx, &priv->phys[idx]);
  2223. if (err)
  2224. return err;
  2225. }
  2226. provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate);
  2227. return PTR_ERR_OR_ZERO(provider);
  2228. }
  2229. static const struct of_device_id sparx5_serdes_match[] = {
  2230. { .compatible = "microchip,sparx5-serdes" },
  2231. { }
  2232. };
  2233. MODULE_DEVICE_TABLE(of, sparx5_serdes_match);
  2234. static struct platform_driver sparx5_serdes_driver = {
  2235. .probe = sparx5_serdes_probe,
  2236. .driver = {
  2237. .name = "sparx5-serdes",
  2238. .of_match_table = sparx5_serdes_match,
  2239. },
  2240. };
  2241. module_platform_driver(sparx5_serdes_driver);
  2242. MODULE_DESCRIPTION("Microchip Sparx5 switch serdes driver");
  2243. MODULE_AUTHOR("Steen Hegelund <[email protected]>");
  2244. MODULE_LICENSE("GPL v2");