phy-hi3670-usb3.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform
  4. *
  5. * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd.
  6. * http://www.huawei.com
  7. *
  8. * Authors: Yu Chen <[email protected]>
  9. */
  10. #include <linux/bitfield.h>
  11. #include <linux/clk.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/module.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #define SCTRL_SCDEEPSLEEPED (0x0)
  19. #define USB_CLK_SELECTED BIT(20)
  20. #define PERI_CRG_PEREN0 (0x00)
  21. #define PERI_CRG_PERDIS0 (0x04)
  22. #define PERI_CRG_PEREN4 (0x40)
  23. #define PERI_CRG_PERDIS4 (0x44)
  24. #define PERI_CRG_PERRSTEN4 (0x90)
  25. #define PERI_CRG_PERRSTDIS4 (0x94)
  26. #define PERI_CRG_ISODIS (0x148)
  27. #define PERI_CRG_PEREN6 (0x410)
  28. #define PERI_CRG_PERDIS6 (0x414)
  29. #define USB_REFCLK_ISO_EN BIT(25)
  30. #define GT_CLK_USB2PHY_REF BIT(19)
  31. #define PCTRL_PERI_CTRL3 (0x10)
  32. #define PCTRL_PERI_CTRL3_MSK_START (16)
  33. #define USB_TCXO_EN BIT(1)
  34. #define PCTRL_PERI_CTRL24 (0x64)
  35. #define SC_CLK_USB3PHY_3MUX1_SEL BIT(25)
  36. #define USB3OTG_CTRL0 (0x00)
  37. #define USB3OTG_CTRL3 (0x0c)
  38. #define USB3OTG_CTRL4 (0x10)
  39. #define USB3OTG_CTRL5 (0x14)
  40. #define USB3OTG_CTRL7 (0x1c)
  41. #define USB_MISC_CFG50 (0x50)
  42. #define USB_MISC_CFG54 (0x54)
  43. #define USB_MISC_CFG58 (0x58)
  44. #define USB_MISC_CFG5C (0x5c)
  45. #define USB_MISC_CFGA0 (0xa0)
  46. #define TCA_CLK_RST (0x200)
  47. #define TCA_INTR_EN (0x204)
  48. #define TCA_INTR_STS (0x208)
  49. #define TCA_GCFG (0x210)
  50. #define TCA_TCPC (0x214)
  51. #define TCA_SYSMODE_CFG (0x218)
  52. #define TCA_VBUS_CTRL (0x240)
  53. #define CTRL0_USB3_VBUSVLD BIT(7)
  54. #define CTRL0_USB3_VBUSVLD_SEL BIT(6)
  55. #define CTRL3_USB2_VBUSVLDEXT0 BIT(6)
  56. #define CTRL3_USB2_VBUSVLDEXTSEL0 BIT(5)
  57. #define CTRL5_USB2_SIDDQ BIT(0)
  58. #define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3)
  59. #define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3))
  60. #define CTRL7_USB2_REFCLKSEL_PAD BIT(4)
  61. #define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23)
  62. #define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16)
  63. #define CFG54_USB3PHY_REF_USE_PAD BIT(12)
  64. #define CFG54_PHY0_PMA_PWR_STABLE BIT(11)
  65. #define CFG54_PHY0_PCS_PWR_STABLE BIT(9)
  66. #define CFG54_USB31PHY_CR_ACK BIT(7)
  67. #define CFG54_USB31PHY_CR_WR_EN BIT(5)
  68. #define CFG54_USB31PHY_CR_SEL BIT(4)
  69. #define CFG54_USB31PHY_CR_RD_EN BIT(3)
  70. #define CFG54_USB31PHY_CR_CLK BIT(2)
  71. #define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1)
  72. #define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16)
  73. #define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1)
  74. #define CFGA0_VAUX_RESET BIT(9)
  75. #define CFGA0_USB31C_RESET BIT(8)
  76. #define CFGA0_USB2PHY_REFCLK_SELECT BIT(4)
  77. #define CFGA0_USB3PHY_RESET BIT(1)
  78. #define CFGA0_USB2PHY_POR BIT(0)
  79. #define INTR_EN_XA_TIMEOUT_EVT_EN BIT(1)
  80. #define INTR_EN_XA_ACK_EVT_EN BIT(0)
  81. #define CLK_RST_TCA_REF_CLK_EN BIT(1)
  82. #define CLK_RST_SUSPEND_CLK_EN BIT(0)
  83. #define GCFG_ROLE_HSTDEV BIT(4)
  84. #define GCFG_OP_MODE GENMASK(1, 0)
  85. #define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0)
  86. #define TCPC_VALID BIT(4)
  87. #define TCPC_LOW_POWER_EN BIT(3)
  88. #define TCPC_MUX_CONTROL_MASK GENMASK(1, 0)
  89. #define TCPC_MUX_CONTROL_USB31 BIT(0)
  90. #define SYSMODE_CFG_TYPEC_DISABLE BIT(3)
  91. #define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2)
  92. #define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0)
  93. #define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4)
  94. #define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5)
  95. #define TX_VBOOST_LVL_REG (0xf)
  96. #define TX_VBOOST_LVL_START (6)
  97. #define TX_VBOOST_LVL_ENABLE BIT(9)
  98. struct hi3670_priv {
  99. struct device *dev;
  100. struct regmap *peri_crg;
  101. struct regmap *pctrl;
  102. struct regmap *sctrl;
  103. struct regmap *usb31misc;
  104. u32 eye_diagram_param;
  105. u32 tx_vboost_lvl;
  106. u32 peri_crg_offset;
  107. u32 pctrl_offset;
  108. u32 usb31misc_offset;
  109. };
  110. static int hi3670_phy_cr_clk(struct regmap *usb31misc)
  111. {
  112. int ret;
  113. /* Clock up */
  114. ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
  115. CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK);
  116. if (ret)
  117. return ret;
  118. /* Clock down */
  119. return regmap_update_bits(usb31misc, USB_MISC_CFG54,
  120. CFG54_USB31PHY_CR_CLK, 0);
  121. }
  122. static int hi3670_phy_cr_set_sel(struct regmap *usb31misc)
  123. {
  124. return regmap_update_bits(usb31misc, USB_MISC_CFG54,
  125. CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL);
  126. }
  127. static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction)
  128. {
  129. int ret, reg;
  130. if (direction)
  131. reg = CFG54_USB31PHY_CR_WR_EN;
  132. else
  133. reg = CFG54_USB31PHY_CR_RD_EN;
  134. ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg);
  135. if (ret)
  136. return ret;
  137. ret = hi3670_phy_cr_clk(usb31misc);
  138. if (ret)
  139. return ret;
  140. return regmap_update_bits(usb31misc, USB_MISC_CFG54,
  141. CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0);
  142. }
  143. static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc)
  144. {
  145. u32 reg;
  146. int retry = 10;
  147. int ret;
  148. while (retry-- > 0) {
  149. ret = regmap_read(usb31misc, USB_MISC_CFG54, &reg);
  150. if (ret)
  151. return ret;
  152. if ((reg & CFG54_USB31PHY_CR_ACK) == CFG54_USB31PHY_CR_ACK)
  153. return 0;
  154. ret = hi3670_phy_cr_clk(usb31misc);
  155. if (ret)
  156. return ret;
  157. usleep_range(10, 20);
  158. }
  159. return -ETIMEDOUT;
  160. }
  161. static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr)
  162. {
  163. u32 reg;
  164. int ret;
  165. ret = regmap_read(usb31misc, USB_MISC_CFG54, &reg);
  166. if (ret)
  167. return ret;
  168. reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr);
  169. return regmap_update_bits(usb31misc, USB_MISC_CFG54,
  170. CFG54_USB31PHY_CR_ADDR_MASK, reg);
  171. }
  172. static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val)
  173. {
  174. int reg, i, ret;
  175. for (i = 0; i < 100; i++) {
  176. ret = hi3670_phy_cr_clk(usb31misc);
  177. if (ret)
  178. return ret;
  179. }
  180. ret = hi3670_phy_cr_set_sel(usb31misc);
  181. if (ret)
  182. return ret;
  183. ret = hi3670_phy_cr_set_addr(usb31misc, addr);
  184. if (ret)
  185. return ret;
  186. ret = hi3670_phy_cr_start(usb31misc, 0);
  187. if (ret)
  188. return ret;
  189. ret = hi3670_phy_cr_wait_ack(usb31misc);
  190. if (ret)
  191. return ret;
  192. ret = regmap_read(usb31misc, USB_MISC_CFG58, &reg);
  193. if (ret)
  194. return ret;
  195. *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg);
  196. return 0;
  197. }
  198. static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val)
  199. {
  200. int i;
  201. int ret;
  202. for (i = 0; i < 100; i++) {
  203. ret = hi3670_phy_cr_clk(usb31misc);
  204. if (ret)
  205. return ret;
  206. }
  207. ret = hi3670_phy_cr_set_sel(usb31misc);
  208. if (ret)
  209. return ret;
  210. ret = hi3670_phy_cr_set_addr(usb31misc, addr);
  211. if (ret)
  212. return ret;
  213. ret = regmap_write(usb31misc, USB_MISC_CFG58,
  214. FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val));
  215. if (ret)
  216. return ret;
  217. ret = hi3670_phy_cr_start(usb31misc, 1);
  218. if (ret)
  219. return ret;
  220. return hi3670_phy_cr_wait_ack(usb31misc);
  221. }
  222. static int hi3670_phy_set_params(struct hi3670_priv *priv)
  223. {
  224. u32 reg;
  225. int ret;
  226. int retry = 3;
  227. ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4,
  228. priv->eye_diagram_param);
  229. if (ret) {
  230. dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n");
  231. return ret;
  232. }
  233. while (retry-- > 0) {
  234. ret = hi3670_phy_cr_read(priv->usb31misc,
  235. TX_VBOOST_LVL_REG, &reg);
  236. if (!ret)
  237. break;
  238. if (ret != -ETIMEDOUT) {
  239. dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n");
  240. return ret;
  241. }
  242. }
  243. if (ret)
  244. return ret;
  245. reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START));
  246. ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg);
  247. if (ret)
  248. dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n");
  249. return ret;
  250. }
  251. static bool hi3670_is_abbclk_selected(struct hi3670_priv *priv)
  252. {
  253. u32 reg;
  254. if (!priv->sctrl) {
  255. dev_err(priv->dev, "priv->sctrl is null!\n");
  256. return false;
  257. }
  258. if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, &reg)) {
  259. dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n");
  260. return false;
  261. }
  262. if ((reg & USB_CLK_SELECTED) == 0)
  263. return false;
  264. return true;
  265. }
  266. static int hi3670_config_phy_clock(struct hi3670_priv *priv)
  267. {
  268. u32 val, mask;
  269. int ret;
  270. if (!hi3670_is_abbclk_selected(priv)) {
  271. /* usb refclk iso disable */
  272. ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS,
  273. USB_REFCLK_ISO_EN);
  274. if (ret)
  275. goto out;
  276. /* enable usb_tcxo_en */
  277. ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3,
  278. USB_TCXO_EN |
  279. (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START));
  280. /* select usbphy clk from abb */
  281. mask = SC_CLK_USB3PHY_3MUX1_SEL;
  282. ret = regmap_update_bits(priv->pctrl,
  283. PCTRL_PERI_CTRL24, mask, 0);
  284. if (ret)
  285. goto out;
  286. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0,
  287. CFGA0_USB2PHY_REFCLK_SELECT, 0);
  288. if (ret)
  289. goto out;
  290. ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val);
  291. if (ret)
  292. goto out;
  293. val &= ~CTRL7_USB2_REFCLKSEL_MASK;
  294. val |= CTRL7_USB2_REFCLKSEL_ABB;
  295. ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val);
  296. if (ret)
  297. goto out;
  298. return 0;
  299. }
  300. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54,
  301. CFG54_USB3PHY_REF_USE_PAD,
  302. CFG54_USB3PHY_REF_USE_PAD);
  303. if (ret)
  304. goto out;
  305. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0,
  306. CFGA0_USB2PHY_REFCLK_SELECT,
  307. CFGA0_USB2PHY_REFCLK_SELECT);
  308. if (ret)
  309. goto out;
  310. ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val);
  311. if (ret)
  312. goto out;
  313. val &= ~CTRL7_USB2_REFCLKSEL_MASK;
  314. val |= CTRL7_USB2_REFCLKSEL_PAD;
  315. ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val);
  316. if (ret)
  317. goto out;
  318. ret = regmap_write(priv->peri_crg,
  319. PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF);
  320. if (ret)
  321. goto out;
  322. return 0;
  323. out:
  324. dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret);
  325. return ret;
  326. }
  327. static int hi3670_config_tca(struct hi3670_priv *priv)
  328. {
  329. u32 val, mask;
  330. int ret;
  331. ret = regmap_write(priv->usb31misc, TCA_INTR_STS, 0xffff);
  332. if (ret)
  333. goto out;
  334. ret = regmap_write(priv->usb31misc, TCA_INTR_EN,
  335. INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN);
  336. if (ret)
  337. goto out;
  338. mask = CLK_RST_TCA_REF_CLK_EN | CLK_RST_SUSPEND_CLK_EN;
  339. ret = regmap_update_bits(priv->usb31misc, TCA_CLK_RST, mask, 0);
  340. if (ret)
  341. goto out;
  342. ret = regmap_update_bits(priv->usb31misc, TCA_GCFG,
  343. GCFG_ROLE_HSTDEV | GCFG_OP_MODE,
  344. GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE);
  345. if (ret)
  346. goto out;
  347. ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG,
  348. SYSMODE_CFG_TYPEC_DISABLE, 0);
  349. if (ret)
  350. goto out;
  351. ret = regmap_read(priv->usb31misc, TCA_TCPC, &val);
  352. if (ret)
  353. goto out;
  354. val &= ~(TCPC_VALID | TCPC_LOW_POWER_EN | TCPC_MUX_CONTROL_MASK);
  355. val |= (TCPC_VALID | TCPC_MUX_CONTROL_USB31);
  356. ret = regmap_write(priv->usb31misc, TCA_TCPC, val);
  357. if (ret)
  358. goto out;
  359. ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL,
  360. VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD);
  361. if (ret)
  362. goto out;
  363. return 0;
  364. out:
  365. dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret);
  366. return ret;
  367. }
  368. static int hi3670_phy_init(struct phy *phy)
  369. {
  370. struct hi3670_priv *priv = phy_get_drvdata(phy);
  371. u32 val;
  372. int ret;
  373. /* assert controller */
  374. val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET |
  375. CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR;
  376. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0);
  377. if (ret)
  378. goto out;
  379. ret = hi3670_config_phy_clock(priv);
  380. if (ret)
  381. goto out;
  382. /* Exit from IDDQ mode */
  383. ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5,
  384. CTRL5_USB2_SIDDQ, 0);
  385. if (ret)
  386. goto out;
  387. /* Release USB31 PHY out of TestPowerDown mode */
  388. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50,
  389. CFG50_USB3_PHY_TEST_POWERDOWN, 0);
  390. if (ret)
  391. goto out;
  392. /* Deassert phy */
  393. val = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR;
  394. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val);
  395. if (ret)
  396. goto out;
  397. usleep_range(100, 120);
  398. /* Tell the PHY power is stable */
  399. val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE |
  400. CFG54_PHY0_PMA_PWR_STABLE;
  401. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54,
  402. val, val);
  403. if (ret)
  404. goto out;
  405. ret = hi3670_config_tca(priv);
  406. if (ret)
  407. goto out;
  408. /* Enable SSC */
  409. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C,
  410. CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN,
  411. CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN);
  412. if (ret)
  413. goto out;
  414. /* Deassert controller */
  415. val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET;
  416. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val);
  417. if (ret)
  418. goto out;
  419. usleep_range(100, 120);
  420. /* Set fake vbus valid signal */
  421. val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL;
  422. ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL0, val, val);
  423. if (ret)
  424. goto out;
  425. val = CTRL3_USB2_VBUSVLDEXT0 | CTRL3_USB2_VBUSVLDEXTSEL0;
  426. ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL3, val, val);
  427. if (ret)
  428. goto out;
  429. usleep_range(100, 120);
  430. ret = hi3670_phy_set_params(priv);
  431. if (ret)
  432. goto out;
  433. return 0;
  434. out:
  435. dev_err(priv->dev, "failed to init phy ret: %d\n", ret);
  436. return ret;
  437. }
  438. static int hi3670_phy_exit(struct phy *phy)
  439. {
  440. struct hi3670_priv *priv = phy_get_drvdata(phy);
  441. u32 mask;
  442. int ret;
  443. /* Assert phy */
  444. mask = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR;
  445. ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, mask, 0);
  446. if (ret)
  447. goto out;
  448. if (!hi3670_is_abbclk_selected(priv)) {
  449. /* disable usb_tcxo_en */
  450. ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3,
  451. USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START);
  452. } else {
  453. ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6,
  454. GT_CLK_USB2PHY_REF);
  455. if (ret)
  456. goto out;
  457. }
  458. return 0;
  459. out:
  460. dev_err(priv->dev, "failed to exit phy ret: %d\n", ret);
  461. return ret;
  462. }
  463. static const struct phy_ops hi3670_phy_ops = {
  464. .init = hi3670_phy_init,
  465. .exit = hi3670_phy_exit,
  466. .owner = THIS_MODULE,
  467. };
  468. static int hi3670_phy_probe(struct platform_device *pdev)
  469. {
  470. struct phy_provider *phy_provider;
  471. struct device *dev = &pdev->dev;
  472. struct phy *phy;
  473. struct hi3670_priv *priv;
  474. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  475. if (!priv)
  476. return -ENOMEM;
  477. priv->dev = dev;
  478. priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node,
  479. "hisilicon,pericrg-syscon");
  480. if (IS_ERR(priv->peri_crg)) {
  481. dev_err(dev, "no hisilicon,pericrg-syscon\n");
  482. return PTR_ERR(priv->peri_crg);
  483. }
  484. priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
  485. "hisilicon,pctrl-syscon");
  486. if (IS_ERR(priv->pctrl)) {
  487. dev_err(dev, "no hisilicon,pctrl-syscon\n");
  488. return PTR_ERR(priv->pctrl);
  489. }
  490. priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
  491. "hisilicon,sctrl-syscon");
  492. if (IS_ERR(priv->sctrl)) {
  493. dev_err(dev, "no hisilicon,sctrl-syscon\n");
  494. return PTR_ERR(priv->sctrl);
  495. }
  496. /* node of hi3670 phy is a sub-node of usb3_otg_bc */
  497. priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node);
  498. if (IS_ERR(priv->usb31misc)) {
  499. dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n");
  500. return PTR_ERR(priv->usb31misc);
  501. }
  502. if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param",
  503. &priv->eye_diagram_param))
  504. priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM;
  505. if (of_property_read_u32(dev->of_node, "hisilicon,tx-vboost-lvl",
  506. &priv->tx_vboost_lvl))
  507. priv->tx_vboost_lvl = KIRIN970_USB_DEFAULT_PHY_VBOOST;
  508. phy = devm_phy_create(dev, NULL, &hi3670_phy_ops);
  509. if (IS_ERR(phy))
  510. return PTR_ERR(phy);
  511. phy_set_drvdata(phy, priv);
  512. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  513. return PTR_ERR_OR_ZERO(phy_provider);
  514. }
  515. static const struct of_device_id hi3670_phy_of_match[] = {
  516. { .compatible = "hisilicon,hi3670-usb-phy" },
  517. { },
  518. };
  519. MODULE_DEVICE_TABLE(of, hi3670_phy_of_match);
  520. static struct platform_driver hi3670_phy_driver = {
  521. .probe = hi3670_phy_probe,
  522. .driver = {
  523. .name = "hi3670-usb-phy",
  524. .of_match_table = hi3670_phy_of_match,
  525. }
  526. };
  527. module_platform_driver(hi3670_phy_driver);
  528. MODULE_AUTHOR("Yu Chen <[email protected]>");
  529. MODULE_LICENSE("GPL v2");
  530. MODULE_DESCRIPTION("Hilisicon Kirin970 USB31 PHY Driver");