phy-hi3670-pcie.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe phy driver for Kirin 970
  4. *
  5. * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
  6. * https://www.huawei.com
  7. * Copyright (C) 2021 Huawei Technologies Co., Ltd.
  8. * https://www.huawei.com
  9. *
  10. * Authors:
  11. * Mauro Carvalho Chehab <[email protected]>
  12. * Manivannan Sadhasivam <[email protected]>
  13. *
  14. * Based on:
  15. * https://lore.kernel.org/lkml/4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org/
  16. */
  17. #include <linux/bitfield.h>
  18. #include <linux/clk.h>
  19. #include <linux/gpio.h>
  20. #include <linux/kernel.h>
  21. #include <linux/mfd/syscon.h>
  22. #include <linux/module.h>
  23. #include <linux/of_gpio.h>
  24. #include <linux/phy/phy.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/regmap.h>
  27. #define AXI_CLK_FREQ 207500000
  28. #define REF_CLK_FREQ 100000000
  29. /* PCIe CTRL registers */
  30. #define SOC_PCIECTRL_CTRL7_ADDR 0x01c
  31. #define SOC_PCIECTRL_CTRL12_ADDR 0x030
  32. #define SOC_PCIECTRL_CTRL20_ADDR 0x050
  33. #define SOC_PCIECTRL_CTRL21_ADDR 0x054
  34. #define PCIE_OUTPUT_PULL_BITS GENMASK(3, 0)
  35. #define SOC_PCIECTRL_CTRL20_2P_MEM_CTRL 0x02605550
  36. #define SOC_PCIECTRL_CTRL21_DEFAULT 0x20000070
  37. #define PCIE_PULL_UP_SYS_AUX_PWR_DET BIT(10)
  38. #define PCIE_OUTPUT_PULL_DOWN BIT(1)
  39. /* PCIe PHY registers */
  40. #define SOC_PCIEPHY_CTRL0_ADDR 0x000
  41. #define SOC_PCIEPHY_CTRL1_ADDR 0x004
  42. #define SOC_PCIEPHY_CTRL38_ADDR 0x0098
  43. #define SOC_PCIEPHY_STATE0_ADDR 0x400
  44. #define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 0xc004
  45. #define SUP_DIG_LVL_OVRD_IN 0x003c
  46. #define LANEN_DIG_ASIC_TX_OVRD_IN_1 0x4008
  47. #define LANEN_DIG_ASIC_TX_OVRD_IN_2 0x400c
  48. #define PCIEPHY_RESET_BIT BIT(17)
  49. #define PCIEPHY_PIPE_LINE0_RESET_BIT BIT(19)
  50. #define PCIE_TXDETECT_RX_FAIL BIT(2)
  51. #define PCIE_CLK_SOURCE BIT(8)
  52. #define PCIE_IS_CLOCK_STABLE BIT(19)
  53. #define PCIE_PULL_DOWN_PHY_TEST_POWERDOWN BIT(22)
  54. #define PCIE_DEASSERT_CONTROLLER_PERST BIT(2)
  55. #define EYEPARAM_NOCFG 0xffffffff
  56. #define EYE_PARM0_MASK GENMASK(8, 6)
  57. #define EYE_PARM1_MASK GENMASK(11, 8)
  58. #define EYE_PARM2_MASK GENMASK(5, 0)
  59. #define EYE_PARM3_MASK GENMASK(12, 7)
  60. #define EYE_PARM4_MASK GENMASK(14, 9)
  61. #define EYE_PARM0_EN BIT(9)
  62. #define EYE_PARM1_EN BIT(12)
  63. #define EYE_PARM2_EN BIT(6)
  64. #define EYE_PARM3_EN BIT(13)
  65. #define EYE_PARM4_EN BIT(15)
  66. /* hi3670 pciephy register */
  67. #define APB_PHY_START_ADDR 0x40000
  68. #define SOC_PCIEPHY_MMC1PLL_CTRL1 0xc04
  69. #define SOC_PCIEPHY_MMC1PLL_CTRL16 0xC40
  70. #define SOC_PCIEPHY_MMC1PLL_CTRL17 0xC44
  71. #define SOC_PCIEPHY_MMC1PLL_CTRL20 0xC50
  72. #define SOC_PCIEPHY_MMC1PLL_CTRL21 0xC54
  73. #define SOC_PCIEPHY_MMC1PLL_STAT0 0xE00
  74. #define CRGPERIPH_PEREN12 0x470
  75. #define CRGPERIPH_PERDIS12 0x474
  76. #define CRGPERIPH_PCIECTRL0 0x800
  77. #define PCIE_FNPLL_FBDIV_MASK GENMASK(27, 16)
  78. #define PCIE_FNPLL_FRACDIV_MASK GENMASK(23, 0)
  79. #define PCIE_FNPLL_POSTDIV1_MASK GENMASK(10, 8)
  80. #define PCIE_FNPLL_POSTDIV2_MASK GENMASK(14, 12)
  81. #define PCIE_FNPLL_PLL_MODE_MASK BIT(25)
  82. #define PCIE_FNPLL_DLL_EN BIT(27)
  83. #define PCIE_FNPLL_FBDIV 0xd0
  84. #define PCIE_FNPLL_FRACDIV 0x555555
  85. #define PCIE_FNPLL_POSTDIV1 0x5
  86. #define PCIE_FNPLL_POSTDIV2 0x4
  87. #define PCIE_FNPLL_PLL_MODE 0x0
  88. #define PCIE_PHY_MMC1PLL 0x20
  89. #define PCIE_PHY_CHOOSE_FNPLL BIT(27)
  90. #define PCIE_PHY_MMC1PLL_DISABLE BIT(0)
  91. #define PCIE_PHY_PCIEPL_BP BIT(16)
  92. /* define ie,oe cfg */
  93. #define IO_OE_HARD_GT_MODE BIT(1)
  94. #define IO_IE_EN_HARD_BYPASS BIT(27)
  95. #define IO_OE_EN_HARD_BYPASS BIT(11)
  96. #define IO_HARD_CTRL_DEBOUNCE_BYPASS BIT(10)
  97. #define IO_OE_GT_MODE BIT(8)
  98. #define DEBOUNCE_WAITCFG_IN GENMASK(23, 20)
  99. #define DEBOUNCE_WAITCFG_OUT GENMASK(16, 13)
  100. #define IO_HP_DEBOUNCE_GT (BIT(12) | BIT(15))
  101. #define IO_PHYREF_SOFT_GT_MODE BIT(14)
  102. #define IO_REF_SOFT_GT_MODE BIT(13)
  103. #define IO_REF_HARD_GT_MODE BIT(0)
  104. /* noc power domain */
  105. #define NOC_POWER_IDLEREQ_1 0x38c
  106. #define NOC_POWER_IDLE_1 0x394
  107. #define NOC_PW_MASK 0x10000
  108. #define NOC_PW_SET_BIT 0x1
  109. #define NUM_EYEPARAM 5
  110. /* info located in sysctrl */
  111. #define SCTRL_PCIE_CMOS_OFFSET 0x60
  112. #define SCTRL_PCIE_CMOS_BIT 0x10
  113. #define SCTRL_PCIE_ISO_OFFSET 0x44
  114. #define SCTRL_PCIE_ISO_BIT 0x30
  115. #define SCTRL_PCIE_HPCLK_OFFSET 0x190
  116. #define SCTRL_PCIE_HPCLK_BIT 0x184000
  117. #define SCTRL_PCIE_OE_OFFSET 0x14a
  118. #define PCIE_DEBOUNCE_PARAM 0xf0f400
  119. #define PCIE_OE_BYPASS GENMASK(29, 28)
  120. /* peri_crg ctrl */
  121. #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
  122. #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
  123. #define FNPLL_HAS_LOCKED BIT(4)
  124. /* Time for delay */
  125. #define TIME_CMOS_MIN 100
  126. #define TIME_CMOS_MAX 105
  127. #define PIPE_CLK_STABLE_TIME 100
  128. #define PLL_CTRL_WAIT_TIME 200
  129. #define NOC_POWER_TIME 100
  130. struct hi3670_pcie_phy {
  131. struct device *dev;
  132. void __iomem *base;
  133. struct regmap *apb;
  134. struct regmap *crgctrl;
  135. struct regmap *sysctrl;
  136. struct regmap *pmctrl;
  137. struct clk *apb_sys_clk;
  138. struct clk *apb_phy_clk;
  139. struct clk *phy_ref_clk;
  140. struct clk *aclk;
  141. struct clk *aux_clk;
  142. u32 eye_param[NUM_EYEPARAM];
  143. };
  144. /* Registers in PCIePHY */
  145. static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
  146. u32 reg)
  147. {
  148. writel(val, phy->base + APB_PHY_START_ADDR + reg);
  149. }
  150. static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
  151. {
  152. return readl(phy->base + APB_PHY_START_ADDR + reg);
  153. }
  154. static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
  155. u32 val, u32 mask, u32 reg)
  156. {
  157. u32 regval;
  158. regval = hi3670_apb_phy_readl(phy, reg);
  159. regval &= ~mask;
  160. regval |= val;
  161. hi3670_apb_phy_writel(phy, regval, reg);
  162. }
  163. static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
  164. u32 val, u32 reg)
  165. {
  166. writel(val, phy->base + reg);
  167. }
  168. static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
  169. u32 reg)
  170. {
  171. return readl(phy->base + reg);
  172. }
  173. static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
  174. {
  175. u32 val;
  176. regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
  177. val |= PCIE_DEBOUNCE_PARAM;
  178. if (enable)
  179. val &= ~PCIE_OE_BYPASS;
  180. else
  181. val |= PCIE_OE_BYPASS;
  182. regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
  183. }
  184. static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
  185. {
  186. struct device *dev = phy->dev;
  187. struct device_node *np;
  188. int ret, i;
  189. np = dev->of_node;
  190. ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
  191. phy->eye_param, NUM_EYEPARAM);
  192. if (!ret)
  193. return;
  194. /* There's no optional eye_param property. Set array to default */
  195. for (i = 0; i < NUM_EYEPARAM; i++)
  196. phy->eye_param[i] = EYEPARAM_NOCFG;
  197. }
  198. static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
  199. {
  200. u32 val;
  201. val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
  202. if (phy->eye_param[1] != EYEPARAM_NOCFG) {
  203. val &= ~EYE_PARM1_MASK;
  204. val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
  205. val |= EYE_PARM1_EN;
  206. }
  207. kirin_apb_natural_phy_writel(phy, val,
  208. RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
  209. val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
  210. val &= ~(EYE_PARM2_MASK | EYE_PARM3_MASK);
  211. if (phy->eye_param[2] != EYEPARAM_NOCFG) {
  212. val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
  213. val |= EYE_PARM2_EN;
  214. }
  215. if (phy->eye_param[3] != EYEPARAM_NOCFG) {
  216. val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
  217. val |= EYE_PARM3_EN;
  218. }
  219. kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
  220. val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
  221. if (phy->eye_param[0] != EYEPARAM_NOCFG) {
  222. val &= ~EYE_PARM0_MASK;
  223. val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
  224. val |= EYE_PARM0_EN;
  225. }
  226. kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
  227. val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
  228. if (phy->eye_param[4] != EYEPARAM_NOCFG) {
  229. val &= ~EYE_PARM4_MASK;
  230. val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
  231. val |= EYE_PARM4_EN;
  232. }
  233. kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
  234. }
  235. static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)
  236. {
  237. u32 val;
  238. /* change 2p mem_ctrl */
  239. regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,
  240. SOC_PCIECTRL_CTRL20_2P_MEM_CTRL);
  241. regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
  242. val |= PCIE_PULL_UP_SYS_AUX_PWR_DET;
  243. regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
  244. /* output, pull down */
  245. regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
  246. val &= ~PCIE_OUTPUT_PULL_BITS;
  247. val |= PCIE_OUTPUT_PULL_DOWN;
  248. regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
  249. /* Handle phy_reset and lane0_reset to HW */
  250. hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,
  251. PCIEPHY_PIPE_LINE0_RESET_BIT | PCIEPHY_RESET_BIT,
  252. SOC_PCIEPHY_CTRL1_ADDR);
  253. /* fix chip bug: TxDetectRx fail */
  254. hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,
  255. SOC_PCIEPHY_CTRL38_ADDR);
  256. }
  257. static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)
  258. {
  259. hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,
  260. SOC_PCIEPHY_MMC1PLL_CTRL1);
  261. hi3670_apb_phy_updatel(phy,
  262. FIELD_PREP(PCIE_FNPLL_FBDIV_MASK, PCIE_FNPLL_FBDIV),
  263. PCIE_FNPLL_FBDIV_MASK,
  264. SOC_PCIEPHY_MMC1PLL_CTRL16);
  265. hi3670_apb_phy_updatel(phy,
  266. FIELD_PREP(PCIE_FNPLL_FRACDIV_MASK, PCIE_FNPLL_FRACDIV),
  267. PCIE_FNPLL_FRACDIV_MASK, SOC_PCIEPHY_MMC1PLL_CTRL17);
  268. hi3670_apb_phy_updatel(phy,
  269. PCIE_FNPLL_DLL_EN |
  270. FIELD_PREP(PCIE_FNPLL_POSTDIV1_MASK, PCIE_FNPLL_POSTDIV1) |
  271. FIELD_PREP(PCIE_FNPLL_POSTDIV2_MASK, PCIE_FNPLL_POSTDIV2) |
  272. FIELD_PREP(PCIE_FNPLL_PLL_MODE_MASK, PCIE_FNPLL_PLL_MODE),
  273. PCIE_FNPLL_POSTDIV1_MASK |
  274. PCIE_FNPLL_POSTDIV2_MASK |
  275. PCIE_FNPLL_PLL_MODE_MASK | PCIE_FNPLL_DLL_EN,
  276. SOC_PCIEPHY_MMC1PLL_CTRL20);
  277. hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,
  278. SOC_PCIEPHY_MMC1PLL_CTRL21);
  279. }
  280. static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
  281. {
  282. struct device *dev = phy->dev;
  283. u32 val;
  284. int time = PLL_CTRL_WAIT_TIME;
  285. if (enable) {
  286. /* pd = 0 */
  287. hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
  288. SOC_PCIEPHY_MMC1PLL_CTRL16);
  289. /* choose FNPLL */
  290. val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
  291. while (!(val & FNPLL_HAS_LOCKED)) {
  292. if (!time) {
  293. dev_err(dev, "wait for pll_lock timeout\n");
  294. return -EINVAL;
  295. }
  296. time--;
  297. udelay(1);
  298. val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
  299. }
  300. hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
  301. SOC_PCIEPHY_MMC1PLL_CTRL20);
  302. } else {
  303. hi3670_apb_phy_updatel(phy,
  304. PCIE_PHY_MMC1PLL_DISABLE,
  305. PCIE_PHY_MMC1PLL_DISABLE,
  306. SOC_PCIEPHY_MMC1PLL_CTRL16);
  307. hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
  308. PCIE_PHY_PCIEPL_BP,
  309. SOC_PCIEPHY_MMC1PLL_CTRL20);
  310. }
  311. return 0;
  312. }
  313. static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)
  314. {
  315. if (open)
  316. /* gt_clk_pcie_hp/gt_clk_pcie_debounce open */
  317. regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,
  318. IO_HP_DEBOUNCE_GT);
  319. else
  320. /* gt_clk_pcie_hp/gt_clk_pcie_debounce close */
  321. regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
  322. IO_HP_DEBOUNCE_GT);
  323. }
  324. static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)
  325. {
  326. unsigned int val;
  327. regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
  328. if (open)
  329. val &= ~IO_OE_HARD_GT_MODE; /* enable hard gt mode */
  330. else
  331. val |= IO_OE_HARD_GT_MODE; /* disable hard gt mode */
  332. regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
  333. /* disable soft gt mode */
  334. regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);
  335. }
  336. static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)
  337. {
  338. unsigned int val;
  339. regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
  340. /* set ie cfg */
  341. val |= IO_IE_EN_HARD_BYPASS;
  342. /* set oe cfg */
  343. val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS;
  344. /* set phy_debounce in&out time */
  345. val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT);
  346. /* select oe_gt_mode */
  347. val |= IO_OE_GT_MODE;
  348. if (en_flag)
  349. val &= ~IO_OE_EN_HARD_BYPASS;
  350. else
  351. val |= IO_OE_EN_HARD_BYPASS;
  352. regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
  353. }
  354. static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)
  355. {
  356. unsigned int val;
  357. if (open) {
  358. regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,
  359. SOC_PCIECTRL_CTRL21_DEFAULT);
  360. hi3670_pcie_oe_ctrl(phy, true);
  361. /* en hard gt mode */
  362. regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
  363. val &= ~IO_REF_HARD_GT_MODE;
  364. regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
  365. /* disable soft gt mode */
  366. regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
  367. IO_REF_SOFT_GT_MODE);
  368. } else {
  369. /* disable hard gt mode */
  370. regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
  371. val |= IO_REF_HARD_GT_MODE;
  372. regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
  373. /* disable soft gt mode */
  374. regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
  375. IO_REF_SOFT_GT_MODE);
  376. hi3670_pcie_oe_ctrl(phy, false);
  377. }
  378. }
  379. static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)
  380. {
  381. struct device *dev = phy->dev;
  382. int ret = 0;
  383. if (!clk_on)
  384. goto close_clocks;
  385. /* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */
  386. hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,
  387. SOC_PCIEPHY_CTRL1_ADDR);
  388. hi3670_pcie_pll_init(phy);
  389. ret = hi3670_pcie_pll_ctrl(phy, true);
  390. if (ret) {
  391. dev_err(dev, "Failed to enable pll\n");
  392. return -EINVAL;
  393. }
  394. hi3670_pcie_hp_debounce_gt(phy, true);
  395. hi3670_pcie_phyref_gt(phy, true);
  396. hi3670_pcie_ioref_gt(phy, true);
  397. ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);
  398. if (ret) {
  399. dev_err(dev, "Failed to set rate\n");
  400. goto close_clocks;
  401. }
  402. return 0;
  403. close_clocks:
  404. hi3670_pcie_ioref_gt(phy, false);
  405. hi3670_pcie_phyref_gt(phy, false);
  406. hi3670_pcie_hp_debounce_gt(phy, false);
  407. hi3670_pcie_pll_ctrl(phy, false);
  408. return ret;
  409. }
  410. static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)
  411. {
  412. struct device *dev = phy->dev;
  413. u32 val;
  414. u32 time = PIPE_CLK_STABLE_TIME;
  415. u32 pipe_clk_stable = PCIE_IS_CLOCK_STABLE;
  416. val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
  417. while (val & pipe_clk_stable) {
  418. mdelay(1);
  419. if (!time) {
  420. dev_err(dev, "PIPE clk is not stable\n");
  421. return false;
  422. }
  423. time--;
  424. val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
  425. }
  426. return true;
  427. }
  428. static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
  429. {
  430. struct device *dev = phy->dev;
  431. u32 time = NOC_POWER_TIME;
  432. unsigned int val = NOC_PW_MASK;
  433. int rst;
  434. if (enable)
  435. val = NOC_PW_MASK | NOC_PW_SET_BIT;
  436. else
  437. val = NOC_PW_MASK;
  438. rst = enable ? 1 : 0;
  439. regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
  440. time = NOC_POWER_TIME;
  441. regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
  442. while ((val & NOC_PW_SET_BIT) != rst) {
  443. udelay(10);
  444. if (!time) {
  445. dev_err(dev, "Failed to reverse noc power-status\n");
  446. return -EINVAL;
  447. }
  448. time--;
  449. regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
  450. }
  451. return 0;
  452. }
  453. static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
  454. {
  455. struct device_node *pcie_port;
  456. struct device *dev = phy->dev;
  457. struct device *pcie_dev;
  458. pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");
  459. if (!pcie_port) {
  460. dev_err(dev, "no pcie node found in %s\n",
  461. dev->parent->of_node->full_name);
  462. return -ENODEV;
  463. }
  464. pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port);
  465. if (!pcie_dev) {
  466. dev_err(dev, "Didn't find pcie device\n");
  467. return -ENODEV;
  468. }
  469. /*
  470. * We might just use NULL instead of the APB name, as the
  471. * pcie-kirin currently registers directly just one regmap (although
  472. * the DWC driver register other regmaps).
  473. *
  474. * Yet, it sounds safer to warrant that it will be accessing the
  475. * right regmap. So, let's use the named version.
  476. */
  477. phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");
  478. if (!phy->apb) {
  479. dev_err(dev, "Failed to get APB regmap\n");
  480. return -ENODEV;
  481. }
  482. return 0;
  483. }
  484. static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)
  485. {
  486. int ret = 0;
  487. if (!enable)
  488. goto close_clk;
  489. ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
  490. if (ret)
  491. return ret;
  492. ret = clk_prepare_enable(phy->phy_ref_clk);
  493. if (ret)
  494. return ret;
  495. ret = clk_prepare_enable(phy->apb_sys_clk);
  496. if (ret)
  497. goto apb_sys_fail;
  498. ret = clk_prepare_enable(phy->apb_phy_clk);
  499. if (ret)
  500. goto apb_phy_fail;
  501. ret = clk_prepare_enable(phy->aclk);
  502. if (ret)
  503. goto aclk_fail;
  504. ret = clk_prepare_enable(phy->aux_clk);
  505. if (ret)
  506. goto aux_clk_fail;
  507. return 0;
  508. close_clk:
  509. clk_disable_unprepare(phy->aux_clk);
  510. aux_clk_fail:
  511. clk_disable_unprepare(phy->aclk);
  512. aclk_fail:
  513. clk_disable_unprepare(phy->apb_phy_clk);
  514. apb_phy_fail:
  515. clk_disable_unprepare(phy->apb_sys_clk);
  516. apb_sys_fail:
  517. clk_disable_unprepare(phy->phy_ref_clk);
  518. return ret;
  519. }
  520. static int hi3670_pcie_phy_init(struct phy *generic_phy)
  521. {
  522. struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
  523. int ret;
  524. /*
  525. * The code under hi3670_pcie_get_resources_from_pcie() need to
  526. * access the reset-gpios and the APB registers, both from the
  527. * pcie-kirin driver.
  528. *
  529. * The APB is obtained via the pcie driver's regmap
  530. * Such kind of resource can only be obtained during the PCIe
  531. * power_on sequence, as the code inside pcie-kirin needs to
  532. * be already probed, as it needs to register the APB regmap.
  533. */
  534. ret = hi3670_pcie_get_resources_from_pcie(phy);
  535. if (ret)
  536. return ret;
  537. return 0;
  538. }
  539. static int hi3670_pcie_phy_power_on(struct phy *generic_phy)
  540. {
  541. struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
  542. int val, ret;
  543. /* Power supply for Host */
  544. regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
  545. usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
  546. hi3670_pcie_phy_oe_enable(phy, true);
  547. ret = kirin_pcie_clk_ctrl(phy, true);
  548. if (ret)
  549. return ret;
  550. /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
  551. regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
  552. regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,
  553. CRGCTRL_PCIE_ASSERT_BIT);
  554. regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,
  555. SCTRL_PCIE_HPCLK_BIT);
  556. hi3670_pcie_natural_cfg(phy);
  557. ret = hi3670_pcie_allclk_ctrl(phy, true);
  558. if (ret)
  559. goto disable_clks;
  560. /* pull down phy_test_powerdown signal */
  561. hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,
  562. SOC_PCIEPHY_CTRL0_ADDR);
  563. /* deassert controller perst_n */
  564. regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
  565. val |= PCIE_DEASSERT_CONTROLLER_PERST;
  566. regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
  567. udelay(10);
  568. ret = is_pipe_clk_stable(phy);
  569. if (!ret)
  570. goto disable_clks;
  571. hi3670_pcie_set_eyeparam(phy);
  572. ret = hi3670_pcie_noc_power(phy, false);
  573. if (ret)
  574. goto disable_clks;
  575. return 0;
  576. disable_clks:
  577. kirin_pcie_clk_ctrl(phy, false);
  578. return ret;
  579. }
  580. static int hi3670_pcie_phy_power_off(struct phy *generic_phy)
  581. {
  582. struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
  583. hi3670_pcie_phy_oe_enable(phy, false);
  584. hi3670_pcie_allclk_ctrl(phy, false);
  585. /* Drop power supply for Host */
  586. regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);
  587. /*
  588. * FIXME: The enabled clocks should be disabled here by calling
  589. * kirin_pcie_clk_ctrl(phy, false);
  590. * However, some clocks used at Kirin 970 should be marked as
  591. * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off
  592. * cause an Asynchronous SError interrupt, which produces panic().
  593. * While clk-hi3670 is not fixed, we cannot risk disabling clocks here.
  594. */
  595. return 0;
  596. }
  597. static const struct phy_ops hi3670_phy_ops = {
  598. .init = hi3670_pcie_phy_init,
  599. .power_on = hi3670_pcie_phy_power_on,
  600. .power_off = hi3670_pcie_phy_power_off,
  601. .owner = THIS_MODULE,
  602. };
  603. static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
  604. struct platform_device *pdev)
  605. {
  606. struct device *dev = &pdev->dev;
  607. /* syscon */
  608. phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");
  609. if (IS_ERR(phy->crgctrl))
  610. return PTR_ERR(phy->crgctrl);
  611. phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");
  612. if (IS_ERR(phy->sysctrl))
  613. return PTR_ERR(phy->sysctrl);
  614. phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
  615. if (IS_ERR(phy->pmctrl))
  616. return PTR_ERR(phy->pmctrl);
  617. /* clocks */
  618. phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
  619. if (IS_ERR(phy->phy_ref_clk))
  620. return PTR_ERR(phy->phy_ref_clk);
  621. phy->aux_clk = devm_clk_get(dev, "aux");
  622. if (IS_ERR(phy->aux_clk))
  623. return PTR_ERR(phy->aux_clk);
  624. phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");
  625. if (IS_ERR(phy->apb_phy_clk))
  626. return PTR_ERR(phy->apb_phy_clk);
  627. phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");
  628. if (IS_ERR(phy->apb_sys_clk))
  629. return PTR_ERR(phy->apb_sys_clk);
  630. phy->aclk = devm_clk_get(dev, "aclk");
  631. if (IS_ERR(phy->aclk))
  632. return PTR_ERR(phy->aclk);
  633. /* registers */
  634. phy->base = devm_platform_ioremap_resource(pdev, 0);
  635. if (IS_ERR(phy->base))
  636. return PTR_ERR(phy->base);
  637. hi3670_pcie_get_eyeparam(phy);
  638. return 0;
  639. }
  640. static int hi3670_pcie_phy_probe(struct platform_device *pdev)
  641. {
  642. struct phy_provider *phy_provider;
  643. struct device *dev = &pdev->dev;
  644. struct hi3670_pcie_phy *phy;
  645. struct phy *generic_phy;
  646. int ret;
  647. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  648. if (!phy)
  649. return -ENOMEM;
  650. phy->dev = dev;
  651. ret = hi3670_pcie_phy_get_resources(phy, pdev);
  652. if (ret)
  653. return ret;
  654. generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops);
  655. if (IS_ERR(generic_phy)) {
  656. dev_err(dev, "failed to create PHY\n");
  657. return PTR_ERR(generic_phy);
  658. }
  659. phy_set_drvdata(generic_phy, phy);
  660. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  661. return PTR_ERR_OR_ZERO(phy_provider);
  662. }
  663. static const struct of_device_id hi3670_pcie_phy_match[] = {
  664. {
  665. .compatible = "hisilicon,hi970-pcie-phy",
  666. },
  667. {},
  668. };
  669. static struct platform_driver hi3670_pcie_phy_driver = {
  670. .probe = hi3670_pcie_phy_probe,
  671. .driver = {
  672. .of_match_table = hi3670_pcie_phy_match,
  673. .name = "hi3670_pcie_phy",
  674. .suppress_bind_attrs = true,
  675. }
  676. };
  677. builtin_platform_driver(hi3670_pcie_phy_driver);
  678. MODULE_DEVICE_TABLE(of, hi3670_pcie_phy_match);
  679. MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");
  680. MODULE_AUTHOR("Mauro Carvalho Chehab <[email protected]>");
  681. MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
  682. MODULE_LICENSE("GPL v2");