phy-sun50i-usb3.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Allwinner sun50i(H6) USB 3.0 phy driver
  4. *
  5. * Copyright (C) 2017 Icenowy Zheng <[email protected]>
  6. *
  7. * Based on phy-sun9i-usb.c, which is:
  8. *
  9. * Copyright (C) 2014-2015 Chen-Yu Tsai <[email protected]>
  10. *
  11. * Based on code from Allwinner BSP, which is:
  12. *
  13. * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
  14. */
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/phy/phy.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/reset.h>
  22. /* Interface Status and Control Registers */
  23. #define SUNXI_ISCR 0x00
  24. #define SUNXI_PIPE_CLOCK_CONTROL 0x14
  25. #define SUNXI_PHY_TUNE_LOW 0x18
  26. #define SUNXI_PHY_TUNE_HIGH 0x1c
  27. #define SUNXI_PHY_EXTERNAL_CONTROL 0x20
  28. /* USB2.0 Interface Status and Control Register */
  29. #define SUNXI_ISCR_FORCE_VBUS (3 << 12)
  30. /* PIPE Clock Control Register */
  31. #define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
  32. /* PHY External Control Register */
  33. #define SUNXI_PEC_EXTERN_VBUS (3 << 1)
  34. #define SUNXI_PEC_SSC_EN (1 << 24)
  35. #define SUNXI_PEC_REF_SSP_EN (1 << 26)
  36. /* PHY Tune High Register */
  37. #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
  38. #define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
  39. #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
  40. #define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
  41. #define SUNXI_TX_SWING_FULL(n) ((n) << 6)
  42. #define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
  43. #define SUNXI_LOS_BIAS(n) ((n) << 3)
  44. #define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
  45. #define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
  46. #define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
  47. struct sun50i_usb3_phy {
  48. struct phy *phy;
  49. void __iomem *regs;
  50. struct reset_control *reset;
  51. struct clk *clk;
  52. };
  53. static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
  54. {
  55. u32 val;
  56. val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
  57. val |= SUNXI_PEC_EXTERN_VBUS;
  58. val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
  59. writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
  60. val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
  61. val |= SUNXI_PCC_PIPE_CLK_OPEN;
  62. writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
  63. val = readl(phy->regs + SUNXI_ISCR);
  64. val |= SUNXI_ISCR_FORCE_VBUS;
  65. writel(val, phy->regs + SUNXI_ISCR);
  66. /*
  67. * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
  68. * registers are directly taken from the BSP USB3 driver from
  69. * Allwiner.
  70. */
  71. writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
  72. val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
  73. val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
  74. SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
  75. SUNXI_TX_DEEMPH_3P5DB_MASK);
  76. val |= SUNXI_TXVBOOSTLVL(0x7);
  77. val |= SUNXI_LOS_BIAS(0x7);
  78. val |= SUNXI_TX_SWING_FULL(0x55);
  79. val |= SUNXI_TX_DEEMPH_6DB(0x20);
  80. val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
  81. writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
  82. }
  83. static int sun50i_usb3_phy_init(struct phy *_phy)
  84. {
  85. struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
  86. int ret;
  87. ret = clk_prepare_enable(phy->clk);
  88. if (ret)
  89. return ret;
  90. ret = reset_control_deassert(phy->reset);
  91. if (ret) {
  92. clk_disable_unprepare(phy->clk);
  93. return ret;
  94. }
  95. sun50i_usb3_phy_open(phy);
  96. return 0;
  97. }
  98. static int sun50i_usb3_phy_exit(struct phy *_phy)
  99. {
  100. struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
  101. reset_control_assert(phy->reset);
  102. clk_disable_unprepare(phy->clk);
  103. return 0;
  104. }
  105. static const struct phy_ops sun50i_usb3_phy_ops = {
  106. .init = sun50i_usb3_phy_init,
  107. .exit = sun50i_usb3_phy_exit,
  108. .owner = THIS_MODULE,
  109. };
  110. static int sun50i_usb3_phy_probe(struct platform_device *pdev)
  111. {
  112. struct sun50i_usb3_phy *phy;
  113. struct device *dev = &pdev->dev;
  114. struct phy_provider *phy_provider;
  115. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  116. if (!phy)
  117. return -ENOMEM;
  118. phy->clk = devm_clk_get(dev, NULL);
  119. if (IS_ERR(phy->clk)) {
  120. if (PTR_ERR(phy->clk) != -EPROBE_DEFER)
  121. dev_err(dev, "failed to get phy clock\n");
  122. return PTR_ERR(phy->clk);
  123. }
  124. phy->reset = devm_reset_control_get(dev, NULL);
  125. if (IS_ERR(phy->reset)) {
  126. dev_err(dev, "failed to get reset control\n");
  127. return PTR_ERR(phy->reset);
  128. }
  129. phy->regs = devm_platform_ioremap_resource(pdev, 0);
  130. if (IS_ERR(phy->regs))
  131. return PTR_ERR(phy->regs);
  132. phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
  133. if (IS_ERR(phy->phy)) {
  134. dev_err(dev, "failed to create PHY\n");
  135. return PTR_ERR(phy->phy);
  136. }
  137. phy_set_drvdata(phy->phy, phy);
  138. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  139. return PTR_ERR_OR_ZERO(phy_provider);
  140. }
  141. static const struct of_device_id sun50i_usb3_phy_of_match[] = {
  142. { .compatible = "allwinner,sun50i-h6-usb3-phy" },
  143. { },
  144. };
  145. MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
  146. static struct platform_driver sun50i_usb3_phy_driver = {
  147. .probe = sun50i_usb3_phy_probe,
  148. .driver = {
  149. .of_match_table = sun50i_usb3_phy_of_match,
  150. .name = "sun50i-usb3-phy",
  151. }
  152. };
  153. module_platform_driver(sun50i_usb3_phy_driver);
  154. MODULE_DESCRIPTION("Allwinner H6 USB 3.0 phy driver");
  155. MODULE_AUTHOR("Icenowy Zheng <[email protected]>");
  156. MODULE_LICENSE("GPL");