phy-sun4i-usb.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Allwinner sun4i USB phy driver
  4. *
  5. * Copyright (C) 2014-2015 Hans de Goede <[email protected]>
  6. *
  7. * Based on code from
  8. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  9. *
  10. * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
  11. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  12. * Author: Sylwester Nawrocki <[email protected]>
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/extcon-provider.h>
  18. #include <linux/gpio/consumer.h>
  19. #include <linux/io.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/mutex.h>
  24. #include <linux/of.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_device.h>
  27. #include <linux/of_gpio.h>
  28. #include <linux/phy/phy.h>
  29. #include <linux/phy/phy-sun4i-usb.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/power_supply.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/reset.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/usb/of.h>
  36. #include <linux/workqueue.h>
  37. #define REG_ISCR 0x00
  38. #define REG_PHYCTL_A10 0x04
  39. #define REG_PHYBIST 0x08
  40. #define REG_PHYTUNE 0x0c
  41. #define REG_PHYCTL_A33 0x10
  42. #define REG_PHY_OTGCTL 0x20
  43. #define REG_HCI_PHY_CTL 0x10
  44. #define PHYCTL_DATA BIT(7)
  45. #define OTGCTL_ROUTE_MUSB BIT(0)
  46. #define SUNXI_AHB_ICHR8_EN BIT(10)
  47. #define SUNXI_AHB_INCR4_BURST_EN BIT(9)
  48. #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
  49. #define SUNXI_ULPI_BYPASS_EN BIT(0)
  50. /* ISCR, Interface Status and Control bits */
  51. #define ISCR_ID_PULLUP_EN (1 << 17)
  52. #define ISCR_DPDM_PULLUP_EN (1 << 16)
  53. /* sunxi has the phy id/vbus pins not connected, so we use the force bits */
  54. #define ISCR_FORCE_ID_MASK (3 << 14)
  55. #define ISCR_FORCE_ID_LOW (2 << 14)
  56. #define ISCR_FORCE_ID_HIGH (3 << 14)
  57. #define ISCR_FORCE_VBUS_MASK (3 << 12)
  58. #define ISCR_FORCE_VBUS_LOW (2 << 12)
  59. #define ISCR_FORCE_VBUS_HIGH (3 << 12)
  60. /* Common Control Bits for Both PHYs */
  61. #define PHY_PLL_BW 0x03
  62. #define PHY_RES45_CAL_EN 0x0c
  63. /* Private Control Bits for Each PHY */
  64. #define PHY_TX_AMPLITUDE_TUNE 0x20
  65. #define PHY_TX_SLEWRATE_TUNE 0x22
  66. #define PHY_VBUSVALID_TH_SEL 0x25
  67. #define PHY_PULLUP_RES_SEL 0x27
  68. #define PHY_OTG_FUNC_EN 0x28
  69. #define PHY_VBUS_DET_EN 0x29
  70. #define PHY_DISCON_TH_SEL 0x2a
  71. #define PHY_SQUELCH_DETECT 0x3c
  72. /* A83T specific control bits for PHY0 */
  73. #define PHY_CTL_VBUSVLDEXT BIT(5)
  74. #define PHY_CTL_SIDDQ BIT(3)
  75. #define PHY_CTL_H3_SIDDQ BIT(1)
  76. /* A83T specific control bits for PHY2 HSIC */
  77. #define SUNXI_EHCI_HS_FORCE BIT(20)
  78. #define SUNXI_HSIC_CONNECT_DET BIT(17)
  79. #define SUNXI_HSIC_CONNECT_INT BIT(16)
  80. #define SUNXI_HSIC BIT(1)
  81. #define MAX_PHYS 4
  82. /*
  83. * Note do not raise the debounce time, we must report Vusb high within 100ms
  84. * otherwise we get Vbus errors
  85. */
  86. #define DEBOUNCE_TIME msecs_to_jiffies(50)
  87. #define POLL_TIME msecs_to_jiffies(250)
  88. enum sun4i_usb_phy_type {
  89. sun4i_a10_phy,
  90. sun6i_a31_phy,
  91. sun8i_a33_phy,
  92. sun8i_a83t_phy,
  93. sun8i_h3_phy,
  94. sun8i_r40_phy,
  95. sun8i_v3s_phy,
  96. sun50i_a64_phy,
  97. sun50i_h6_phy,
  98. };
  99. struct sun4i_usb_phy_cfg {
  100. int num_phys;
  101. int hsic_index;
  102. enum sun4i_usb_phy_type type;
  103. u32 disc_thresh;
  104. u32 hci_phy_ctl_clear;
  105. u8 phyctl_offset;
  106. bool dedicated_clocks;
  107. bool phy0_dual_route;
  108. bool needs_phy2_siddq;
  109. int missing_phys;
  110. };
  111. struct sun4i_usb_phy_data {
  112. void __iomem *base;
  113. const struct sun4i_usb_phy_cfg *cfg;
  114. enum usb_dr_mode dr_mode;
  115. spinlock_t reg_lock; /* guard access to phyctl reg */
  116. struct sun4i_usb_phy {
  117. struct phy *phy;
  118. void __iomem *pmu;
  119. struct regulator *vbus;
  120. struct reset_control *reset;
  121. struct clk *clk;
  122. struct clk *clk2;
  123. bool regulator_on;
  124. int index;
  125. } phys[MAX_PHYS];
  126. /* phy0 / otg related variables */
  127. struct extcon_dev *extcon;
  128. bool phy0_init;
  129. struct gpio_desc *id_det_gpio;
  130. struct gpio_desc *vbus_det_gpio;
  131. struct power_supply *vbus_power_supply;
  132. struct notifier_block vbus_power_nb;
  133. bool vbus_power_nb_registered;
  134. bool force_session_end;
  135. int id_det_irq;
  136. int vbus_det_irq;
  137. int id_det;
  138. int vbus_det;
  139. struct delayed_work detect;
  140. };
  141. #define to_sun4i_usb_phy_data(phy) \
  142. container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
  143. static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
  144. {
  145. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  146. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  147. u32 iscr;
  148. iscr = readl(data->base + REG_ISCR);
  149. iscr &= ~clr;
  150. iscr |= set;
  151. writel(iscr, data->base + REG_ISCR);
  152. }
  153. static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
  154. {
  155. if (val)
  156. val = ISCR_FORCE_ID_HIGH;
  157. else
  158. val = ISCR_FORCE_ID_LOW;
  159. sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val);
  160. }
  161. static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
  162. {
  163. if (val)
  164. val = ISCR_FORCE_VBUS_HIGH;
  165. else
  166. val = ISCR_FORCE_VBUS_LOW;
  167. sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val);
  168. }
  169. static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
  170. int len)
  171. {
  172. struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
  173. u32 temp, usbc_bit = BIT(phy->index * 2);
  174. void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
  175. unsigned long flags;
  176. int i;
  177. spin_lock_irqsave(&phy_data->reg_lock, flags);
  178. if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
  179. /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
  180. writel(0, phyctl);
  181. }
  182. for (i = 0; i < len; i++) {
  183. temp = readl(phyctl);
  184. /* clear the address portion */
  185. temp &= ~(0xff << 8);
  186. /* set the address */
  187. temp |= ((addr + i) << 8);
  188. writel(temp, phyctl);
  189. /* set the data bit and clear usbc bit*/
  190. temp = readb(phyctl);
  191. if (data & 0x1)
  192. temp |= PHYCTL_DATA;
  193. else
  194. temp &= ~PHYCTL_DATA;
  195. temp &= ~usbc_bit;
  196. writeb(temp, phyctl);
  197. /* pulse usbc_bit */
  198. temp = readb(phyctl);
  199. temp |= usbc_bit;
  200. writeb(temp, phyctl);
  201. temp = readb(phyctl);
  202. temp &= ~usbc_bit;
  203. writeb(temp, phyctl);
  204. data >>= 1;
  205. }
  206. spin_unlock_irqrestore(&phy_data->reg_lock, flags);
  207. }
  208. static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
  209. {
  210. struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
  211. u32 bits, reg_value;
  212. if (!phy->pmu)
  213. return;
  214. bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
  215. SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
  216. /* A83T USB2 is HSIC */
  217. if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
  218. bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
  219. SUNXI_HSIC;
  220. reg_value = readl(phy->pmu);
  221. if (enable)
  222. reg_value |= bits;
  223. else
  224. reg_value &= ~bits;
  225. writel(reg_value, phy->pmu);
  226. }
  227. static int sun4i_usb_phy_init(struct phy *_phy)
  228. {
  229. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  230. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  231. int ret;
  232. u32 val;
  233. ret = clk_prepare_enable(phy->clk);
  234. if (ret)
  235. return ret;
  236. ret = clk_prepare_enable(phy->clk2);
  237. if (ret) {
  238. clk_disable_unprepare(phy->clk);
  239. return ret;
  240. }
  241. ret = reset_control_deassert(phy->reset);
  242. if (ret) {
  243. clk_disable_unprepare(phy->clk2);
  244. clk_disable_unprepare(phy->clk);
  245. return ret;
  246. }
  247. /* Some PHYs on some SoCs need the help of PHY2 to work. */
  248. if (data->cfg->needs_phy2_siddq && phy->index != 2) {
  249. struct sun4i_usb_phy *phy2 = &data->phys[2];
  250. ret = clk_prepare_enable(phy2->clk);
  251. if (ret) {
  252. reset_control_assert(phy->reset);
  253. clk_disable_unprepare(phy->clk2);
  254. clk_disable_unprepare(phy->clk);
  255. return ret;
  256. }
  257. ret = reset_control_deassert(phy2->reset);
  258. if (ret) {
  259. clk_disable_unprepare(phy2->clk);
  260. reset_control_assert(phy->reset);
  261. clk_disable_unprepare(phy->clk2);
  262. clk_disable_unprepare(phy->clk);
  263. return ret;
  264. }
  265. /*
  266. * This extra clock is just needed to access the
  267. * REG_HCI_PHY_CTL PMU register for PHY2.
  268. */
  269. ret = clk_prepare_enable(phy2->clk2);
  270. if (ret) {
  271. reset_control_assert(phy2->reset);
  272. clk_disable_unprepare(phy2->clk);
  273. reset_control_assert(phy->reset);
  274. clk_disable_unprepare(phy->clk2);
  275. clk_disable_unprepare(phy->clk);
  276. return ret;
  277. }
  278. if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
  279. val = readl(phy2->pmu + REG_HCI_PHY_CTL);
  280. val &= ~data->cfg->hci_phy_ctl_clear;
  281. writel(val, phy2->pmu + REG_HCI_PHY_CTL);
  282. }
  283. clk_disable_unprepare(phy->clk2);
  284. }
  285. if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
  286. val = readl(phy->pmu + REG_HCI_PHY_CTL);
  287. val &= ~data->cfg->hci_phy_ctl_clear;
  288. writel(val, phy->pmu + REG_HCI_PHY_CTL);
  289. }
  290. if (data->cfg->type == sun8i_a83t_phy ||
  291. data->cfg->type == sun50i_h6_phy) {
  292. if (phy->index == 0) {
  293. val = readl(data->base + data->cfg->phyctl_offset);
  294. val |= PHY_CTL_VBUSVLDEXT;
  295. val &= ~PHY_CTL_SIDDQ;
  296. writel(val, data->base + data->cfg->phyctl_offset);
  297. }
  298. } else {
  299. /* Enable USB 45 Ohm resistor calibration */
  300. if (phy->index == 0)
  301. sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
  302. /* Adjust PHY's magnitude and rate */
  303. sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
  304. /* Disconnect threshold adjustment */
  305. sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
  306. data->cfg->disc_thresh, 2);
  307. }
  308. sun4i_usb_phy_passby(phy, 1);
  309. if (phy->index == 0) {
  310. data->phy0_init = true;
  311. /* Enable pull-ups */
  312. sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
  313. sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
  314. /* Force ISCR and cable state updates */
  315. data->id_det = -1;
  316. data->vbus_det = -1;
  317. queue_delayed_work(system_wq, &data->detect, 0);
  318. }
  319. return 0;
  320. }
  321. static int sun4i_usb_phy_exit(struct phy *_phy)
  322. {
  323. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  324. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  325. if (phy->index == 0) {
  326. if (data->cfg->type == sun8i_a83t_phy ||
  327. data->cfg->type == sun50i_h6_phy) {
  328. void __iomem *phyctl = data->base +
  329. data->cfg->phyctl_offset;
  330. writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
  331. }
  332. /* Disable pull-ups */
  333. sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
  334. sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
  335. data->phy0_init = false;
  336. }
  337. if (data->cfg->needs_phy2_siddq && phy->index != 2) {
  338. struct sun4i_usb_phy *phy2 = &data->phys[2];
  339. clk_disable_unprepare(phy2->clk);
  340. reset_control_assert(phy2->reset);
  341. }
  342. sun4i_usb_phy_passby(phy, 0);
  343. reset_control_assert(phy->reset);
  344. clk_disable_unprepare(phy->clk2);
  345. clk_disable_unprepare(phy->clk);
  346. return 0;
  347. }
  348. static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
  349. {
  350. switch (data->dr_mode) {
  351. case USB_DR_MODE_OTG:
  352. if (data->id_det_gpio)
  353. return gpiod_get_value_cansleep(data->id_det_gpio);
  354. else
  355. return 1; /* Fallback to peripheral mode */
  356. case USB_DR_MODE_HOST:
  357. return 0;
  358. case USB_DR_MODE_PERIPHERAL:
  359. default:
  360. return 1;
  361. }
  362. }
  363. static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
  364. {
  365. if (data->vbus_det_gpio)
  366. return gpiod_get_value_cansleep(data->vbus_det_gpio);
  367. if (data->vbus_power_supply) {
  368. union power_supply_propval val;
  369. int r;
  370. r = power_supply_get_property(data->vbus_power_supply,
  371. POWER_SUPPLY_PROP_PRESENT, &val);
  372. if (r == 0)
  373. return val.intval;
  374. }
  375. /* Fallback: report vbus as high */
  376. return 1;
  377. }
  378. static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
  379. {
  380. return data->vbus_det_gpio || data->vbus_power_supply;
  381. }
  382. static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
  383. {
  384. if ((data->id_det_gpio && data->id_det_irq <= 0) ||
  385. (data->vbus_det_gpio && data->vbus_det_irq <= 0))
  386. return true;
  387. /*
  388. * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
  389. * generate vbus change interrupts when the board is driving
  390. * vbus using the N_VBUSEN pin on the pmic, so we must poll
  391. * when using the pmic for vbus-det _and_ we're driving vbus.
  392. */
  393. if ((data->cfg->type == sun6i_a31_phy ||
  394. data->cfg->type == sun8i_a33_phy) &&
  395. data->vbus_power_supply && data->phys[0].regulator_on)
  396. return true;
  397. return false;
  398. }
  399. static int sun4i_usb_phy_power_on(struct phy *_phy)
  400. {
  401. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  402. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  403. int ret;
  404. if (!phy->vbus || phy->regulator_on)
  405. return 0;
  406. /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
  407. if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
  408. data->vbus_det) {
  409. dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
  410. return 0;
  411. }
  412. ret = regulator_enable(phy->vbus);
  413. if (ret)
  414. return ret;
  415. phy->regulator_on = true;
  416. /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
  417. if (phy->index == 0 && sun4i_usb_phy0_poll(data))
  418. mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
  419. return 0;
  420. }
  421. static int sun4i_usb_phy_power_off(struct phy *_phy)
  422. {
  423. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  424. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  425. if (!phy->vbus || !phy->regulator_on)
  426. return 0;
  427. regulator_disable(phy->vbus);
  428. phy->regulator_on = false;
  429. /*
  430. * phy0 vbus typically slowly discharges, sometimes this causes the
  431. * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
  432. */
  433. if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
  434. mod_delayed_work(system_wq, &data->detect, POLL_TIME);
  435. return 0;
  436. }
  437. static int sun4i_usb_phy_set_mode(struct phy *_phy,
  438. enum phy_mode mode, int submode)
  439. {
  440. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  441. struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  442. int new_mode;
  443. if (phy->index != 0) {
  444. if (mode == PHY_MODE_USB_HOST)
  445. return 0;
  446. return -EINVAL;
  447. }
  448. switch (mode) {
  449. case PHY_MODE_USB_HOST:
  450. new_mode = USB_DR_MODE_HOST;
  451. break;
  452. case PHY_MODE_USB_DEVICE:
  453. new_mode = USB_DR_MODE_PERIPHERAL;
  454. break;
  455. case PHY_MODE_USB_OTG:
  456. new_mode = USB_DR_MODE_OTG;
  457. break;
  458. default:
  459. return -EINVAL;
  460. }
  461. if (new_mode != data->dr_mode) {
  462. dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
  463. data->dr_mode = new_mode;
  464. }
  465. data->id_det = -1; /* Force reprocessing of id */
  466. data->force_session_end = true;
  467. queue_delayed_work(system_wq, &data->detect, 0);
  468. return 0;
  469. }
  470. void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
  471. {
  472. struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  473. sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
  474. }
  475. EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
  476. static const struct phy_ops sun4i_usb_phy_ops = {
  477. .init = sun4i_usb_phy_init,
  478. .exit = sun4i_usb_phy_exit,
  479. .power_on = sun4i_usb_phy_power_on,
  480. .power_off = sun4i_usb_phy_power_off,
  481. .set_mode = sun4i_usb_phy_set_mode,
  482. .owner = THIS_MODULE,
  483. };
  484. static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
  485. {
  486. u32 regval;
  487. regval = readl(data->base + REG_PHY_OTGCTL);
  488. if (id_det == 0) {
  489. /* Host mode. Route phy0 to EHCI/OHCI */
  490. regval &= ~OTGCTL_ROUTE_MUSB;
  491. } else {
  492. /* Peripheral mode. Route phy0 to MUSB */
  493. regval |= OTGCTL_ROUTE_MUSB;
  494. }
  495. writel(regval, data->base + REG_PHY_OTGCTL);
  496. }
  497. static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
  498. {
  499. struct sun4i_usb_phy_data *data =
  500. container_of(work, struct sun4i_usb_phy_data, detect.work);
  501. struct phy *phy0 = data->phys[0].phy;
  502. struct sun4i_usb_phy *phy;
  503. bool force_session_end, id_notify = false, vbus_notify = false;
  504. int id_det, vbus_det;
  505. if (!phy0)
  506. return;
  507. phy = phy_get_drvdata(phy0);
  508. id_det = sun4i_usb_phy0_get_id_det(data);
  509. vbus_det = sun4i_usb_phy0_get_vbus_det(data);
  510. mutex_lock(&phy0->mutex);
  511. if (!data->phy0_init) {
  512. mutex_unlock(&phy0->mutex);
  513. return;
  514. }
  515. force_session_end = data->force_session_end;
  516. data->force_session_end = false;
  517. if (id_det != data->id_det) {
  518. /* id-change, force session end if we've no vbus detection */
  519. if (data->dr_mode == USB_DR_MODE_OTG &&
  520. !sun4i_usb_phy0_have_vbus_det(data))
  521. force_session_end = true;
  522. /* When entering host mode (id = 0) force end the session now */
  523. if (force_session_end && id_det == 0) {
  524. sun4i_usb_phy0_set_vbus_detect(phy0, 0);
  525. msleep(200);
  526. sun4i_usb_phy0_set_vbus_detect(phy0, 1);
  527. }
  528. sun4i_usb_phy0_set_id_detect(phy0, id_det);
  529. data->id_det = id_det;
  530. id_notify = true;
  531. }
  532. if (vbus_det != data->vbus_det) {
  533. sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det);
  534. data->vbus_det = vbus_det;
  535. vbus_notify = true;
  536. }
  537. mutex_unlock(&phy0->mutex);
  538. if (id_notify) {
  539. extcon_set_state_sync(data->extcon, EXTCON_USB_HOST,
  540. !id_det);
  541. /* When leaving host mode force end the session here */
  542. if (force_session_end && id_det == 1) {
  543. mutex_lock(&phy0->mutex);
  544. sun4i_usb_phy0_set_vbus_detect(phy0, 0);
  545. msleep(1000);
  546. sun4i_usb_phy0_set_vbus_detect(phy0, 1);
  547. mutex_unlock(&phy0->mutex);
  548. }
  549. /* Enable PHY0 passby for host mode only. */
  550. sun4i_usb_phy_passby(phy, !id_det);
  551. /* Re-route PHY0 if necessary */
  552. if (data->cfg->phy0_dual_route)
  553. sun4i_usb_phy0_reroute(data, id_det);
  554. }
  555. if (vbus_notify)
  556. extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det);
  557. if (sun4i_usb_phy0_poll(data))
  558. queue_delayed_work(system_wq, &data->detect, POLL_TIME);
  559. }
  560. static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
  561. {
  562. struct sun4i_usb_phy_data *data = dev_id;
  563. /* vbus or id changed, let the pins settle and then scan them */
  564. mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
  565. return IRQ_HANDLED;
  566. }
  567. static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
  568. unsigned long val, void *v)
  569. {
  570. struct sun4i_usb_phy_data *data =
  571. container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
  572. struct power_supply *psy = v;
  573. /* Properties on the vbus_power_supply changed, scan vbus_det */
  574. if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
  575. mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
  576. return NOTIFY_OK;
  577. }
  578. static struct phy *sun4i_usb_phy_xlate(struct device *dev,
  579. struct of_phandle_args *args)
  580. {
  581. struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
  582. if (args->args[0] >= data->cfg->num_phys)
  583. return ERR_PTR(-ENODEV);
  584. if (data->cfg->missing_phys & BIT(args->args[0]))
  585. return ERR_PTR(-ENODEV);
  586. return data->phys[args->args[0]].phy;
  587. }
  588. static int sun4i_usb_phy_remove(struct platform_device *pdev)
  589. {
  590. struct device *dev = &pdev->dev;
  591. struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
  592. if (data->vbus_power_nb_registered)
  593. power_supply_unreg_notifier(&data->vbus_power_nb);
  594. if (data->id_det_irq > 0)
  595. devm_free_irq(dev, data->id_det_irq, data);
  596. if (data->vbus_det_irq > 0)
  597. devm_free_irq(dev, data->vbus_det_irq, data);
  598. cancel_delayed_work_sync(&data->detect);
  599. return 0;
  600. }
  601. static const unsigned int sun4i_usb_phy0_cable[] = {
  602. EXTCON_USB,
  603. EXTCON_USB_HOST,
  604. EXTCON_NONE,
  605. };
  606. static int sun4i_usb_phy_probe(struct platform_device *pdev)
  607. {
  608. struct sun4i_usb_phy_data *data;
  609. struct device *dev = &pdev->dev;
  610. struct device_node *np = dev->of_node;
  611. struct phy_provider *phy_provider;
  612. int i, ret;
  613. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  614. if (!data)
  615. return -ENOMEM;
  616. spin_lock_init(&data->reg_lock);
  617. INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
  618. dev_set_drvdata(dev, data);
  619. data->cfg = of_device_get_match_data(dev);
  620. if (!data->cfg)
  621. return -EINVAL;
  622. data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
  623. if (IS_ERR(data->base))
  624. return PTR_ERR(data->base);
  625. data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
  626. GPIOD_IN);
  627. if (IS_ERR(data->id_det_gpio)) {
  628. dev_err(dev, "Couldn't request ID GPIO\n");
  629. return PTR_ERR(data->id_det_gpio);
  630. }
  631. data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
  632. GPIOD_IN);
  633. if (IS_ERR(data->vbus_det_gpio)) {
  634. dev_err(dev, "Couldn't request VBUS detect GPIO\n");
  635. return PTR_ERR(data->vbus_det_gpio);
  636. }
  637. if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
  638. data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
  639. "usb0_vbus_power-supply");
  640. if (IS_ERR(data->vbus_power_supply)) {
  641. dev_err(dev, "Couldn't get the VBUS power supply\n");
  642. return PTR_ERR(data->vbus_power_supply);
  643. }
  644. if (!data->vbus_power_supply)
  645. return -EPROBE_DEFER;
  646. }
  647. data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
  648. data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable);
  649. if (IS_ERR(data->extcon)) {
  650. dev_err(dev, "Couldn't allocate our extcon device\n");
  651. return PTR_ERR(data->extcon);
  652. }
  653. ret = devm_extcon_dev_register(dev, data->extcon);
  654. if (ret) {
  655. dev_err(dev, "failed to register extcon: %d\n", ret);
  656. return ret;
  657. }
  658. for (i = 0; i < data->cfg->num_phys; i++) {
  659. struct sun4i_usb_phy *phy = data->phys + i;
  660. char name[16];
  661. if (data->cfg->missing_phys & BIT(i))
  662. continue;
  663. snprintf(name, sizeof(name), "usb%d_vbus", i);
  664. phy->vbus = devm_regulator_get_optional(dev, name);
  665. if (IS_ERR(phy->vbus)) {
  666. if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
  667. dev_err(dev,
  668. "Couldn't get regulator %s... Deferring probe\n",
  669. name);
  670. return -EPROBE_DEFER;
  671. }
  672. phy->vbus = NULL;
  673. }
  674. if (data->cfg->dedicated_clocks)
  675. snprintf(name, sizeof(name), "usb%d_phy", i);
  676. else
  677. strscpy(name, "usb_phy", sizeof(name));
  678. phy->clk = devm_clk_get(dev, name);
  679. if (IS_ERR(phy->clk)) {
  680. dev_err(dev, "failed to get clock %s\n", name);
  681. return PTR_ERR(phy->clk);
  682. }
  683. /* The first PHY is always tied to OTG, and never HSIC */
  684. if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
  685. /* HSIC needs secondary clock */
  686. snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
  687. phy->clk2 = devm_clk_get(dev, name);
  688. if (IS_ERR(phy->clk2)) {
  689. dev_err(dev, "failed to get clock %s\n", name);
  690. return PTR_ERR(phy->clk2);
  691. }
  692. } else {
  693. snprintf(name, sizeof(name), "pmu%d_clk", i);
  694. phy->clk2 = devm_clk_get_optional(dev, name);
  695. if (IS_ERR(phy->clk2)) {
  696. dev_err(dev, "failed to get clock %s\n", name);
  697. return PTR_ERR(phy->clk2);
  698. }
  699. }
  700. snprintf(name, sizeof(name), "usb%d_reset", i);
  701. phy->reset = devm_reset_control_get(dev, name);
  702. if (IS_ERR(phy->reset)) {
  703. dev_err(dev, "failed to get reset %s\n", name);
  704. return PTR_ERR(phy->reset);
  705. }
  706. if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
  707. snprintf(name, sizeof(name), "pmu%d", i);
  708. phy->pmu = devm_platform_ioremap_resource_byname(pdev, name);
  709. if (IS_ERR(phy->pmu))
  710. return PTR_ERR(phy->pmu);
  711. }
  712. phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
  713. if (IS_ERR(phy->phy)) {
  714. dev_err(dev, "failed to create PHY %d\n", i);
  715. return PTR_ERR(phy->phy);
  716. }
  717. phy->index = i;
  718. phy_set_drvdata(phy->phy, &data->phys[i]);
  719. }
  720. data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
  721. if (data->id_det_irq > 0) {
  722. ret = devm_request_irq(dev, data->id_det_irq,
  723. sun4i_usb_phy0_id_vbus_det_irq,
  724. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  725. "usb0-id-det", data);
  726. if (ret) {
  727. dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
  728. return ret;
  729. }
  730. }
  731. data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
  732. if (data->vbus_det_irq > 0) {
  733. ret = devm_request_irq(dev, data->vbus_det_irq,
  734. sun4i_usb_phy0_id_vbus_det_irq,
  735. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  736. "usb0-vbus-det", data);
  737. if (ret) {
  738. dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
  739. data->vbus_det_irq = -1;
  740. sun4i_usb_phy_remove(pdev); /* Stop detect work */
  741. return ret;
  742. }
  743. }
  744. if (data->vbus_power_supply) {
  745. data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
  746. data->vbus_power_nb.priority = 0;
  747. ret = power_supply_reg_notifier(&data->vbus_power_nb);
  748. if (ret) {
  749. sun4i_usb_phy_remove(pdev); /* Stop detect work */
  750. return ret;
  751. }
  752. data->vbus_power_nb_registered = true;
  753. }
  754. phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
  755. if (IS_ERR(phy_provider)) {
  756. sun4i_usb_phy_remove(pdev); /* Stop detect work */
  757. return PTR_ERR(phy_provider);
  758. }
  759. dev_dbg(dev, "successfully loaded\n");
  760. return 0;
  761. }
  762. static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
  763. .num_phys = 3,
  764. .type = sun4i_a10_phy,
  765. .disc_thresh = 3,
  766. .phyctl_offset = REG_PHYCTL_A10,
  767. .dedicated_clocks = false,
  768. };
  769. static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
  770. .num_phys = 2,
  771. .type = sun4i_a10_phy,
  772. .disc_thresh = 2,
  773. .phyctl_offset = REG_PHYCTL_A10,
  774. .dedicated_clocks = false,
  775. };
  776. static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
  777. .num_phys = 3,
  778. .type = sun6i_a31_phy,
  779. .disc_thresh = 3,
  780. .phyctl_offset = REG_PHYCTL_A10,
  781. .dedicated_clocks = true,
  782. };
  783. static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
  784. .num_phys = 3,
  785. .type = sun4i_a10_phy,
  786. .disc_thresh = 2,
  787. .phyctl_offset = REG_PHYCTL_A10,
  788. .dedicated_clocks = false,
  789. };
  790. static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
  791. .num_phys = 2,
  792. .type = sun6i_a31_phy,
  793. .disc_thresh = 3,
  794. .phyctl_offset = REG_PHYCTL_A10,
  795. .dedicated_clocks = true,
  796. };
  797. static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
  798. .num_phys = 2,
  799. .type = sun8i_a33_phy,
  800. .disc_thresh = 3,
  801. .phyctl_offset = REG_PHYCTL_A33,
  802. .dedicated_clocks = true,
  803. };
  804. static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
  805. .num_phys = 3,
  806. .hsic_index = 2,
  807. .type = sun8i_a83t_phy,
  808. .phyctl_offset = REG_PHYCTL_A33,
  809. .dedicated_clocks = true,
  810. };
  811. static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
  812. .num_phys = 4,
  813. .type = sun8i_h3_phy,
  814. .disc_thresh = 3,
  815. .phyctl_offset = REG_PHYCTL_A33,
  816. .dedicated_clocks = true,
  817. .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
  818. .phy0_dual_route = true,
  819. };
  820. static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
  821. .num_phys = 3,
  822. .type = sun8i_r40_phy,
  823. .disc_thresh = 3,
  824. .phyctl_offset = REG_PHYCTL_A33,
  825. .dedicated_clocks = true,
  826. .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
  827. .phy0_dual_route = true,
  828. };
  829. static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
  830. .num_phys = 1,
  831. .type = sun8i_v3s_phy,
  832. .disc_thresh = 3,
  833. .phyctl_offset = REG_PHYCTL_A33,
  834. .dedicated_clocks = true,
  835. .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
  836. .phy0_dual_route = true,
  837. };
  838. static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
  839. .num_phys = 2,
  840. .type = sun50i_h6_phy,
  841. .phyctl_offset = REG_PHYCTL_A33,
  842. .dedicated_clocks = true,
  843. .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
  844. .phy0_dual_route = true,
  845. };
  846. static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
  847. .num_phys = 2,
  848. .type = sun50i_a64_phy,
  849. .disc_thresh = 3,
  850. .phyctl_offset = REG_PHYCTL_A33,
  851. .dedicated_clocks = true,
  852. .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
  853. .phy0_dual_route = true,
  854. };
  855. static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
  856. .num_phys = 4,
  857. .type = sun50i_h6_phy,
  858. .phyctl_offset = REG_PHYCTL_A33,
  859. .dedicated_clocks = true,
  860. .phy0_dual_route = true,
  861. .missing_phys = BIT(1) | BIT(2),
  862. };
  863. static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
  864. .num_phys = 4,
  865. .type = sun50i_h6_phy,
  866. .disc_thresh = 3,
  867. .phyctl_offset = REG_PHYCTL_A33,
  868. .dedicated_clocks = true,
  869. .phy0_dual_route = true,
  870. .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
  871. .needs_phy2_siddq = true,
  872. };
  873. static const struct of_device_id sun4i_usb_phy_of_match[] = {
  874. { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
  875. { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
  876. { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
  877. { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
  878. { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
  879. { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
  880. { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
  881. { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
  882. { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
  883. { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
  884. { .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
  885. { .compatible = "allwinner,sun50i-a64-usb-phy",
  886. .data = &sun50i_a64_cfg},
  887. { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
  888. { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
  889. { },
  890. };
  891. MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
  892. static struct platform_driver sun4i_usb_phy_driver = {
  893. .probe = sun4i_usb_phy_probe,
  894. .remove = sun4i_usb_phy_remove,
  895. .driver = {
  896. .of_match_table = sun4i_usb_phy_of_match,
  897. .name = "sun4i-usb-phy",
  898. }
  899. };
  900. module_platform_driver(sun4i_usb_phy_driver);
  901. MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
  902. MODULE_AUTHOR("Hans de Goede <[email protected]>");
  903. MODULE_LICENSE("GPL v2");