pcie-rcar.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * PCIe driver for Renesas R-Car SoCs
  4. * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
  5. *
  6. * Author: Phil Edworthy <[email protected]>
  7. */
  8. #ifndef _PCIE_RCAR_H
  9. #define _PCIE_RCAR_H
  10. #define PCIECAR 0x000010
  11. #define PCIECCTLR 0x000018
  12. #define CONFIG_SEND_ENABLE BIT(31)
  13. #define TYPE0 (0 << 8)
  14. #define TYPE1 BIT(8)
  15. #define PCIECDR 0x000020
  16. #define PCIEMSR 0x000028
  17. #define PCIEINTXR 0x000400
  18. #define ASTINTX BIT(16)
  19. #define PCIEPHYSR 0x0007f0
  20. #define PHYRDY BIT(0)
  21. #define PCIEMSITXR 0x000840
  22. /* Transfer control */
  23. #define PCIETCTLR 0x02000
  24. #define DL_DOWN BIT(3)
  25. #define CFINIT BIT(0)
  26. #define PCIETSTR 0x02004
  27. #define DATA_LINK_ACTIVE BIT(0)
  28. #define PCIEERRFR 0x02020
  29. #define UNSUPPORTED_REQUEST BIT(4)
  30. #define PCIEMSIFR 0x02044
  31. #define PCIEMSIALR 0x02048
  32. #define MSIFE BIT(0)
  33. #define PCIEMSIAUR 0x0204c
  34. #define PCIEMSIIER 0x02050
  35. /* root port address */
  36. #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
  37. /* local address reg & mask */
  38. #define PCIELAR(x) (0x02200 + ((x) * 0x20))
  39. #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
  40. #define LAM_PREFETCH BIT(3)
  41. #define LAM_64BIT BIT(2)
  42. #define LAR_ENABLE BIT(1)
  43. /* PCIe address reg & mask */
  44. #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
  45. #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
  46. #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
  47. #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
  48. #define PAR_ENABLE BIT(31)
  49. #define IO_SPACE BIT(8)
  50. /* Configuration */
  51. #define PCICONF(x) (0x010000 + ((x) * 0x4))
  52. #define INTDIS BIT(10)
  53. #define PMCAP(x) (0x010040 + ((x) * 0x4))
  54. #define MSICAP(x) (0x010050 + ((x) * 0x4))
  55. #define MSICAP0_MSIE BIT(16)
  56. #define MSICAP0_MMESCAP_OFFSET 17
  57. #define MSICAP0_MMESE_OFFSET 20
  58. #define MSICAP0_MMESE_MASK GENMASK(22, 20)
  59. #define EXPCAP(x) (0x010070 + ((x) * 0x4))
  60. #define VCCAP(x) (0x010100 + ((x) * 0x4))
  61. /* link layer */
  62. #define IDSETR0 0x011000
  63. #define IDSETR1 0x011004
  64. #define SUBIDSETR 0x011024
  65. #define TLCTLR 0x011048
  66. #define MACSR 0x011054
  67. #define SPCHGFIN BIT(4)
  68. #define SPCHGFAIL BIT(6)
  69. #define SPCHGSUC BIT(7)
  70. #define LINK_SPEED (0xf << 16)
  71. #define LINK_SPEED_2_5GTS (1 << 16)
  72. #define LINK_SPEED_5_0GTS (2 << 16)
  73. #define MACCTLR 0x011058
  74. #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
  75. #define SPEED_CHANGE BIT(24)
  76. #define SCRAMBLE_DISABLE BIT(27)
  77. #define LTSMDIS BIT(31)
  78. #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
  79. #define PMSR 0x01105c
  80. #define L1FAEG BIT(31)
  81. #define PMEL1RX BIT(23)
  82. #define PMSTATE GENMASK(18, 16)
  83. #define PMSTATE_L1 (3 << 16)
  84. #define PMCTLR 0x011060
  85. #define L1IATN BIT(31)
  86. #define MACS2R 0x011078
  87. #define MACCGSPSETR 0x011084
  88. #define SPCNGRSN BIT(31)
  89. /* R-Car H1 PHY */
  90. #define H1_PCIEPHYADRR 0x04000c
  91. #define WRITE_CMD BIT(16)
  92. #define PHY_ACK BIT(24)
  93. #define RATE_POS 12
  94. #define LANE_POS 8
  95. #define ADR_POS 0
  96. #define H1_PCIEPHYDOUTR 0x040014
  97. /* R-Car Gen2 PHY */
  98. #define GEN2_PCIEPHYADDR 0x780
  99. #define GEN2_PCIEPHYDATA 0x784
  100. #define GEN2_PCIEPHYCTRL 0x78c
  101. #define INT_PCI_MSI_NR 32
  102. #define RCONF(x) (PCICONF(0) + (x))
  103. #define RPMCAP(x) (PMCAP(0) + (x))
  104. #define REXPCAP(x) (EXPCAP(0) + (x))
  105. #define RVCCAP(x) (VCCAP(0) + (x))
  106. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
  107. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
  108. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
  109. #define RCAR_PCI_MAX_RESOURCES 4
  110. #define MAX_NR_INBOUND_MAPS 6
  111. struct rcar_pcie {
  112. struct device *dev;
  113. void __iomem *base;
  114. };
  115. enum {
  116. RCAR_PCI_ACCESS_READ,
  117. RCAR_PCI_ACCESS_WRITE,
  118. };
  119. void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
  120. u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
  121. void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
  122. int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
  123. int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
  124. void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
  125. struct resource_entry *window);
  126. void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
  127. u64 pci_addr, u64 flags, int idx, bool host);
  128. #endif