pcie-rcar-host.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe driver for Renesas R-Car SoCs
  4. * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
  5. *
  6. * Based on:
  7. * arch/sh/drivers/pci/pcie-sh7786.c
  8. * arch/sh/drivers/pci/ops-sh7786.c
  9. * Copyright (C) 2009 - 2011 Paul Mundt
  10. *
  11. * Author: Phil Edworthy <[email protected]>
  12. */
  13. #include <linux/bitops.h>
  14. #include <linux/clk.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/delay.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/irqdomain.h>
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/iopoll.h>
  23. #include <linux/msi.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/pci.h>
  28. #include <linux/phy/phy.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pm_runtime.h>
  31. #include "pcie-rcar.h"
  32. struct rcar_msi {
  33. DECLARE_BITMAP(used, INT_PCI_MSI_NR);
  34. struct irq_domain *domain;
  35. struct mutex map_lock;
  36. spinlock_t mask_lock;
  37. int irq1;
  38. int irq2;
  39. };
  40. #ifdef CONFIG_ARM
  41. /*
  42. * Here we keep a static copy of the remapped PCIe controller address.
  43. * This is only used on aarch32 systems, all of which have one single
  44. * PCIe controller, to provide quick access to the PCIe controller in
  45. * the L1 link state fixup function, called from the ARM fault handler.
  46. */
  47. static void __iomem *pcie_base;
  48. /*
  49. * Static copy of PCIe device pointer, so we can check whether the
  50. * device is runtime suspended or not.
  51. */
  52. static struct device *pcie_dev;
  53. #endif
  54. /* Structure representing the PCIe interface */
  55. struct rcar_pcie_host {
  56. struct rcar_pcie pcie;
  57. struct phy *phy;
  58. struct clk *bus_clk;
  59. struct rcar_msi msi;
  60. int (*phy_init_fn)(struct rcar_pcie_host *host);
  61. };
  62. static DEFINE_SPINLOCK(pmsr_lock);
  63. static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
  64. {
  65. unsigned long flags;
  66. u32 pmsr, val;
  67. int ret = 0;
  68. spin_lock_irqsave(&pmsr_lock, flags);
  69. if (!pcie_base || pm_runtime_suspended(pcie_dev)) {
  70. ret = -EINVAL;
  71. goto unlock_exit;
  72. }
  73. pmsr = readl(pcie_base + PMSR);
  74. /*
  75. * Test if the PCIe controller received PM_ENTER_L1 DLLP and
  76. * the PCIe controller is not in L1 link state. If true, apply
  77. * fix, which will put the controller into L1 link state, from
  78. * which it can return to L0s/L0 on its own.
  79. */
  80. if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
  81. writel(L1IATN, pcie_base + PMCTLR);
  82. ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
  83. val & L1FAEG, 10, 1000);
  84. WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
  85. writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
  86. }
  87. unlock_exit:
  88. spin_unlock_irqrestore(&pmsr_lock, flags);
  89. return ret;
  90. }
  91. static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
  92. {
  93. return container_of(msi, struct rcar_pcie_host, msi);
  94. }
  95. static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
  96. {
  97. unsigned int shift = BITS_PER_BYTE * (where & 3);
  98. u32 val = rcar_pci_read_reg(pcie, where & ~3);
  99. return val >> shift;
  100. }
  101. #ifdef CONFIG_ARM
  102. #define __rcar_pci_rw_reg_workaround(instr) \
  103. " .arch armv7-a\n" \
  104. "1: " instr " %1, [%2]\n" \
  105. "2: isb\n" \
  106. "3: .pushsection .text.fixup,\"ax\"\n" \
  107. " .align 2\n" \
  108. "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \
  109. " b 3b\n" \
  110. " .popsection\n" \
  111. " .pushsection __ex_table,\"a\"\n" \
  112. " .align 3\n" \
  113. " .long 1b, 4b\n" \
  114. " .long 2b, 4b\n" \
  115. " .popsection\n"
  116. #endif
  117. static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val,
  118. unsigned int reg)
  119. {
  120. int error = PCIBIOS_SUCCESSFUL;
  121. #ifdef CONFIG_ARM
  122. asm volatile(
  123. __rcar_pci_rw_reg_workaround("str")
  124. : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory");
  125. #else
  126. rcar_pci_write_reg(pcie, val, reg);
  127. #endif
  128. return error;
  129. }
  130. static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val,
  131. unsigned int reg)
  132. {
  133. int error = PCIBIOS_SUCCESSFUL;
  134. #ifdef CONFIG_ARM
  135. asm volatile(
  136. __rcar_pci_rw_reg_workaround("ldr")
  137. : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory");
  138. if (error != PCIBIOS_SUCCESSFUL)
  139. PCI_SET_ERROR_RESPONSE(val);
  140. #else
  141. *val = rcar_pci_read_reg(pcie, reg);
  142. #endif
  143. return error;
  144. }
  145. /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
  146. static int rcar_pcie_config_access(struct rcar_pcie_host *host,
  147. unsigned char access_type, struct pci_bus *bus,
  148. unsigned int devfn, int where, u32 *data)
  149. {
  150. struct rcar_pcie *pcie = &host->pcie;
  151. unsigned int dev, func, reg, index;
  152. int ret;
  153. /* Wake the bus up in case it is in L1 state. */
  154. ret = rcar_pcie_wakeup(pcie->dev, pcie->base);
  155. if (ret) {
  156. PCI_SET_ERROR_RESPONSE(data);
  157. return PCIBIOS_SET_FAILED;
  158. }
  159. dev = PCI_SLOT(devfn);
  160. func = PCI_FUNC(devfn);
  161. reg = where & ~3;
  162. index = reg / 4;
  163. /*
  164. * While each channel has its own memory-mapped extended config
  165. * space, it's generally only accessible when in endpoint mode.
  166. * When in root complex mode, the controller is unable to target
  167. * itself with either type 0 or type 1 accesses, and indeed, any
  168. * controller initiated target transfer to its own config space
  169. * result in a completer abort.
  170. *
  171. * Each channel effectively only supports a single device, but as
  172. * the same channel <-> device access works for any PCI_SLOT()
  173. * value, we cheat a bit here and bind the controller's config
  174. * space to devfn 0 in order to enable self-enumeration. In this
  175. * case the regular ECAR/ECDR path is sidelined and the mangled
  176. * config access itself is initiated as an internal bus transaction.
  177. */
  178. if (pci_is_root_bus(bus)) {
  179. if (dev != 0)
  180. return PCIBIOS_DEVICE_NOT_FOUND;
  181. if (access_type == RCAR_PCI_ACCESS_READ)
  182. *data = rcar_pci_read_reg(pcie, PCICONF(index));
  183. else
  184. rcar_pci_write_reg(pcie, *data, PCICONF(index));
  185. return PCIBIOS_SUCCESSFUL;
  186. }
  187. /* Clear errors */
  188. rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
  189. /* Set the PIO address */
  190. rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
  191. PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
  192. /* Enable the configuration access */
  193. if (pci_is_root_bus(bus->parent))
  194. rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
  195. else
  196. rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
  197. /* Check for errors */
  198. if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
  199. return PCIBIOS_DEVICE_NOT_FOUND;
  200. /* Check for master and target aborts */
  201. if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
  202. (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
  203. return PCIBIOS_DEVICE_NOT_FOUND;
  204. if (access_type == RCAR_PCI_ACCESS_READ)
  205. ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR);
  206. else
  207. ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR);
  208. /* Disable the configuration access */
  209. rcar_pci_write_reg(pcie, 0, PCIECCTLR);
  210. return ret;
  211. }
  212. static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
  213. int where, int size, u32 *val)
  214. {
  215. struct rcar_pcie_host *host = bus->sysdata;
  216. int ret;
  217. ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
  218. bus, devfn, where, val);
  219. if (ret != PCIBIOS_SUCCESSFUL)
  220. return ret;
  221. if (size == 1)
  222. *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
  223. else if (size == 2)
  224. *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
  225. dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
  226. bus->number, devfn, where, size, *val);
  227. return ret;
  228. }
  229. /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
  230. static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
  231. int where, int size, u32 val)
  232. {
  233. struct rcar_pcie_host *host = bus->sysdata;
  234. unsigned int shift;
  235. u32 data;
  236. int ret;
  237. ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
  238. bus, devfn, where, &data);
  239. if (ret != PCIBIOS_SUCCESSFUL)
  240. return ret;
  241. dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
  242. bus->number, devfn, where, size, val);
  243. if (size == 1) {
  244. shift = BITS_PER_BYTE * (where & 3);
  245. data &= ~(0xff << shift);
  246. data |= ((val & 0xff) << shift);
  247. } else if (size == 2) {
  248. shift = BITS_PER_BYTE * (where & 2);
  249. data &= ~(0xffff << shift);
  250. data |= ((val & 0xffff) << shift);
  251. } else
  252. data = val;
  253. ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE,
  254. bus, devfn, where, &data);
  255. return ret;
  256. }
  257. static struct pci_ops rcar_pcie_ops = {
  258. .read = rcar_pcie_read_conf,
  259. .write = rcar_pcie_write_conf,
  260. };
  261. static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
  262. {
  263. struct device *dev = pcie->dev;
  264. unsigned int timeout = 1000;
  265. u32 macsr;
  266. if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
  267. return;
  268. if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
  269. dev_err(dev, "Speed change already in progress\n");
  270. return;
  271. }
  272. macsr = rcar_pci_read_reg(pcie, MACSR);
  273. if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
  274. goto done;
  275. /* Set target link speed to 5.0 GT/s */
  276. rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
  277. PCI_EXP_LNKSTA_CLS_5_0GB);
  278. /* Set speed change reason as intentional factor */
  279. rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
  280. /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
  281. if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
  282. rcar_pci_write_reg(pcie, macsr, MACSR);
  283. /* Start link speed change */
  284. rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
  285. while (timeout--) {
  286. macsr = rcar_pci_read_reg(pcie, MACSR);
  287. if (macsr & SPCHGFIN) {
  288. /* Clear the interrupt bits */
  289. rcar_pci_write_reg(pcie, macsr, MACSR);
  290. if (macsr & SPCHGFAIL)
  291. dev_err(dev, "Speed change failed\n");
  292. goto done;
  293. }
  294. msleep(1);
  295. }
  296. dev_err(dev, "Speed change timed out\n");
  297. done:
  298. dev_info(dev, "Current link speed is %s GT/s\n",
  299. (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
  300. }
  301. static void rcar_pcie_hw_enable(struct rcar_pcie_host *host)
  302. {
  303. struct rcar_pcie *pcie = &host->pcie;
  304. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
  305. struct resource_entry *win;
  306. LIST_HEAD(res);
  307. int i = 0;
  308. /* Try setting 5 GT/s link speed */
  309. rcar_pcie_force_speedup(pcie);
  310. /* Setup PCI resources */
  311. resource_list_for_each_entry(win, &bridge->windows) {
  312. struct resource *res = win->res;
  313. if (!res->flags)
  314. continue;
  315. switch (resource_type(res)) {
  316. case IORESOURCE_IO:
  317. case IORESOURCE_MEM:
  318. rcar_pcie_set_outbound(pcie, i, win);
  319. i++;
  320. break;
  321. }
  322. }
  323. }
  324. static int rcar_pcie_enable(struct rcar_pcie_host *host)
  325. {
  326. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
  327. rcar_pcie_hw_enable(host);
  328. pci_add_flags(PCI_REASSIGN_ALL_BUS);
  329. bridge->sysdata = host;
  330. bridge->ops = &rcar_pcie_ops;
  331. return pci_host_probe(bridge);
  332. }
  333. static int phy_wait_for_ack(struct rcar_pcie *pcie)
  334. {
  335. struct device *dev = pcie->dev;
  336. unsigned int timeout = 100;
  337. while (timeout--) {
  338. if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
  339. return 0;
  340. udelay(100);
  341. }
  342. dev_err(dev, "Access to PCIe phy timed out\n");
  343. return -ETIMEDOUT;
  344. }
  345. static void phy_write_reg(struct rcar_pcie *pcie,
  346. unsigned int rate, u32 addr,
  347. unsigned int lane, u32 data)
  348. {
  349. u32 phyaddr;
  350. phyaddr = WRITE_CMD |
  351. ((rate & 1) << RATE_POS) |
  352. ((lane & 0xf) << LANE_POS) |
  353. ((addr & 0xff) << ADR_POS);
  354. /* Set write data */
  355. rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
  356. rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
  357. /* Ignore errors as they will be dealt with if the data link is down */
  358. phy_wait_for_ack(pcie);
  359. /* Clear command */
  360. rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
  361. rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
  362. /* Ignore errors as they will be dealt with if the data link is down */
  363. phy_wait_for_ack(pcie);
  364. }
  365. static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
  366. {
  367. int err;
  368. /* Begin initialization */
  369. rcar_pci_write_reg(pcie, 0, PCIETCTLR);
  370. /* Set mode */
  371. rcar_pci_write_reg(pcie, 1, PCIEMSR);
  372. err = rcar_pcie_wait_for_phyrdy(pcie);
  373. if (err)
  374. return err;
  375. /*
  376. * Initial header for port config space is type 1, set the device
  377. * class to match. Hardware takes care of propagating the IDSETR
  378. * settings, so there is no need to bother with a quirk.
  379. */
  380. rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1);
  381. /*
  382. * Setup Secondary Bus Number & Subordinate Bus Number, even though
  383. * they aren't used, to avoid bridge being detected as broken.
  384. */
  385. rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
  386. rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
  387. /* Initialize default capabilities. */
  388. rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
  389. rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
  390. PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
  391. rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
  392. PCI_HEADER_TYPE_BRIDGE);
  393. /* Enable data link layer active state reporting */
  394. rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
  395. PCI_EXP_LNKCAP_DLLLARC);
  396. /* Write out the physical slot number = 0 */
  397. rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
  398. /* Set the completion timer timeout to the maximum 50ms. */
  399. rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
  400. /* Terminate list of capabilities (Next Capability Offset=0) */
  401. rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
  402. /* Enable MSI */
  403. if (IS_ENABLED(CONFIG_PCI_MSI))
  404. rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
  405. rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
  406. /* Finish initialization - establish a PCI Express link */
  407. rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
  408. /* This will timeout if we don't have a link. */
  409. err = rcar_pcie_wait_for_dl(pcie);
  410. if (err)
  411. return err;
  412. /* Enable INTx interrupts */
  413. rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
  414. wmb();
  415. return 0;
  416. }
  417. static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host)
  418. {
  419. struct rcar_pcie *pcie = &host->pcie;
  420. /* Initialize the phy */
  421. phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
  422. phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
  423. phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
  424. phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
  425. phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
  426. phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
  427. phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
  428. phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
  429. phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
  430. phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
  431. phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
  432. phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
  433. phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
  434. phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
  435. phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
  436. return 0;
  437. }
  438. static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host)
  439. {
  440. struct rcar_pcie *pcie = &host->pcie;
  441. /*
  442. * These settings come from the R-Car Series, 2nd Generation User's
  443. * Manual, section 50.3.1 (2) Initialization of the physical layer.
  444. */
  445. rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
  446. rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
  447. rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
  448. rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
  449. rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
  450. /* The following value is for DC connection, no termination resistor */
  451. rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
  452. rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
  453. rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
  454. return 0;
  455. }
  456. static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
  457. {
  458. int err;
  459. err = phy_init(host->phy);
  460. if (err)
  461. return err;
  462. err = phy_power_on(host->phy);
  463. if (err)
  464. phy_exit(host->phy);
  465. return err;
  466. }
  467. static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
  468. {
  469. struct rcar_pcie_host *host = data;
  470. struct rcar_pcie *pcie = &host->pcie;
  471. struct rcar_msi *msi = &host->msi;
  472. struct device *dev = pcie->dev;
  473. unsigned long reg;
  474. reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
  475. /* MSI & INTx share an interrupt - we only handle MSI here */
  476. if (!reg)
  477. return IRQ_NONE;
  478. while (reg) {
  479. unsigned int index = find_first_bit(&reg, 32);
  480. int ret;
  481. ret = generic_handle_domain_irq(msi->domain->parent, index);
  482. if (ret) {
  483. /* Unknown MSI, just clear it */
  484. dev_dbg(dev, "unexpected MSI\n");
  485. rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
  486. }
  487. /* see if there's any more pending in this vector */
  488. reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
  489. }
  490. return IRQ_HANDLED;
  491. }
  492. static void rcar_msi_top_irq_ack(struct irq_data *d)
  493. {
  494. irq_chip_ack_parent(d);
  495. }
  496. static void rcar_msi_top_irq_mask(struct irq_data *d)
  497. {
  498. pci_msi_mask_irq(d);
  499. irq_chip_mask_parent(d);
  500. }
  501. static void rcar_msi_top_irq_unmask(struct irq_data *d)
  502. {
  503. pci_msi_unmask_irq(d);
  504. irq_chip_unmask_parent(d);
  505. }
  506. static struct irq_chip rcar_msi_top_chip = {
  507. .name = "PCIe MSI",
  508. .irq_ack = rcar_msi_top_irq_ack,
  509. .irq_mask = rcar_msi_top_irq_mask,
  510. .irq_unmask = rcar_msi_top_irq_unmask,
  511. };
  512. static void rcar_msi_irq_ack(struct irq_data *d)
  513. {
  514. struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
  515. struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
  516. /* clear the interrupt */
  517. rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
  518. }
  519. static void rcar_msi_irq_mask(struct irq_data *d)
  520. {
  521. struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
  522. struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
  523. unsigned long flags;
  524. u32 value;
  525. spin_lock_irqsave(&msi->mask_lock, flags);
  526. value = rcar_pci_read_reg(pcie, PCIEMSIIER);
  527. value &= ~BIT(d->hwirq);
  528. rcar_pci_write_reg(pcie, value, PCIEMSIIER);
  529. spin_unlock_irqrestore(&msi->mask_lock, flags);
  530. }
  531. static void rcar_msi_irq_unmask(struct irq_data *d)
  532. {
  533. struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
  534. struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
  535. unsigned long flags;
  536. u32 value;
  537. spin_lock_irqsave(&msi->mask_lock, flags);
  538. value = rcar_pci_read_reg(pcie, PCIEMSIIER);
  539. value |= BIT(d->hwirq);
  540. rcar_pci_write_reg(pcie, value, PCIEMSIIER);
  541. spin_unlock_irqrestore(&msi->mask_lock, flags);
  542. }
  543. static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
  544. {
  545. return -EINVAL;
  546. }
  547. static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  548. {
  549. struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
  550. struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
  551. msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
  552. msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
  553. msg->data = data->hwirq;
  554. }
  555. static struct irq_chip rcar_msi_bottom_chip = {
  556. .name = "Rcar MSI",
  557. .irq_ack = rcar_msi_irq_ack,
  558. .irq_mask = rcar_msi_irq_mask,
  559. .irq_unmask = rcar_msi_irq_unmask,
  560. .irq_set_affinity = rcar_msi_set_affinity,
  561. .irq_compose_msi_msg = rcar_compose_msi_msg,
  562. };
  563. static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
  564. unsigned int nr_irqs, void *args)
  565. {
  566. struct rcar_msi *msi = domain->host_data;
  567. unsigned int i;
  568. int hwirq;
  569. mutex_lock(&msi->map_lock);
  570. hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
  571. mutex_unlock(&msi->map_lock);
  572. if (hwirq < 0)
  573. return -ENOSPC;
  574. for (i = 0; i < nr_irqs; i++)
  575. irq_domain_set_info(domain, virq + i, hwirq + i,
  576. &rcar_msi_bottom_chip, domain->host_data,
  577. handle_edge_irq, NULL, NULL);
  578. return 0;
  579. }
  580. static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
  581. unsigned int nr_irqs)
  582. {
  583. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  584. struct rcar_msi *msi = domain->host_data;
  585. mutex_lock(&msi->map_lock);
  586. bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
  587. mutex_unlock(&msi->map_lock);
  588. }
  589. static const struct irq_domain_ops rcar_msi_domain_ops = {
  590. .alloc = rcar_msi_domain_alloc,
  591. .free = rcar_msi_domain_free,
  592. };
  593. static struct msi_domain_info rcar_msi_info = {
  594. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  595. MSI_FLAG_MULTI_PCI_MSI),
  596. .chip = &rcar_msi_top_chip,
  597. };
  598. static int rcar_allocate_domains(struct rcar_msi *msi)
  599. {
  600. struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
  601. struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
  602. struct irq_domain *parent;
  603. parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
  604. &rcar_msi_domain_ops, msi);
  605. if (!parent) {
  606. dev_err(pcie->dev, "failed to create IRQ domain\n");
  607. return -ENOMEM;
  608. }
  609. irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
  610. msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
  611. if (!msi->domain) {
  612. dev_err(pcie->dev, "failed to create MSI domain\n");
  613. irq_domain_remove(parent);
  614. return -ENOMEM;
  615. }
  616. return 0;
  617. }
  618. static void rcar_free_domains(struct rcar_msi *msi)
  619. {
  620. struct irq_domain *parent = msi->domain->parent;
  621. irq_domain_remove(msi->domain);
  622. irq_domain_remove(parent);
  623. }
  624. static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
  625. {
  626. struct rcar_pcie *pcie = &host->pcie;
  627. struct device *dev = pcie->dev;
  628. struct rcar_msi *msi = &host->msi;
  629. struct resource res;
  630. int err;
  631. mutex_init(&msi->map_lock);
  632. spin_lock_init(&msi->mask_lock);
  633. err = of_address_to_resource(dev->of_node, 0, &res);
  634. if (err)
  635. return err;
  636. err = rcar_allocate_domains(msi);
  637. if (err)
  638. return err;
  639. /* Two irqs are for MSI, but they are also used for non-MSI irqs */
  640. err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
  641. IRQF_SHARED | IRQF_NO_THREAD,
  642. rcar_msi_bottom_chip.name, host);
  643. if (err < 0) {
  644. dev_err(dev, "failed to request IRQ: %d\n", err);
  645. goto err;
  646. }
  647. err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
  648. IRQF_SHARED | IRQF_NO_THREAD,
  649. rcar_msi_bottom_chip.name, host);
  650. if (err < 0) {
  651. dev_err(dev, "failed to request IRQ: %d\n", err);
  652. goto err;
  653. }
  654. /* disable all MSIs */
  655. rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
  656. /*
  657. * Setup MSI data target using RC base address address, which
  658. * is guaranteed to be in the low 32bit range on any RCar HW.
  659. */
  660. rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
  661. rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
  662. return 0;
  663. err:
  664. rcar_free_domains(msi);
  665. return err;
  666. }
  667. static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
  668. {
  669. struct rcar_pcie *pcie = &host->pcie;
  670. /* Disable all MSI interrupts */
  671. rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
  672. /* Disable address decoding of the MSI interrupt, MSIFE */
  673. rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
  674. rcar_free_domains(&host->msi);
  675. }
  676. static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
  677. {
  678. struct rcar_pcie *pcie = &host->pcie;
  679. struct device *dev = pcie->dev;
  680. struct resource res;
  681. int err, i;
  682. host->phy = devm_phy_optional_get(dev, "pcie");
  683. if (IS_ERR(host->phy))
  684. return PTR_ERR(host->phy);
  685. err = of_address_to_resource(dev->of_node, 0, &res);
  686. if (err)
  687. return err;
  688. pcie->base = devm_ioremap_resource(dev, &res);
  689. if (IS_ERR(pcie->base))
  690. return PTR_ERR(pcie->base);
  691. host->bus_clk = devm_clk_get(dev, "pcie_bus");
  692. if (IS_ERR(host->bus_clk)) {
  693. dev_err(dev, "cannot get pcie bus clock\n");
  694. return PTR_ERR(host->bus_clk);
  695. }
  696. i = irq_of_parse_and_map(dev->of_node, 0);
  697. if (!i) {
  698. dev_err(dev, "cannot get platform resources for msi interrupt\n");
  699. err = -ENOENT;
  700. goto err_irq1;
  701. }
  702. host->msi.irq1 = i;
  703. i = irq_of_parse_and_map(dev->of_node, 1);
  704. if (!i) {
  705. dev_err(dev, "cannot get platform resources for msi interrupt\n");
  706. err = -ENOENT;
  707. goto err_irq2;
  708. }
  709. host->msi.irq2 = i;
  710. #ifdef CONFIG_ARM
  711. /* Cache static copy for L1 link state fixup hook on aarch32 */
  712. pcie_base = pcie->base;
  713. pcie_dev = pcie->dev;
  714. #endif
  715. return 0;
  716. err_irq2:
  717. irq_dispose_mapping(host->msi.irq1);
  718. err_irq1:
  719. return err;
  720. }
  721. static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
  722. struct resource_entry *entry,
  723. int *index)
  724. {
  725. u64 restype = entry->res->flags;
  726. u64 cpu_addr = entry->res->start;
  727. u64 cpu_end = entry->res->end;
  728. u64 pci_addr = entry->res->start - entry->offset;
  729. u32 flags = LAM_64BIT | LAR_ENABLE;
  730. u64 mask;
  731. u64 size = resource_size(entry->res);
  732. int idx = *index;
  733. if (restype & IORESOURCE_PREFETCH)
  734. flags |= LAM_PREFETCH;
  735. while (cpu_addr < cpu_end) {
  736. if (idx >= MAX_NR_INBOUND_MAPS - 1) {
  737. dev_err(pcie->dev, "Failed to map inbound regions!\n");
  738. return -EINVAL;
  739. }
  740. /*
  741. * If the size of the range is larger than the alignment of
  742. * the start address, we have to use multiple entries to
  743. * perform the mapping.
  744. */
  745. if (cpu_addr > 0) {
  746. unsigned long nr_zeros = __ffs64(cpu_addr);
  747. u64 alignment = 1ULL << nr_zeros;
  748. size = min(size, alignment);
  749. }
  750. /* Hardware supports max 4GiB inbound region */
  751. size = min(size, 1ULL << 32);
  752. mask = roundup_pow_of_two(size) - 1;
  753. mask &= ~0xf;
  754. rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
  755. lower_32_bits(mask) | flags, idx, true);
  756. pci_addr += size;
  757. cpu_addr += size;
  758. idx += 2;
  759. }
  760. *index = idx;
  761. return 0;
  762. }
  763. static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host)
  764. {
  765. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
  766. struct resource_entry *entry;
  767. int index = 0, err = 0;
  768. resource_list_for_each_entry(entry, &bridge->dma_ranges) {
  769. err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
  770. if (err)
  771. break;
  772. }
  773. return err;
  774. }
  775. static const struct of_device_id rcar_pcie_of_match[] = {
  776. { .compatible = "renesas,pcie-r8a7779",
  777. .data = rcar_pcie_phy_init_h1 },
  778. { .compatible = "renesas,pcie-r8a7790",
  779. .data = rcar_pcie_phy_init_gen2 },
  780. { .compatible = "renesas,pcie-r8a7791",
  781. .data = rcar_pcie_phy_init_gen2 },
  782. { .compatible = "renesas,pcie-rcar-gen2",
  783. .data = rcar_pcie_phy_init_gen2 },
  784. { .compatible = "renesas,pcie-r8a7795",
  785. .data = rcar_pcie_phy_init_gen3 },
  786. { .compatible = "renesas,pcie-rcar-gen3",
  787. .data = rcar_pcie_phy_init_gen3 },
  788. {},
  789. };
  790. static int rcar_pcie_probe(struct platform_device *pdev)
  791. {
  792. struct device *dev = &pdev->dev;
  793. struct rcar_pcie_host *host;
  794. struct rcar_pcie *pcie;
  795. u32 data;
  796. int err;
  797. struct pci_host_bridge *bridge;
  798. bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
  799. if (!bridge)
  800. return -ENOMEM;
  801. host = pci_host_bridge_priv(bridge);
  802. pcie = &host->pcie;
  803. pcie->dev = dev;
  804. platform_set_drvdata(pdev, host);
  805. pm_runtime_enable(pcie->dev);
  806. err = pm_runtime_get_sync(pcie->dev);
  807. if (err < 0) {
  808. dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
  809. goto err_pm_put;
  810. }
  811. err = rcar_pcie_get_resources(host);
  812. if (err < 0) {
  813. dev_err(dev, "failed to request resources: %d\n", err);
  814. goto err_pm_put;
  815. }
  816. err = clk_prepare_enable(host->bus_clk);
  817. if (err) {
  818. dev_err(dev, "failed to enable bus clock: %d\n", err);
  819. goto err_unmap_msi_irqs;
  820. }
  821. err = rcar_pcie_parse_map_dma_ranges(host);
  822. if (err)
  823. goto err_clk_disable;
  824. host->phy_init_fn = of_device_get_match_data(dev);
  825. err = host->phy_init_fn(host);
  826. if (err) {
  827. dev_err(dev, "failed to init PCIe PHY\n");
  828. goto err_clk_disable;
  829. }
  830. /* Failure to get a link might just be that no cards are inserted */
  831. if (rcar_pcie_hw_init(pcie)) {
  832. dev_info(dev, "PCIe link down\n");
  833. err = -ENODEV;
  834. goto err_phy_shutdown;
  835. }
  836. data = rcar_pci_read_reg(pcie, MACSR);
  837. dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
  838. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  839. err = rcar_pcie_enable_msi(host);
  840. if (err < 0) {
  841. dev_err(dev,
  842. "failed to enable MSI support: %d\n",
  843. err);
  844. goto err_phy_shutdown;
  845. }
  846. }
  847. err = rcar_pcie_enable(host);
  848. if (err)
  849. goto err_msi_teardown;
  850. return 0;
  851. err_msi_teardown:
  852. if (IS_ENABLED(CONFIG_PCI_MSI))
  853. rcar_pcie_teardown_msi(host);
  854. err_phy_shutdown:
  855. if (host->phy) {
  856. phy_power_off(host->phy);
  857. phy_exit(host->phy);
  858. }
  859. err_clk_disable:
  860. clk_disable_unprepare(host->bus_clk);
  861. err_unmap_msi_irqs:
  862. irq_dispose_mapping(host->msi.irq2);
  863. irq_dispose_mapping(host->msi.irq1);
  864. err_pm_put:
  865. pm_runtime_put(dev);
  866. pm_runtime_disable(dev);
  867. return err;
  868. }
  869. static int rcar_pcie_resume(struct device *dev)
  870. {
  871. struct rcar_pcie_host *host = dev_get_drvdata(dev);
  872. struct rcar_pcie *pcie = &host->pcie;
  873. unsigned int data;
  874. int err;
  875. err = rcar_pcie_parse_map_dma_ranges(host);
  876. if (err)
  877. return 0;
  878. /* Failure to get a link might just be that no cards are inserted */
  879. err = host->phy_init_fn(host);
  880. if (err) {
  881. dev_info(dev, "PCIe link down\n");
  882. return 0;
  883. }
  884. data = rcar_pci_read_reg(pcie, MACSR);
  885. dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
  886. /* Enable MSI */
  887. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  888. struct resource res;
  889. u32 val;
  890. of_address_to_resource(dev->of_node, 0, &res);
  891. rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
  892. rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
  893. bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
  894. rcar_pci_write_reg(pcie, val, PCIEMSIIER);
  895. }
  896. rcar_pcie_hw_enable(host);
  897. return 0;
  898. }
  899. static int rcar_pcie_resume_noirq(struct device *dev)
  900. {
  901. struct rcar_pcie_host *host = dev_get_drvdata(dev);
  902. struct rcar_pcie *pcie = &host->pcie;
  903. if (rcar_pci_read_reg(pcie, PMSR) &&
  904. !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
  905. return 0;
  906. /* Re-establish the PCIe link */
  907. rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
  908. rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
  909. return rcar_pcie_wait_for_dl(pcie);
  910. }
  911. static const struct dev_pm_ops rcar_pcie_pm_ops = {
  912. SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume)
  913. .resume_noirq = rcar_pcie_resume_noirq,
  914. };
  915. static struct platform_driver rcar_pcie_driver = {
  916. .driver = {
  917. .name = "rcar-pcie",
  918. .of_match_table = rcar_pcie_of_match,
  919. .pm = &rcar_pcie_pm_ops,
  920. .suppress_bind_attrs = true,
  921. },
  922. .probe = rcar_pcie_probe,
  923. };
  924. #ifdef CONFIG_ARM
  925. static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
  926. unsigned int fsr, struct pt_regs *regs)
  927. {
  928. return !fixup_exception(regs);
  929. }
  930. static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = {
  931. { .compatible = "renesas,pcie-r8a7779" },
  932. { .compatible = "renesas,pcie-r8a7790" },
  933. { .compatible = "renesas,pcie-r8a7791" },
  934. { .compatible = "renesas,pcie-rcar-gen2" },
  935. {},
  936. };
  937. static int __init rcar_pcie_init(void)
  938. {
  939. if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) {
  940. #ifdef CONFIG_ARM_LPAE
  941. hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
  942. "asynchronous external abort");
  943. #else
  944. hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
  945. "imprecise external abort");
  946. #endif
  947. }
  948. return platform_driver_register(&rcar_pcie_driver);
  949. }
  950. device_initcall(rcar_pcie_init);
  951. #else
  952. builtin_platform_driver(rcar_pcie_driver);
  953. #endif