pci-xgene.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * APM X-Gene PCIe Driver
  4. *
  5. * Copyright (c) 2014 Applied Micro Circuits Corporation.
  6. *
  7. * Author: Tanmay Inamdar <[email protected]>.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/memblock.h>
  14. #include <linux/init.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_pci.h>
  19. #include <linux/pci.h>
  20. #include <linux/pci-acpi.h>
  21. #include <linux/pci-ecam.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/slab.h>
  24. #include "../pci.h"
  25. #define PCIECORE_CTLANDSTATUS 0x50
  26. #define PIM1_1L 0x80
  27. #define IBAR2 0x98
  28. #define IR2MSK 0x9c
  29. #define PIM2_1L 0xa0
  30. #define IBAR3L 0xb4
  31. #define IR3MSKL 0xbc
  32. #define PIM3_1L 0xc4
  33. #define OMR1BARL 0x100
  34. #define OMR2BARL 0x118
  35. #define OMR3BARL 0x130
  36. #define CFGBARL 0x154
  37. #define CFGBARH 0x158
  38. #define CFGCTL 0x15c
  39. #define RTDID 0x160
  40. #define BRIDGE_CFG_0 0x2000
  41. #define BRIDGE_CFG_4 0x2010
  42. #define BRIDGE_STATUS_0 0x2600
  43. #define LINK_UP_MASK 0x00000100
  44. #define AXI_EP_CFG_ACCESS 0x10000
  45. #define EN_COHERENCY 0xF0000000
  46. #define EN_REG 0x00000001
  47. #define OB_LO_IO 0x00000002
  48. #define XGENE_PCIE_DEVICEID 0xE004
  49. #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
  50. #define XGENE_V1_PCI_EXP_CAP 0x40
  51. /* PCIe IP version */
  52. #define XGENE_PCIE_IP_VER_UNKN 0
  53. #define XGENE_PCIE_IP_VER_1 1
  54. #define XGENE_PCIE_IP_VER_2 2
  55. #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
  56. struct xgene_pcie {
  57. struct device_node *node;
  58. struct device *dev;
  59. struct clk *clk;
  60. void __iomem *csr_base;
  61. void __iomem *cfg_base;
  62. unsigned long cfg_addr;
  63. bool link_up;
  64. u32 version;
  65. };
  66. static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)
  67. {
  68. return readl(port->csr_base + reg);
  69. }
  70. static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)
  71. {
  72. writel(val, port->csr_base + reg);
  73. }
  74. static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
  75. {
  76. return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
  77. }
  78. static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus)
  79. {
  80. struct pci_config_window *cfg;
  81. if (acpi_disabled)
  82. return (struct xgene_pcie *)(bus->sysdata);
  83. cfg = bus->sysdata;
  84. return (struct xgene_pcie *)(cfg->priv);
  85. }
  86. /*
  87. * When the address bit [17:16] is 2'b01, the Configuration access will be
  88. * treated as Type 1 and it will be forwarded to external PCIe device.
  89. */
  90. static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
  91. {
  92. struct xgene_pcie *port = pcie_bus_to_port(bus);
  93. if (bus->number >= (bus->primary + 1))
  94. return port->cfg_base + AXI_EP_CFG_ACCESS;
  95. return port->cfg_base;
  96. }
  97. /*
  98. * For Configuration request, RTDID register is used as Bus Number,
  99. * Device Number and Function number of the header fields.
  100. */
  101. static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
  102. {
  103. struct xgene_pcie *port = pcie_bus_to_port(bus);
  104. unsigned int b, d, f;
  105. u32 rtdid_val = 0;
  106. b = bus->number;
  107. d = PCI_SLOT(devfn);
  108. f = PCI_FUNC(devfn);
  109. if (!pci_is_root_bus(bus))
  110. rtdid_val = (b << 8) | (d << 3) | f;
  111. xgene_pcie_writel(port, RTDID, rtdid_val);
  112. /* read the register back to ensure flush */
  113. xgene_pcie_readl(port, RTDID);
  114. }
  115. /*
  116. * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
  117. * the translation from PCI bus to native BUS. Entire DDR region
  118. * is mapped into PCIe space using these registers, so it can be
  119. * reached by DMA from EP devices. The BAR0/1 of bridge should be
  120. * hidden during enumeration to avoid the sizing and resource allocation
  121. * by PCIe core.
  122. */
  123. static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
  124. {
  125. if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
  126. (offset == PCI_BASE_ADDRESS_1)))
  127. return true;
  128. return false;
  129. }
  130. static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
  131. int offset)
  132. {
  133. if ((pci_is_root_bus(bus) && devfn != 0) ||
  134. xgene_pcie_hide_rc_bars(bus, offset))
  135. return NULL;
  136. xgene_pcie_set_rtdid_reg(bus, devfn);
  137. return xgene_pcie_get_cfg_base(bus) + offset;
  138. }
  139. static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
  140. int where, int size, u32 *val)
  141. {
  142. struct xgene_pcie *port = pcie_bus_to_port(bus);
  143. if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
  144. PCIBIOS_SUCCESSFUL)
  145. return PCIBIOS_DEVICE_NOT_FOUND;
  146. /*
  147. * The v1 controller has a bug in its Configuration Request Retry
  148. * Status (CRS) logic: when CRS Software Visibility is enabled and
  149. * we read the Vendor and Device ID of a non-existent device, the
  150. * controller fabricates return data of 0xFFFF0001 ("device exists
  151. * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE)
  152. * ("device does not exist"). This causes the PCI core to retry
  153. * the read until it times out. Avoid this by not claiming to
  154. * support CRS SV.
  155. */
  156. if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
  157. ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
  158. *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
  159. if (size <= 2)
  160. *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
  161. return PCIBIOS_SUCCESSFUL;
  162. }
  163. #endif
  164. #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
  165. static int xgene_get_csr_resource(struct acpi_device *adev,
  166. struct resource *res)
  167. {
  168. struct device *dev = &adev->dev;
  169. struct resource_entry *entry;
  170. struct list_head list;
  171. unsigned long flags;
  172. int ret;
  173. INIT_LIST_HEAD(&list);
  174. flags = IORESOURCE_MEM;
  175. ret = acpi_dev_get_resources(adev, &list,
  176. acpi_dev_filter_resource_type_cb,
  177. (void *) flags);
  178. if (ret < 0) {
  179. dev_err(dev, "failed to parse _CRS method, error code %d\n",
  180. ret);
  181. return ret;
  182. }
  183. if (ret == 0) {
  184. dev_err(dev, "no IO and memory resources present in _CRS\n");
  185. return -EINVAL;
  186. }
  187. entry = list_first_entry(&list, struct resource_entry, node);
  188. *res = *entry->res;
  189. acpi_dev_free_resource_list(&list);
  190. return 0;
  191. }
  192. static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
  193. {
  194. struct device *dev = cfg->parent;
  195. struct acpi_device *adev = to_acpi_device(dev);
  196. struct xgene_pcie *port;
  197. struct resource csr;
  198. int ret;
  199. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  200. if (!port)
  201. return -ENOMEM;
  202. ret = xgene_get_csr_resource(adev, &csr);
  203. if (ret) {
  204. dev_err(dev, "can't get CSR resource\n");
  205. return ret;
  206. }
  207. port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
  208. if (IS_ERR(port->csr_base))
  209. return PTR_ERR(port->csr_base);
  210. port->cfg_base = cfg->win;
  211. port->version = ipversion;
  212. cfg->priv = port;
  213. return 0;
  214. }
  215. static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
  216. {
  217. return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
  218. }
  219. const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
  220. .init = xgene_v1_pcie_ecam_init,
  221. .pci_ops = {
  222. .map_bus = xgene_pcie_map_bus,
  223. .read = xgene_pcie_config_read32,
  224. .write = pci_generic_config_write,
  225. }
  226. };
  227. static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
  228. {
  229. return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
  230. }
  231. const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
  232. .init = xgene_v2_pcie_ecam_init,
  233. .pci_ops = {
  234. .map_bus = xgene_pcie_map_bus,
  235. .read = xgene_pcie_config_read32,
  236. .write = pci_generic_config_write,
  237. }
  238. };
  239. #endif
  240. #if defined(CONFIG_PCI_XGENE)
  241. static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,
  242. u32 flags, u64 size)
  243. {
  244. u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
  245. u32 val32 = 0;
  246. u32 val;
  247. val32 = xgene_pcie_readl(port, addr);
  248. val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
  249. xgene_pcie_writel(port, addr, val);
  250. val32 = xgene_pcie_readl(port, addr + 0x04);
  251. val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
  252. xgene_pcie_writel(port, addr + 0x04, val);
  253. val32 = xgene_pcie_readl(port, addr + 0x04);
  254. val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
  255. xgene_pcie_writel(port, addr + 0x04, val);
  256. val32 = xgene_pcie_readl(port, addr + 0x08);
  257. val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
  258. xgene_pcie_writel(port, addr + 0x08, val);
  259. return mask;
  260. }
  261. static void xgene_pcie_linkup(struct xgene_pcie *port,
  262. u32 *lanes, u32 *speed)
  263. {
  264. u32 val32;
  265. port->link_up = false;
  266. val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
  267. if (val32 & LINK_UP_MASK) {
  268. port->link_up = true;
  269. *speed = PIPE_PHY_RATE_RD(val32);
  270. val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
  271. *lanes = val32 >> 26;
  272. }
  273. }
  274. static int xgene_pcie_init_port(struct xgene_pcie *port)
  275. {
  276. struct device *dev = port->dev;
  277. int rc;
  278. port->clk = clk_get(dev, NULL);
  279. if (IS_ERR(port->clk)) {
  280. dev_err(dev, "clock not available\n");
  281. return -ENODEV;
  282. }
  283. rc = clk_prepare_enable(port->clk);
  284. if (rc) {
  285. dev_err(dev, "clock enable failed\n");
  286. return rc;
  287. }
  288. return 0;
  289. }
  290. static int xgene_pcie_map_reg(struct xgene_pcie *port,
  291. struct platform_device *pdev)
  292. {
  293. struct device *dev = port->dev;
  294. struct resource *res;
  295. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
  296. port->csr_base = devm_pci_remap_cfg_resource(dev, res);
  297. if (IS_ERR(port->csr_base))
  298. return PTR_ERR(port->csr_base);
  299. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
  300. port->cfg_base = devm_ioremap_resource(dev, res);
  301. if (IS_ERR(port->cfg_base))
  302. return PTR_ERR(port->cfg_base);
  303. port->cfg_addr = res->start;
  304. return 0;
  305. }
  306. static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,
  307. struct resource *res, u32 offset,
  308. u64 cpu_addr, u64 pci_addr)
  309. {
  310. struct device *dev = port->dev;
  311. resource_size_t size = resource_size(res);
  312. u64 restype = resource_type(res);
  313. u64 mask = 0;
  314. u32 min_size;
  315. u32 flag = EN_REG;
  316. if (restype == IORESOURCE_MEM) {
  317. min_size = SZ_128M;
  318. } else {
  319. min_size = 128;
  320. flag |= OB_LO_IO;
  321. }
  322. if (size >= min_size)
  323. mask = ~(size - 1) | flag;
  324. else
  325. dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
  326. (u64)size, min_size);
  327. xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
  328. xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
  329. xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
  330. xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
  331. xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
  332. xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
  333. }
  334. static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)
  335. {
  336. u64 addr = port->cfg_addr;
  337. xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
  338. xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
  339. xgene_pcie_writel(port, CFGCTL, EN_REG);
  340. }
  341. static int xgene_pcie_map_ranges(struct xgene_pcie *port)
  342. {
  343. struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
  344. struct resource_entry *window;
  345. struct device *dev = port->dev;
  346. resource_list_for_each_entry(window, &bridge->windows) {
  347. struct resource *res = window->res;
  348. u64 restype = resource_type(res);
  349. dev_dbg(dev, "%pR\n", res);
  350. switch (restype) {
  351. case IORESOURCE_IO:
  352. xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
  353. pci_pio_to_address(res->start),
  354. res->start - window->offset);
  355. break;
  356. case IORESOURCE_MEM:
  357. if (res->flags & IORESOURCE_PREFETCH)
  358. xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
  359. res->start,
  360. res->start -
  361. window->offset);
  362. else
  363. xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
  364. res->start,
  365. res->start -
  366. window->offset);
  367. break;
  368. case IORESOURCE_BUS:
  369. break;
  370. default:
  371. dev_err(dev, "invalid resource %pR\n", res);
  372. return -EINVAL;
  373. }
  374. }
  375. xgene_pcie_setup_cfg_reg(port);
  376. return 0;
  377. }
  378. static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,
  379. u64 pim, u64 size)
  380. {
  381. xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
  382. xgene_pcie_writel(port, pim_reg + 0x04,
  383. upper_32_bits(pim) | EN_COHERENCY);
  384. xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
  385. xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
  386. }
  387. /*
  388. * X-Gene PCIe support maximum 3 inbound memory regions
  389. * This function helps to select a region based on size of region
  390. */
  391. static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
  392. {
  393. if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
  394. *ib_reg_mask |= (1 << 1);
  395. return 1;
  396. }
  397. if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
  398. *ib_reg_mask |= (1 << 0);
  399. return 0;
  400. }
  401. if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
  402. *ib_reg_mask |= (1 << 2);
  403. return 2;
  404. }
  405. return -EINVAL;
  406. }
  407. static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,
  408. struct of_pci_range *range, u8 *ib_reg_mask)
  409. {
  410. void __iomem *cfg_base = port->cfg_base;
  411. struct device *dev = port->dev;
  412. void __iomem *bar_addr;
  413. u32 pim_reg;
  414. u64 cpu_addr = range->cpu_addr;
  415. u64 pci_addr = range->pci_addr;
  416. u64 size = range->size;
  417. u64 mask = ~(size - 1) | EN_REG;
  418. u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
  419. u32 bar_low;
  420. int region;
  421. region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
  422. if (region < 0) {
  423. dev_warn(dev, "invalid pcie dma-range config\n");
  424. return;
  425. }
  426. if (range->flags & IORESOURCE_PREFETCH)
  427. flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
  428. bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
  429. switch (region) {
  430. case 0:
  431. xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
  432. bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
  433. writel(bar_low, bar_addr);
  434. writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
  435. pim_reg = PIM1_1L;
  436. break;
  437. case 1:
  438. xgene_pcie_writel(port, IBAR2, bar_low);
  439. xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
  440. pim_reg = PIM2_1L;
  441. break;
  442. case 2:
  443. xgene_pcie_writel(port, IBAR3L, bar_low);
  444. xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
  445. xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
  446. xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
  447. pim_reg = PIM3_1L;
  448. break;
  449. }
  450. xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
  451. }
  452. static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)
  453. {
  454. struct device_node *np = port->node;
  455. struct of_pci_range range;
  456. struct of_pci_range_parser parser;
  457. struct device *dev = port->dev;
  458. u8 ib_reg_mask = 0;
  459. if (of_pci_dma_range_parser_init(&parser, np)) {
  460. dev_err(dev, "missing dma-ranges property\n");
  461. return -EINVAL;
  462. }
  463. /* Get the dma-ranges from DT */
  464. for_each_of_pci_range(&parser, &range) {
  465. u64 end = range.cpu_addr + range.size - 1;
  466. dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
  467. range.flags, range.cpu_addr, end, range.pci_addr);
  468. xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
  469. }
  470. return 0;
  471. }
  472. /* clear BAR configuration which was done by firmware */
  473. static void xgene_pcie_clear_config(struct xgene_pcie *port)
  474. {
  475. int i;
  476. for (i = PIM1_1L; i <= CFGCTL; i += 4)
  477. xgene_pcie_writel(port, i, 0);
  478. }
  479. static int xgene_pcie_setup(struct xgene_pcie *port)
  480. {
  481. struct device *dev = port->dev;
  482. u32 val, lanes = 0, speed = 0;
  483. int ret;
  484. xgene_pcie_clear_config(port);
  485. /* setup the vendor and device IDs correctly */
  486. val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC;
  487. xgene_pcie_writel(port, BRIDGE_CFG_0, val);
  488. ret = xgene_pcie_map_ranges(port);
  489. if (ret)
  490. return ret;
  491. ret = xgene_pcie_parse_map_dma_ranges(port);
  492. if (ret)
  493. return ret;
  494. xgene_pcie_linkup(port, &lanes, &speed);
  495. if (!port->link_up)
  496. dev_info(dev, "(rc) link down\n");
  497. else
  498. dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
  499. return 0;
  500. }
  501. static struct pci_ops xgene_pcie_ops = {
  502. .map_bus = xgene_pcie_map_bus,
  503. .read = xgene_pcie_config_read32,
  504. .write = pci_generic_config_write32,
  505. };
  506. static int xgene_pcie_probe(struct platform_device *pdev)
  507. {
  508. struct device *dev = &pdev->dev;
  509. struct device_node *dn = dev->of_node;
  510. struct xgene_pcie *port;
  511. struct pci_host_bridge *bridge;
  512. int ret;
  513. bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
  514. if (!bridge)
  515. return -ENOMEM;
  516. port = pci_host_bridge_priv(bridge);
  517. port->node = of_node_get(dn);
  518. port->dev = dev;
  519. port->version = XGENE_PCIE_IP_VER_UNKN;
  520. if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
  521. port->version = XGENE_PCIE_IP_VER_1;
  522. ret = xgene_pcie_map_reg(port, pdev);
  523. if (ret)
  524. return ret;
  525. ret = xgene_pcie_init_port(port);
  526. if (ret)
  527. return ret;
  528. ret = xgene_pcie_setup(port);
  529. if (ret)
  530. return ret;
  531. bridge->sysdata = port;
  532. bridge->ops = &xgene_pcie_ops;
  533. return pci_host_probe(bridge);
  534. }
  535. static const struct of_device_id xgene_pcie_match_table[] = {
  536. {.compatible = "apm,xgene-pcie",},
  537. {},
  538. };
  539. static struct platform_driver xgene_pcie_driver = {
  540. .driver = {
  541. .name = "xgene-pcie",
  542. .of_match_table = xgene_pcie_match_table,
  543. .suppress_bind_attrs = true,
  544. },
  545. .probe = xgene_pcie_probe,
  546. };
  547. builtin_platform_driver(xgene_pcie_driver);
  548. #endif