pci-versatile.c 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2004 Koninklijke Philips Electronics NV
  4. *
  5. * Conversion to platform driver and DT:
  6. * Copyright 2014 Linaro Ltd.
  7. *
  8. * 14/04/2005 Initial version, [email protected]
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_pci.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/pci.h>
  16. #include <linux/platform_device.h>
  17. #include "../pci.h"
  18. static void __iomem *versatile_pci_base;
  19. static void __iomem *versatile_cfg_base[2];
  20. #define PCI_IMAP(m) (versatile_pci_base + ((m) * 4))
  21. #define PCI_SMAP(m) (versatile_pci_base + 0x14 + ((m) * 4))
  22. #define PCI_SELFID (versatile_pci_base + 0xc)
  23. #define VP_PCI_DEVICE_ID 0x030010ee
  24. #define VP_PCI_CLASS_ID 0x0b400000
  25. static u32 pci_slot_ignore;
  26. static int __init versatile_pci_slot_ignore(char *str)
  27. {
  28. int slot;
  29. while (get_option(&str, &slot)) {
  30. if ((slot < 0) || (slot > 31))
  31. pr_err("Illegal slot value: %d\n", slot);
  32. else
  33. pci_slot_ignore |= (1 << slot);
  34. }
  35. return 1;
  36. }
  37. __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
  38. static void __iomem *versatile_map_bus(struct pci_bus *bus,
  39. unsigned int devfn, int offset)
  40. {
  41. unsigned int busnr = bus->number;
  42. if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
  43. return NULL;
  44. return versatile_cfg_base[1] + ((busnr << 16) | (devfn << 8) | offset);
  45. }
  46. static struct pci_ops pci_versatile_ops = {
  47. .map_bus = versatile_map_bus,
  48. .read = pci_generic_config_read32,
  49. .write = pci_generic_config_write,
  50. };
  51. static int versatile_pci_probe(struct platform_device *pdev)
  52. {
  53. struct device *dev = &pdev->dev;
  54. struct resource *res;
  55. struct resource_entry *entry;
  56. int i, myslot = -1, mem = 1;
  57. u32 val;
  58. void __iomem *local_pci_cfg_base;
  59. struct pci_host_bridge *bridge;
  60. bridge = devm_pci_alloc_host_bridge(dev, 0);
  61. if (!bridge)
  62. return -ENOMEM;
  63. versatile_pci_base = devm_platform_ioremap_resource(pdev, 0);
  64. if (IS_ERR(versatile_pci_base))
  65. return PTR_ERR(versatile_pci_base);
  66. versatile_cfg_base[0] = devm_platform_ioremap_resource(pdev, 1);
  67. if (IS_ERR(versatile_cfg_base[0]))
  68. return PTR_ERR(versatile_cfg_base[0]);
  69. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  70. versatile_cfg_base[1] = devm_pci_remap_cfg_resource(dev, res);
  71. if (IS_ERR(versatile_cfg_base[1]))
  72. return PTR_ERR(versatile_cfg_base[1]);
  73. resource_list_for_each_entry(entry, &bridge->windows) {
  74. if (resource_type(entry->res) == IORESOURCE_MEM) {
  75. writel(entry->res->start >> 28, PCI_IMAP(mem));
  76. writel(__pa(PAGE_OFFSET) >> 28, PCI_SMAP(mem));
  77. mem++;
  78. }
  79. }
  80. /*
  81. * We need to discover the PCI core first to configure itself
  82. * before the main PCI probing is performed
  83. */
  84. for (i = 0; i < 32; i++) {
  85. if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
  86. (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
  87. myslot = i;
  88. break;
  89. }
  90. }
  91. if (myslot == -1) {
  92. dev_err(dev, "Cannot find PCI core!\n");
  93. return -EIO;
  94. }
  95. /*
  96. * Do not to map Versatile FPGA PCI device into memory space
  97. */
  98. pci_slot_ignore |= (1 << myslot);
  99. dev_info(dev, "PCI core found (slot %d)\n", myslot);
  100. writel(myslot, PCI_SELFID);
  101. local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);
  102. val = readl(local_pci_cfg_base + PCI_COMMAND);
  103. val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
  104. writel(val, local_pci_cfg_base + PCI_COMMAND);
  105. /*
  106. * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
  107. */
  108. writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_0);
  109. writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_1);
  110. writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_2);
  111. /*
  112. * For many years the kernel and QEMU were symbiotically buggy
  113. * in that they both assumed the same broken IRQ mapping.
  114. * QEMU therefore attempts to auto-detect old broken kernels
  115. * so that they still work on newer QEMU as they did on old
  116. * QEMU. Since we now use the correct (ie matching-hardware)
  117. * IRQ mapping we write a definitely different value to a
  118. * PCI_INTERRUPT_LINE register to tell QEMU that we expect
  119. * real hardware behaviour and it need not be backwards
  120. * compatible for us. This write is harmless on real hardware.
  121. */
  122. writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
  123. pci_add_flags(PCI_REASSIGN_ALL_BUS);
  124. bridge->ops = &pci_versatile_ops;
  125. return pci_host_probe(bridge);
  126. }
  127. static const struct of_device_id versatile_pci_of_match[] = {
  128. { .compatible = "arm,versatile-pci", },
  129. { },
  130. };
  131. MODULE_DEVICE_TABLE(of, versatile_pci_of_match);
  132. static struct platform_driver versatile_pci_driver = {
  133. .driver = {
  134. .name = "versatile-pci",
  135. .of_match_table = versatile_pci_of_match,
  136. .suppress_bind_attrs = true,
  137. },
  138. .probe = versatile_pci_probe,
  139. };
  140. module_platform_driver(versatile_pci_driver);
  141. MODULE_DESCRIPTION("Versatile PCI driver");
  142. MODULE_LICENSE("GPL v2");