pcie-cadence-plat.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Cadence PCIe platform driver.
  4. *
  5. * Copyright (c) 2019, Cadence Design Systems
  6. * Author: Tom Joseph <[email protected]>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_pci.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/of_device.h>
  14. #include "pcie-cadence.h"
  15. #define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF
  16. /**
  17. * struct cdns_plat_pcie - private data for this PCIe platform driver
  18. * @pcie: Cadence PCIe controller
  19. * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
  20. * if 0 it is in Endpoint mode.
  21. */
  22. struct cdns_plat_pcie {
  23. struct cdns_pcie *pcie;
  24. bool is_rc;
  25. };
  26. struct cdns_plat_pcie_of_data {
  27. bool is_rc;
  28. };
  29. static const struct of_device_id cdns_plat_pcie_of_match[];
  30. static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
  31. {
  32. return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
  33. }
  34. static const struct cdns_pcie_ops cdns_plat_ops = {
  35. .cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
  36. };
  37. static int cdns_plat_pcie_probe(struct platform_device *pdev)
  38. {
  39. const struct cdns_plat_pcie_of_data *data;
  40. struct cdns_plat_pcie *cdns_plat_pcie;
  41. struct device *dev = &pdev->dev;
  42. struct pci_host_bridge *bridge;
  43. struct cdns_pcie_ep *ep;
  44. struct cdns_pcie_rc *rc;
  45. int phy_count;
  46. bool is_rc;
  47. int ret;
  48. data = of_device_get_match_data(dev);
  49. if (!data)
  50. return -EINVAL;
  51. is_rc = data->is_rc;
  52. pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc);
  53. cdns_plat_pcie = devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL);
  54. if (!cdns_plat_pcie)
  55. return -ENOMEM;
  56. platform_set_drvdata(pdev, cdns_plat_pcie);
  57. if (is_rc) {
  58. if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST))
  59. return -ENODEV;
  60. bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
  61. if (!bridge)
  62. return -ENOMEM;
  63. rc = pci_host_bridge_priv(bridge);
  64. rc->pcie.dev = dev;
  65. rc->pcie.ops = &cdns_plat_ops;
  66. cdns_plat_pcie->pcie = &rc->pcie;
  67. cdns_plat_pcie->is_rc = is_rc;
  68. ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
  69. if (ret) {
  70. dev_err(dev, "failed to init phy\n");
  71. return ret;
  72. }
  73. pm_runtime_enable(dev);
  74. ret = pm_runtime_get_sync(dev);
  75. if (ret < 0) {
  76. dev_err(dev, "pm_runtime_get_sync() failed\n");
  77. goto err_get_sync;
  78. }
  79. ret = cdns_pcie_host_setup(rc);
  80. if (ret)
  81. goto err_init;
  82. } else {
  83. if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP))
  84. return -ENODEV;
  85. ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
  86. if (!ep)
  87. return -ENOMEM;
  88. ep->pcie.dev = dev;
  89. ep->pcie.ops = &cdns_plat_ops;
  90. cdns_plat_pcie->pcie = &ep->pcie;
  91. cdns_plat_pcie->is_rc = is_rc;
  92. ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
  93. if (ret) {
  94. dev_err(dev, "failed to init phy\n");
  95. return ret;
  96. }
  97. pm_runtime_enable(dev);
  98. ret = pm_runtime_get_sync(dev);
  99. if (ret < 0) {
  100. dev_err(dev, "pm_runtime_get_sync() failed\n");
  101. goto err_get_sync;
  102. }
  103. ret = cdns_pcie_ep_setup(ep);
  104. if (ret)
  105. goto err_init;
  106. }
  107. return 0;
  108. err_init:
  109. err_get_sync:
  110. pm_runtime_put_sync(dev);
  111. pm_runtime_disable(dev);
  112. cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
  113. phy_count = cdns_plat_pcie->pcie->phy_count;
  114. while (phy_count--)
  115. device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
  116. return 0;
  117. }
  118. static void cdns_plat_pcie_shutdown(struct platform_device *pdev)
  119. {
  120. struct device *dev = &pdev->dev;
  121. struct cdns_pcie *pcie = dev_get_drvdata(dev);
  122. int ret;
  123. ret = pm_runtime_put_sync(dev);
  124. if (ret < 0)
  125. dev_dbg(dev, "pm_runtime_put_sync failed\n");
  126. pm_runtime_disable(dev);
  127. cdns_pcie_disable_phy(pcie);
  128. }
  129. static const struct cdns_plat_pcie_of_data cdns_plat_pcie_host_of_data = {
  130. .is_rc = true,
  131. };
  132. static const struct cdns_plat_pcie_of_data cdns_plat_pcie_ep_of_data = {
  133. .is_rc = false,
  134. };
  135. static const struct of_device_id cdns_plat_pcie_of_match[] = {
  136. {
  137. .compatible = "cdns,cdns-pcie-host",
  138. .data = &cdns_plat_pcie_host_of_data,
  139. },
  140. {
  141. .compatible = "cdns,cdns-pcie-ep",
  142. .data = &cdns_plat_pcie_ep_of_data,
  143. },
  144. {},
  145. };
  146. static struct platform_driver cdns_plat_pcie_driver = {
  147. .driver = {
  148. .name = "cdns-pcie",
  149. .of_match_table = cdns_plat_pcie_of_match,
  150. .pm = &cdns_pcie_pm_ops,
  151. },
  152. .probe = cdns_plat_pcie_probe,
  153. .shutdown = cdns_plat_pcie_shutdown,
  154. };
  155. builtin_platform_driver(cdns_plat_pcie_driver);