mrf24j40.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
  4. *
  5. * Copyright (C) 2012 Alan Ott <[email protected]>
  6. * Signal 11 Software
  7. */
  8. #include <linux/spi/spi.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/mod_devicetable.h>
  11. #include <linux/module.h>
  12. #include <linux/regmap.h>
  13. #include <linux/ieee802154.h>
  14. #include <linux/irq.h>
  15. #include <net/cfg802154.h>
  16. #include <net/mac802154.h>
  17. /* MRF24J40 Short Address Registers */
  18. #define REG_RXMCR 0x00 /* Receive MAC control */
  19. #define BIT_PROMI BIT(0)
  20. #define BIT_ERRPKT BIT(1)
  21. #define BIT_NOACKRSP BIT(5)
  22. #define BIT_PANCOORD BIT(3)
  23. #define REG_PANIDL 0x01 /* PAN ID (low) */
  24. #define REG_PANIDH 0x02 /* PAN ID (high) */
  25. #define REG_SADRL 0x03 /* Short address (low) */
  26. #define REG_SADRH 0x04 /* Short address (high) */
  27. #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
  28. #define REG_EADR1 0x06
  29. #define REG_EADR2 0x07
  30. #define REG_EADR3 0x08
  31. #define REG_EADR4 0x09
  32. #define REG_EADR5 0x0A
  33. #define REG_EADR6 0x0B
  34. #define REG_EADR7 0x0C
  35. #define REG_RXFLUSH 0x0D
  36. #define REG_ORDER 0x10
  37. #define REG_TXMCR 0x11 /* Transmit MAC control */
  38. #define TXMCR_MIN_BE_SHIFT 3
  39. #define TXMCR_MIN_BE_MASK 0x18
  40. #define TXMCR_CSMA_RETRIES_SHIFT 0
  41. #define TXMCR_CSMA_RETRIES_MASK 0x07
  42. #define REG_ACKTMOUT 0x12
  43. #define REG_ESLOTG1 0x13
  44. #define REG_SYMTICKL 0x14
  45. #define REG_SYMTICKH 0x15
  46. #define REG_PACON0 0x16 /* Power Amplifier Control */
  47. #define REG_PACON1 0x17 /* Power Amplifier Control */
  48. #define REG_PACON2 0x18 /* Power Amplifier Control */
  49. #define REG_TXBCON0 0x1A
  50. #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
  51. #define BIT_TXNTRIG BIT(0)
  52. #define BIT_TXNSECEN BIT(1)
  53. #define BIT_TXNACKREQ BIT(2)
  54. #define REG_TXG1CON 0x1C
  55. #define REG_TXG2CON 0x1D
  56. #define REG_ESLOTG23 0x1E
  57. #define REG_ESLOTG45 0x1F
  58. #define REG_ESLOTG67 0x20
  59. #define REG_TXPEND 0x21
  60. #define REG_WAKECON 0x22
  61. #define REG_FROMOFFSET 0x23
  62. #define REG_TXSTAT 0x24 /* TX MAC Status Register */
  63. #define REG_TXBCON1 0x25
  64. #define REG_GATECLK 0x26
  65. #define REG_TXTIME 0x27
  66. #define REG_HSYMTMRL 0x28
  67. #define REG_HSYMTMRH 0x29
  68. #define REG_SOFTRST 0x2A /* Soft Reset */
  69. #define REG_SECCON0 0x2C
  70. #define REG_SECCON1 0x2D
  71. #define REG_TXSTBL 0x2E /* TX Stabilization */
  72. #define REG_RXSR 0x30
  73. #define REG_INTSTAT 0x31 /* Interrupt Status */
  74. #define BIT_TXNIF BIT(0)
  75. #define BIT_RXIF BIT(3)
  76. #define BIT_SECIF BIT(4)
  77. #define BIT_SECIGNORE BIT(7)
  78. #define REG_INTCON 0x32 /* Interrupt Control */
  79. #define BIT_TXNIE BIT(0)
  80. #define BIT_RXIE BIT(3)
  81. #define BIT_SECIE BIT(4)
  82. #define REG_GPIO 0x33 /* GPIO */
  83. #define REG_TRISGPIO 0x34 /* GPIO direction */
  84. #define REG_SLPACK 0x35
  85. #define REG_RFCTL 0x36 /* RF Control Mode Register */
  86. #define BIT_RFRST BIT(2)
  87. #define REG_SECCR2 0x37
  88. #define REG_BBREG0 0x38
  89. #define REG_BBREG1 0x39 /* Baseband Registers */
  90. #define BIT_RXDECINV BIT(2)
  91. #define REG_BBREG2 0x3A /* */
  92. #define BBREG2_CCA_MODE_SHIFT 6
  93. #define BBREG2_CCA_MODE_MASK 0xc0
  94. #define REG_BBREG3 0x3B
  95. #define REG_BBREG4 0x3C
  96. #define REG_BBREG6 0x3E /* */
  97. #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
  98. /* MRF24J40 Long Address Registers */
  99. #define REG_RFCON0 0x200 /* RF Control Registers */
  100. #define RFCON0_CH_SHIFT 4
  101. #define RFCON0_CH_MASK 0xf0
  102. #define RFOPT_RECOMMEND 3
  103. #define REG_RFCON1 0x201
  104. #define REG_RFCON2 0x202
  105. #define REG_RFCON3 0x203
  106. #define TXPWRL_MASK 0xc0
  107. #define TXPWRL_SHIFT 6
  108. #define TXPWRL_30 0x3
  109. #define TXPWRL_20 0x2
  110. #define TXPWRL_10 0x1
  111. #define TXPWRL_0 0x0
  112. #define TXPWRS_MASK 0x38
  113. #define TXPWRS_SHIFT 3
  114. #define TXPWRS_6_3 0x7
  115. #define TXPWRS_4_9 0x6
  116. #define TXPWRS_3_7 0x5
  117. #define TXPWRS_2_8 0x4
  118. #define TXPWRS_1_9 0x3
  119. #define TXPWRS_1_2 0x2
  120. #define TXPWRS_0_5 0x1
  121. #define TXPWRS_0 0x0
  122. #define REG_RFCON5 0x205
  123. #define REG_RFCON6 0x206
  124. #define REG_RFCON7 0x207
  125. #define REG_RFCON8 0x208
  126. #define REG_SLPCAL0 0x209
  127. #define REG_SLPCAL1 0x20A
  128. #define REG_SLPCAL2 0x20B
  129. #define REG_RFSTATE 0x20F
  130. #define REG_RSSI 0x210
  131. #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
  132. #define BIT_INTEDGE BIT(1)
  133. #define REG_SLPCON1 0x220
  134. #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
  135. #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
  136. #define REG_REMCNTL 0x224
  137. #define REG_REMCNTH 0x225
  138. #define REG_MAINCNT0 0x226
  139. #define REG_MAINCNT1 0x227
  140. #define REG_MAINCNT2 0x228
  141. #define REG_MAINCNT3 0x229
  142. #define REG_TESTMODE 0x22F /* Test mode */
  143. #define REG_ASSOEAR0 0x230
  144. #define REG_ASSOEAR1 0x231
  145. #define REG_ASSOEAR2 0x232
  146. #define REG_ASSOEAR3 0x233
  147. #define REG_ASSOEAR4 0x234
  148. #define REG_ASSOEAR5 0x235
  149. #define REG_ASSOEAR6 0x236
  150. #define REG_ASSOEAR7 0x237
  151. #define REG_ASSOSAR0 0x238
  152. #define REG_ASSOSAR1 0x239
  153. #define REG_UNONCE0 0x240
  154. #define REG_UNONCE1 0x241
  155. #define REG_UNONCE2 0x242
  156. #define REG_UNONCE3 0x243
  157. #define REG_UNONCE4 0x244
  158. #define REG_UNONCE5 0x245
  159. #define REG_UNONCE6 0x246
  160. #define REG_UNONCE7 0x247
  161. #define REG_UNONCE8 0x248
  162. #define REG_UNONCE9 0x249
  163. #define REG_UNONCE10 0x24A
  164. #define REG_UNONCE11 0x24B
  165. #define REG_UNONCE12 0x24C
  166. #define REG_RX_FIFO 0x300 /* Receive FIFO */
  167. /* Device configuration: Only channels 11-26 on page 0 are supported. */
  168. #define MRF24J40_CHAN_MIN 11
  169. #define MRF24J40_CHAN_MAX 26
  170. #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
  171. - ((u32)1 << MRF24J40_CHAN_MIN))
  172. #define TX_FIFO_SIZE 128 /* From datasheet */
  173. #define RX_FIFO_SIZE 144 /* From datasheet */
  174. #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
  175. enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
  176. /* Device Private Data */
  177. struct mrf24j40 {
  178. struct spi_device *spi;
  179. struct ieee802154_hw *hw;
  180. struct regmap *regmap_short;
  181. struct regmap *regmap_long;
  182. /* for writing txfifo */
  183. struct spi_message tx_msg;
  184. u8 tx_hdr_buf[2];
  185. struct spi_transfer tx_hdr_trx;
  186. u8 tx_len_buf[2];
  187. struct spi_transfer tx_len_trx;
  188. struct spi_transfer tx_buf_trx;
  189. struct sk_buff *tx_skb;
  190. /* post transmit message to send frame out */
  191. struct spi_message tx_post_msg;
  192. u8 tx_post_buf[2];
  193. struct spi_transfer tx_post_trx;
  194. /* for protect/unprotect/read length rxfifo */
  195. struct spi_message rx_msg;
  196. u8 rx_buf[3];
  197. struct spi_transfer rx_trx;
  198. /* receive handling */
  199. struct spi_message rx_buf_msg;
  200. u8 rx_addr_buf[2];
  201. struct spi_transfer rx_addr_trx;
  202. u8 rx_lqi_buf[2];
  203. struct spi_transfer rx_lqi_trx;
  204. u8 rx_fifo_buf[RX_FIFO_SIZE];
  205. struct spi_transfer rx_fifo_buf_trx;
  206. /* isr handling for reading intstat */
  207. struct spi_message irq_msg;
  208. u8 irq_buf[2];
  209. struct spi_transfer irq_trx;
  210. };
  211. /* regmap information for short address register access */
  212. #define MRF24J40_SHORT_WRITE 0x01
  213. #define MRF24J40_SHORT_READ 0x00
  214. #define MRF24J40_SHORT_NUMREGS 0x3F
  215. /* regmap information for long address register access */
  216. #define MRF24J40_LONG_ACCESS 0x80
  217. #define MRF24J40_LONG_NUMREGS 0x38F
  218. /* Read/Write SPI Commands for Short and Long Address registers. */
  219. #define MRF24J40_READSHORT(reg) ((reg) << 1)
  220. #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
  221. #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
  222. #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
  223. /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
  224. #define MAX_SPI_SPEED_HZ 10000000
  225. #define printdev(X) (&X->spi->dev)
  226. static bool
  227. mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
  228. {
  229. switch (reg) {
  230. case REG_RXMCR:
  231. case REG_PANIDL:
  232. case REG_PANIDH:
  233. case REG_SADRL:
  234. case REG_SADRH:
  235. case REG_EADR0:
  236. case REG_EADR1:
  237. case REG_EADR2:
  238. case REG_EADR3:
  239. case REG_EADR4:
  240. case REG_EADR5:
  241. case REG_EADR6:
  242. case REG_EADR7:
  243. case REG_RXFLUSH:
  244. case REG_ORDER:
  245. case REG_TXMCR:
  246. case REG_ACKTMOUT:
  247. case REG_ESLOTG1:
  248. case REG_SYMTICKL:
  249. case REG_SYMTICKH:
  250. case REG_PACON0:
  251. case REG_PACON1:
  252. case REG_PACON2:
  253. case REG_TXBCON0:
  254. case REG_TXNCON:
  255. case REG_TXG1CON:
  256. case REG_TXG2CON:
  257. case REG_ESLOTG23:
  258. case REG_ESLOTG45:
  259. case REG_ESLOTG67:
  260. case REG_TXPEND:
  261. case REG_WAKECON:
  262. case REG_FROMOFFSET:
  263. case REG_TXBCON1:
  264. case REG_GATECLK:
  265. case REG_TXTIME:
  266. case REG_HSYMTMRL:
  267. case REG_HSYMTMRH:
  268. case REG_SOFTRST:
  269. case REG_SECCON0:
  270. case REG_SECCON1:
  271. case REG_TXSTBL:
  272. case REG_RXSR:
  273. case REG_INTCON:
  274. case REG_TRISGPIO:
  275. case REG_GPIO:
  276. case REG_RFCTL:
  277. case REG_SECCR2:
  278. case REG_SLPACK:
  279. case REG_BBREG0:
  280. case REG_BBREG1:
  281. case REG_BBREG2:
  282. case REG_BBREG3:
  283. case REG_BBREG4:
  284. case REG_BBREG6:
  285. case REG_CCAEDTH:
  286. return true;
  287. default:
  288. return false;
  289. }
  290. }
  291. static bool
  292. mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
  293. {
  294. bool rc;
  295. /* all writeable are also readable */
  296. rc = mrf24j40_short_reg_writeable(dev, reg);
  297. if (rc)
  298. return rc;
  299. /* readonly regs */
  300. switch (reg) {
  301. case REG_TXSTAT:
  302. case REG_INTSTAT:
  303. return true;
  304. default:
  305. return false;
  306. }
  307. }
  308. static bool
  309. mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
  310. {
  311. /* can be changed during runtime */
  312. switch (reg) {
  313. case REG_TXSTAT:
  314. case REG_INTSTAT:
  315. case REG_RXFLUSH:
  316. case REG_TXNCON:
  317. case REG_SOFTRST:
  318. case REG_RFCTL:
  319. case REG_TXBCON0:
  320. case REG_TXG1CON:
  321. case REG_TXG2CON:
  322. case REG_TXBCON1:
  323. case REG_SECCON0:
  324. case REG_RXSR:
  325. case REG_SLPACK:
  326. case REG_SECCR2:
  327. case REG_BBREG6:
  328. /* use them in spi_async and regmap so it's volatile */
  329. case REG_BBREG1:
  330. return true;
  331. default:
  332. return false;
  333. }
  334. }
  335. static bool
  336. mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
  337. {
  338. /* don't clear irq line on read */
  339. switch (reg) {
  340. case REG_INTSTAT:
  341. return true;
  342. default:
  343. return false;
  344. }
  345. }
  346. static const struct regmap_config mrf24j40_short_regmap = {
  347. .name = "mrf24j40_short",
  348. .reg_bits = 7,
  349. .val_bits = 8,
  350. .pad_bits = 1,
  351. .write_flag_mask = MRF24J40_SHORT_WRITE,
  352. .read_flag_mask = MRF24J40_SHORT_READ,
  353. .cache_type = REGCACHE_RBTREE,
  354. .max_register = MRF24J40_SHORT_NUMREGS,
  355. .writeable_reg = mrf24j40_short_reg_writeable,
  356. .readable_reg = mrf24j40_short_reg_readable,
  357. .volatile_reg = mrf24j40_short_reg_volatile,
  358. .precious_reg = mrf24j40_short_reg_precious,
  359. };
  360. static bool
  361. mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
  362. {
  363. switch (reg) {
  364. case REG_RFCON0:
  365. case REG_RFCON1:
  366. case REG_RFCON2:
  367. case REG_RFCON3:
  368. case REG_RFCON5:
  369. case REG_RFCON6:
  370. case REG_RFCON7:
  371. case REG_RFCON8:
  372. case REG_SLPCAL2:
  373. case REG_SLPCON0:
  374. case REG_SLPCON1:
  375. case REG_WAKETIMEL:
  376. case REG_WAKETIMEH:
  377. case REG_REMCNTL:
  378. case REG_REMCNTH:
  379. case REG_MAINCNT0:
  380. case REG_MAINCNT1:
  381. case REG_MAINCNT2:
  382. case REG_MAINCNT3:
  383. case REG_TESTMODE:
  384. case REG_ASSOEAR0:
  385. case REG_ASSOEAR1:
  386. case REG_ASSOEAR2:
  387. case REG_ASSOEAR3:
  388. case REG_ASSOEAR4:
  389. case REG_ASSOEAR5:
  390. case REG_ASSOEAR6:
  391. case REG_ASSOEAR7:
  392. case REG_ASSOSAR0:
  393. case REG_ASSOSAR1:
  394. case REG_UNONCE0:
  395. case REG_UNONCE1:
  396. case REG_UNONCE2:
  397. case REG_UNONCE3:
  398. case REG_UNONCE4:
  399. case REG_UNONCE5:
  400. case REG_UNONCE6:
  401. case REG_UNONCE7:
  402. case REG_UNONCE8:
  403. case REG_UNONCE9:
  404. case REG_UNONCE10:
  405. case REG_UNONCE11:
  406. case REG_UNONCE12:
  407. return true;
  408. default:
  409. return false;
  410. }
  411. }
  412. static bool
  413. mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
  414. {
  415. bool rc;
  416. /* all writeable are also readable */
  417. rc = mrf24j40_long_reg_writeable(dev, reg);
  418. if (rc)
  419. return rc;
  420. /* readonly regs */
  421. switch (reg) {
  422. case REG_SLPCAL0:
  423. case REG_SLPCAL1:
  424. case REG_RFSTATE:
  425. case REG_RSSI:
  426. return true;
  427. default:
  428. return false;
  429. }
  430. }
  431. static bool
  432. mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
  433. {
  434. /* can be changed during runtime */
  435. switch (reg) {
  436. case REG_SLPCAL0:
  437. case REG_SLPCAL1:
  438. case REG_SLPCAL2:
  439. case REG_RFSTATE:
  440. case REG_RSSI:
  441. case REG_MAINCNT3:
  442. return true;
  443. default:
  444. return false;
  445. }
  446. }
  447. static const struct regmap_config mrf24j40_long_regmap = {
  448. .name = "mrf24j40_long",
  449. .reg_bits = 11,
  450. .val_bits = 8,
  451. .pad_bits = 5,
  452. .write_flag_mask = MRF24J40_LONG_ACCESS,
  453. .read_flag_mask = MRF24J40_LONG_ACCESS,
  454. .cache_type = REGCACHE_RBTREE,
  455. .max_register = MRF24J40_LONG_NUMREGS,
  456. .writeable_reg = mrf24j40_long_reg_writeable,
  457. .readable_reg = mrf24j40_long_reg_readable,
  458. .volatile_reg = mrf24j40_long_reg_volatile,
  459. };
  460. static int mrf24j40_long_regmap_write(void *context, const void *data,
  461. size_t count)
  462. {
  463. struct spi_device *spi = context;
  464. u8 buf[3];
  465. if (count > 3)
  466. return -EINVAL;
  467. /* regmap supports read/write mask only in frist byte
  468. * long write access need to set the 12th bit, so we
  469. * make special handling for write.
  470. */
  471. memcpy(buf, data, count);
  472. buf[1] |= (1 << 4);
  473. return spi_write(spi, buf, count);
  474. }
  475. static int
  476. mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
  477. void *val, size_t val_size)
  478. {
  479. struct spi_device *spi = context;
  480. return spi_write_then_read(spi, reg, reg_size, val, val_size);
  481. }
  482. static const struct regmap_bus mrf24j40_long_regmap_bus = {
  483. .write = mrf24j40_long_regmap_write,
  484. .read = mrf24j40_long_regmap_read,
  485. .reg_format_endian_default = REGMAP_ENDIAN_BIG,
  486. .val_format_endian_default = REGMAP_ENDIAN_BIG,
  487. };
  488. static void write_tx_buf_complete(void *context)
  489. {
  490. struct mrf24j40 *devrec = context;
  491. __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
  492. u8 val = BIT_TXNTRIG;
  493. int ret;
  494. if (ieee802154_is_secen(fc))
  495. val |= BIT_TXNSECEN;
  496. if (ieee802154_is_ackreq(fc))
  497. val |= BIT_TXNACKREQ;
  498. devrec->tx_post_msg.complete = NULL;
  499. devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
  500. devrec->tx_post_buf[1] = val;
  501. ret = spi_async(devrec->spi, &devrec->tx_post_msg);
  502. if (ret)
  503. dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
  504. }
  505. /* This function relies on an undocumented write method. Once a write command
  506. and address is set, as many bytes of data as desired can be clocked into
  507. the device. The datasheet only shows setting one byte at a time. */
  508. static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
  509. const u8 *data, size_t length)
  510. {
  511. u16 cmd;
  512. int ret;
  513. /* Range check the length. 2 bytes are used for the length fields.*/
  514. if (length > TX_FIFO_SIZE-2) {
  515. dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
  516. length = TX_FIFO_SIZE-2;
  517. }
  518. cmd = MRF24J40_WRITELONG(reg);
  519. devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
  520. devrec->tx_hdr_buf[1] = cmd & 0xff;
  521. devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
  522. devrec->tx_len_buf[1] = length; /* Total length */
  523. devrec->tx_buf_trx.tx_buf = data;
  524. devrec->tx_buf_trx.len = length;
  525. ret = spi_async(devrec->spi, &devrec->tx_msg);
  526. if (ret)
  527. dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
  528. return ret;
  529. }
  530. static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
  531. {
  532. struct mrf24j40 *devrec = hw->priv;
  533. dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
  534. devrec->tx_skb = skb;
  535. return write_tx_buf(devrec, 0x000, skb->data, skb->len);
  536. }
  537. static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
  538. {
  539. /* TODO: */
  540. pr_warn("mrf24j40: ed not implemented\n");
  541. *level = 0;
  542. return 0;
  543. }
  544. static int mrf24j40_start(struct ieee802154_hw *hw)
  545. {
  546. struct mrf24j40 *devrec = hw->priv;
  547. dev_dbg(printdev(devrec), "start\n");
  548. /* Clear TXNIE and RXIE. Enable interrupts */
  549. return regmap_update_bits(devrec->regmap_short, REG_INTCON,
  550. BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0);
  551. }
  552. static void mrf24j40_stop(struct ieee802154_hw *hw)
  553. {
  554. struct mrf24j40 *devrec = hw->priv;
  555. dev_dbg(printdev(devrec), "stop\n");
  556. /* Set TXNIE and RXIE. Disable Interrupts */
  557. regmap_update_bits(devrec->regmap_short, REG_INTCON,
  558. BIT_TXNIE | BIT_RXIE, BIT_TXNIE | BIT_RXIE);
  559. }
  560. static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
  561. {
  562. struct mrf24j40 *devrec = hw->priv;
  563. u8 val;
  564. int ret;
  565. dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
  566. WARN_ON(page != 0);
  567. WARN_ON(channel < MRF24J40_CHAN_MIN);
  568. WARN_ON(channel > MRF24J40_CHAN_MAX);
  569. /* Set Channel TODO */
  570. val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
  571. ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
  572. RFCON0_CH_MASK, val);
  573. if (ret)
  574. return ret;
  575. /* RF Reset */
  576. ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
  577. BIT_RFRST);
  578. if (ret)
  579. return ret;
  580. ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
  581. if (!ret)
  582. udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
  583. return ret;
  584. }
  585. static int mrf24j40_filter(struct ieee802154_hw *hw,
  586. struct ieee802154_hw_addr_filt *filt,
  587. unsigned long changed)
  588. {
  589. struct mrf24j40 *devrec = hw->priv;
  590. dev_dbg(printdev(devrec), "filter\n");
  591. if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
  592. /* Short Addr */
  593. u8 addrh, addrl;
  594. addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
  595. addrl = le16_to_cpu(filt->short_addr) & 0xff;
  596. regmap_write(devrec->regmap_short, REG_SADRH, addrh);
  597. regmap_write(devrec->regmap_short, REG_SADRL, addrl);
  598. dev_dbg(printdev(devrec),
  599. "Set short addr to %04hx\n", filt->short_addr);
  600. }
  601. if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
  602. /* Device Address */
  603. u8 i, addr[8];
  604. memcpy(addr, &filt->ieee_addr, 8);
  605. for (i = 0; i < 8; i++)
  606. regmap_write(devrec->regmap_short, REG_EADR0 + i,
  607. addr[i]);
  608. #ifdef DEBUG
  609. pr_debug("Set long addr to: ");
  610. for (i = 0; i < 8; i++)
  611. pr_debug("%02hhx ", addr[7 - i]);
  612. pr_debug("\n");
  613. #endif
  614. }
  615. if (changed & IEEE802154_AFILT_PANID_CHANGED) {
  616. /* PAN ID */
  617. u8 panidl, panidh;
  618. panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
  619. panidl = le16_to_cpu(filt->pan_id) & 0xff;
  620. regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
  621. regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
  622. dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
  623. }
  624. if (changed & IEEE802154_AFILT_PANC_CHANGED) {
  625. /* Pan Coordinator */
  626. u8 val;
  627. int ret;
  628. if (filt->pan_coord)
  629. val = BIT_PANCOORD;
  630. else
  631. val = 0;
  632. ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
  633. BIT_PANCOORD, val);
  634. if (ret)
  635. return ret;
  636. /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
  637. * REG_ORDER is maintained as default (no beacon/superframe).
  638. */
  639. dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
  640. filt->pan_coord ? "on" : "off");
  641. }
  642. return 0;
  643. }
  644. static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
  645. {
  646. int ret;
  647. /* Turn back on reception of packets off the air. */
  648. devrec->rx_msg.complete = NULL;
  649. devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
  650. devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
  651. ret = spi_async(devrec->spi, &devrec->rx_msg);
  652. if (ret)
  653. dev_err(printdev(devrec), "failed to unlock rx buffer\n");
  654. }
  655. static void mrf24j40_handle_rx_read_buf_complete(void *context)
  656. {
  657. struct mrf24j40 *devrec = context;
  658. u8 len = devrec->rx_buf[2];
  659. u8 rx_local_buf[RX_FIFO_SIZE];
  660. struct sk_buff *skb;
  661. memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
  662. mrf24j40_handle_rx_read_buf_unlock(devrec);
  663. skb = dev_alloc_skb(IEEE802154_MTU);
  664. if (!skb) {
  665. dev_err(printdev(devrec), "failed to allocate skb\n");
  666. return;
  667. }
  668. skb_put_data(skb, rx_local_buf, len);
  669. ieee802154_rx_irqsafe(devrec->hw, skb, 0);
  670. #ifdef DEBUG
  671. print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
  672. rx_local_buf, len, 0);
  673. pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
  674. devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
  675. #endif
  676. }
  677. static void mrf24j40_handle_rx_read_buf(void *context)
  678. {
  679. struct mrf24j40 *devrec = context;
  680. u16 cmd;
  681. int ret;
  682. /* if length is invalid read the full MTU */
  683. if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
  684. devrec->rx_buf[2] = IEEE802154_MTU;
  685. cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
  686. devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
  687. devrec->rx_addr_buf[1] = cmd & 0xff;
  688. devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
  689. ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
  690. if (ret) {
  691. dev_err(printdev(devrec), "failed to read rx buffer\n");
  692. mrf24j40_handle_rx_read_buf_unlock(devrec);
  693. }
  694. }
  695. static void mrf24j40_handle_rx_read_len(void *context)
  696. {
  697. struct mrf24j40 *devrec = context;
  698. u16 cmd;
  699. int ret;
  700. /* read the length of received frame */
  701. devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
  702. devrec->rx_trx.len = 3;
  703. cmd = MRF24J40_READLONG(REG_RX_FIFO);
  704. devrec->rx_buf[0] = cmd >> 8 & 0xff;
  705. devrec->rx_buf[1] = cmd & 0xff;
  706. ret = spi_async(devrec->spi, &devrec->rx_msg);
  707. if (ret) {
  708. dev_err(printdev(devrec), "failed to read rx buffer length\n");
  709. mrf24j40_handle_rx_read_buf_unlock(devrec);
  710. }
  711. }
  712. static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
  713. {
  714. /* Turn off reception of packets off the air. This prevents the
  715. * device from overwriting the buffer while we're reading it.
  716. */
  717. devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
  718. devrec->rx_trx.len = 2;
  719. devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
  720. devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
  721. return spi_async(devrec->spi, &devrec->rx_msg);
  722. }
  723. static int
  724. mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
  725. u8 retries)
  726. {
  727. struct mrf24j40 *devrec = hw->priv;
  728. u8 val;
  729. /* min_be */
  730. val = min_be << TXMCR_MIN_BE_SHIFT;
  731. /* csma backoffs */
  732. val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
  733. return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
  734. TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
  735. val);
  736. }
  737. static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
  738. const struct wpan_phy_cca *cca)
  739. {
  740. struct mrf24j40 *devrec = hw->priv;
  741. u8 val;
  742. /* mapping 802.15.4 to driver spec */
  743. switch (cca->mode) {
  744. case NL802154_CCA_ENERGY:
  745. val = 2;
  746. break;
  747. case NL802154_CCA_CARRIER:
  748. val = 1;
  749. break;
  750. case NL802154_CCA_ENERGY_CARRIER:
  751. switch (cca->opt) {
  752. case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
  753. val = 3;
  754. break;
  755. default:
  756. return -EINVAL;
  757. }
  758. break;
  759. default:
  760. return -EINVAL;
  761. }
  762. return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
  763. BBREG2_CCA_MODE_MASK,
  764. val << BBREG2_CCA_MODE_SHIFT);
  765. }
  766. /* array for representing ed levels */
  767. static const s32 mrf24j40_ed_levels[] = {
  768. -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
  769. -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
  770. -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
  771. -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
  772. -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
  773. -4000, -3900, -3800, -3700, -3600, -3500
  774. };
  775. /* map ed levels to register value */
  776. static const s32 mrf24j40_ed_levels_map[][2] = {
  777. { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },
  778. { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },
  779. { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },
  780. { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },
  781. { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },
  782. { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },
  783. { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },
  784. { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 },
  785. { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 },
  786. { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },
  787. { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },
  788. { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },
  789. { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },
  790. { -3700, 253 }, { -3600, 254 }, { -3500, 255 },
  791. };
  792. static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
  793. {
  794. struct mrf24j40 *devrec = hw->priv;
  795. int i;
  796. for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {
  797. if (mrf24j40_ed_levels_map[i][0] == mbm)
  798. return regmap_write(devrec->regmap_short, REG_CCAEDTH,
  799. mrf24j40_ed_levels_map[i][1]);
  800. }
  801. return -EINVAL;
  802. }
  803. static const s32 mrf24j40ma_powers[] = {
  804. 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190,
  805. -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370,
  806. -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630,
  807. };
  808. static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
  809. {
  810. struct mrf24j40 *devrec = hw->priv;
  811. s32 small_scale;
  812. u8 val;
  813. if (0 >= mbm && mbm > -1000) {
  814. val = TXPWRL_0 << TXPWRL_SHIFT;
  815. small_scale = mbm;
  816. } else if (-1000 >= mbm && mbm > -2000) {
  817. val = TXPWRL_10 << TXPWRL_SHIFT;
  818. small_scale = mbm + 1000;
  819. } else if (-2000 >= mbm && mbm > -3000) {
  820. val = TXPWRL_20 << TXPWRL_SHIFT;
  821. small_scale = mbm + 2000;
  822. } else if (-3000 >= mbm && mbm > -4000) {
  823. val = TXPWRL_30 << TXPWRL_SHIFT;
  824. small_scale = mbm + 3000;
  825. } else {
  826. return -EINVAL;
  827. }
  828. switch (small_scale) {
  829. case 0:
  830. val |= (TXPWRS_0 << TXPWRS_SHIFT);
  831. break;
  832. case -50:
  833. val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
  834. break;
  835. case -120:
  836. val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
  837. break;
  838. case -190:
  839. val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
  840. break;
  841. case -280:
  842. val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
  843. break;
  844. case -370:
  845. val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
  846. break;
  847. case -490:
  848. val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
  849. break;
  850. case -630:
  851. val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
  852. break;
  853. default:
  854. return -EINVAL;
  855. }
  856. return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
  857. TXPWRL_MASK | TXPWRS_MASK, val);
  858. }
  859. static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
  860. {
  861. struct mrf24j40 *devrec = hw->priv;
  862. int ret;
  863. if (on) {
  864. /* set PROMI, ERRPKT and NOACKRSP */
  865. ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
  866. BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
  867. BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
  868. } else {
  869. /* clear PROMI, ERRPKT and NOACKRSP */
  870. ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
  871. BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
  872. 0);
  873. }
  874. return ret;
  875. }
  876. static const struct ieee802154_ops mrf24j40_ops = {
  877. .owner = THIS_MODULE,
  878. .xmit_async = mrf24j40_tx,
  879. .ed = mrf24j40_ed,
  880. .start = mrf24j40_start,
  881. .stop = mrf24j40_stop,
  882. .set_channel = mrf24j40_set_channel,
  883. .set_hw_addr_filt = mrf24j40_filter,
  884. .set_csma_params = mrf24j40_csma_params,
  885. .set_cca_mode = mrf24j40_set_cca_mode,
  886. .set_cca_ed_level = mrf24j40_set_cca_ed_level,
  887. .set_txpower = mrf24j40_set_txpower,
  888. .set_promiscuous_mode = mrf24j40_set_promiscuous_mode,
  889. };
  890. static void mrf24j40_intstat_complete(void *context)
  891. {
  892. struct mrf24j40 *devrec = context;
  893. u8 intstat = devrec->irq_buf[1];
  894. enable_irq(devrec->spi->irq);
  895. /* Ignore Rx security decryption */
  896. if (intstat & BIT_SECIF)
  897. regmap_write_async(devrec->regmap_short, REG_SECCON0,
  898. BIT_SECIGNORE);
  899. /* Check for TX complete */
  900. if (intstat & BIT_TXNIF)
  901. ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
  902. /* Check for Rx */
  903. if (intstat & BIT_RXIF)
  904. mrf24j40_handle_rx(devrec);
  905. }
  906. static irqreturn_t mrf24j40_isr(int irq, void *data)
  907. {
  908. struct mrf24j40 *devrec = data;
  909. int ret;
  910. disable_irq_nosync(irq);
  911. devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
  912. devrec->irq_buf[1] = 0;
  913. /* Read the interrupt status */
  914. ret = spi_async(devrec->spi, &devrec->irq_msg);
  915. if (ret) {
  916. enable_irq(irq);
  917. return IRQ_NONE;
  918. }
  919. return IRQ_HANDLED;
  920. }
  921. static int mrf24j40_hw_init(struct mrf24j40 *devrec)
  922. {
  923. u32 irq_type;
  924. int ret;
  925. /* Initialize the device.
  926. From datasheet section 3.2: Initialization. */
  927. ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
  928. if (ret)
  929. goto err_ret;
  930. ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
  931. if (ret)
  932. goto err_ret;
  933. ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
  934. if (ret)
  935. goto err_ret;
  936. ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
  937. if (ret)
  938. goto err_ret;
  939. ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
  940. if (ret)
  941. goto err_ret;
  942. ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
  943. if (ret)
  944. goto err_ret;
  945. ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
  946. if (ret)
  947. goto err_ret;
  948. ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
  949. if (ret)
  950. goto err_ret;
  951. ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
  952. if (ret)
  953. goto err_ret;
  954. ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
  955. if (ret)
  956. goto err_ret;
  957. ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
  958. if (ret)
  959. goto err_ret;
  960. ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
  961. if (ret)
  962. goto err_ret;
  963. ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
  964. if (ret)
  965. goto err_ret;
  966. ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
  967. if (ret)
  968. goto err_ret;
  969. ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
  970. if (ret)
  971. goto err_ret;
  972. udelay(192);
  973. /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
  974. ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
  975. if (ret)
  976. goto err_ret;
  977. if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
  978. /* Enable external amplifier.
  979. * From MRF24J40MC datasheet section 1.3: Operation.
  980. */
  981. regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
  982. 0x07);
  983. /* Set GPIO3 as output. */
  984. regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
  985. 0x08);
  986. /* Set GPIO3 HIGH to enable U5 voltage regulator */
  987. regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
  988. /* Reduce TX pwr to meet FCC requirements.
  989. * From MRF24J40MC datasheet section 3.1.1
  990. */
  991. regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
  992. }
  993. irq_type = irq_get_trigger_type(devrec->spi->irq);
  994. if (irq_type == IRQ_TYPE_EDGE_RISING ||
  995. irq_type == IRQ_TYPE_EDGE_FALLING)
  996. dev_warn(&devrec->spi->dev,
  997. "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n");
  998. switch (irq_type) {
  999. case IRQ_TYPE_EDGE_RISING:
  1000. case IRQ_TYPE_LEVEL_HIGH:
  1001. /* set interrupt polarity to rising */
  1002. ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
  1003. BIT_INTEDGE, BIT_INTEDGE);
  1004. if (ret)
  1005. goto err_ret;
  1006. break;
  1007. default:
  1008. /* default is falling edge */
  1009. break;
  1010. }
  1011. return 0;
  1012. err_ret:
  1013. return ret;
  1014. }
  1015. static void
  1016. mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
  1017. {
  1018. spi_message_init(&devrec->tx_msg);
  1019. devrec->tx_msg.context = devrec;
  1020. devrec->tx_msg.complete = write_tx_buf_complete;
  1021. devrec->tx_hdr_trx.len = 2;
  1022. devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
  1023. spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
  1024. devrec->tx_len_trx.len = 2;
  1025. devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
  1026. spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
  1027. spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
  1028. spi_message_init(&devrec->tx_post_msg);
  1029. devrec->tx_post_msg.context = devrec;
  1030. devrec->tx_post_trx.len = 2;
  1031. devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
  1032. spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
  1033. }
  1034. static void
  1035. mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
  1036. {
  1037. spi_message_init(&devrec->rx_msg);
  1038. devrec->rx_msg.context = devrec;
  1039. devrec->rx_trx.len = 2;
  1040. devrec->rx_trx.tx_buf = devrec->rx_buf;
  1041. devrec->rx_trx.rx_buf = devrec->rx_buf;
  1042. spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
  1043. spi_message_init(&devrec->rx_buf_msg);
  1044. devrec->rx_buf_msg.context = devrec;
  1045. devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
  1046. devrec->rx_addr_trx.len = 2;
  1047. devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
  1048. spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
  1049. devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
  1050. spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
  1051. devrec->rx_lqi_trx.len = 2;
  1052. devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
  1053. spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
  1054. }
  1055. static void
  1056. mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
  1057. {
  1058. spi_message_init(&devrec->irq_msg);
  1059. devrec->irq_msg.context = devrec;
  1060. devrec->irq_msg.complete = mrf24j40_intstat_complete;
  1061. devrec->irq_trx.len = 2;
  1062. devrec->irq_trx.tx_buf = devrec->irq_buf;
  1063. devrec->irq_trx.rx_buf = devrec->irq_buf;
  1064. spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
  1065. }
  1066. static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
  1067. {
  1068. ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
  1069. devrec->hw->phy->current_channel = 11;
  1070. /* mrf24j40 supports max_minbe 0 - 3 */
  1071. devrec->hw->phy->supported.max_minbe = 3;
  1072. /* datasheet doesn't say anything about max_be, but we have min_be
  1073. * So we assume the max_be default.
  1074. */
  1075. devrec->hw->phy->supported.min_maxbe = 5;
  1076. devrec->hw->phy->supported.max_maxbe = 5;
  1077. devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;
  1078. devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
  1079. BIT(NL802154_CCA_CARRIER) |
  1080. BIT(NL802154_CCA_ENERGY_CARRIER);
  1081. devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
  1082. devrec->hw->phy->cca_ed_level = -6900;
  1083. devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
  1084. devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
  1085. switch (spi_get_device_id(devrec->spi)->driver_data) {
  1086. case MRF24J40:
  1087. case MRF24J40MA:
  1088. devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;
  1089. devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);
  1090. devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;
  1091. break;
  1092. default:
  1093. break;
  1094. }
  1095. }
  1096. static int mrf24j40_probe(struct spi_device *spi)
  1097. {
  1098. int ret = -ENOMEM, irq_type;
  1099. struct ieee802154_hw *hw;
  1100. struct mrf24j40 *devrec;
  1101. dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
  1102. /* Register with the 802154 subsystem */
  1103. hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
  1104. if (!hw)
  1105. goto err_ret;
  1106. devrec = hw->priv;
  1107. devrec->spi = spi;
  1108. spi_set_drvdata(spi, devrec);
  1109. devrec->hw = hw;
  1110. devrec->hw->parent = &spi->dev;
  1111. devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
  1112. devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
  1113. IEEE802154_HW_CSMA_PARAMS |
  1114. IEEE802154_HW_PROMISCUOUS;
  1115. devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
  1116. WPAN_PHY_FLAG_CCA_ED_LEVEL;
  1117. mrf24j40_setup_tx_spi_messages(devrec);
  1118. mrf24j40_setup_rx_spi_messages(devrec);
  1119. mrf24j40_setup_irq_spi_messages(devrec);
  1120. devrec->regmap_short = devm_regmap_init_spi(spi,
  1121. &mrf24j40_short_regmap);
  1122. if (IS_ERR(devrec->regmap_short)) {
  1123. ret = PTR_ERR(devrec->regmap_short);
  1124. dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
  1125. ret);
  1126. goto err_register_device;
  1127. }
  1128. devrec->regmap_long = devm_regmap_init(&spi->dev,
  1129. &mrf24j40_long_regmap_bus,
  1130. spi, &mrf24j40_long_regmap);
  1131. if (IS_ERR(devrec->regmap_long)) {
  1132. ret = PTR_ERR(devrec->regmap_long);
  1133. dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
  1134. ret);
  1135. goto err_register_device;
  1136. }
  1137. if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
  1138. dev_warn(&spi->dev, "spi clock above possible maximum: %d",
  1139. MAX_SPI_SPEED_HZ);
  1140. ret = -EINVAL;
  1141. goto err_register_device;
  1142. }
  1143. ret = mrf24j40_hw_init(devrec);
  1144. if (ret)
  1145. goto err_register_device;
  1146. mrf24j40_phy_setup(devrec);
  1147. /* request IRQF_TRIGGER_LOW as fallback default */
  1148. irq_type = irq_get_trigger_type(spi->irq);
  1149. if (!irq_type)
  1150. irq_type = IRQF_TRIGGER_LOW;
  1151. ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
  1152. irq_type, dev_name(&spi->dev), devrec);
  1153. if (ret) {
  1154. dev_err(printdev(devrec), "Unable to get IRQ");
  1155. goto err_register_device;
  1156. }
  1157. dev_dbg(printdev(devrec), "registered mrf24j40\n");
  1158. ret = ieee802154_register_hw(devrec->hw);
  1159. if (ret)
  1160. goto err_register_device;
  1161. return 0;
  1162. err_register_device:
  1163. ieee802154_free_hw(devrec->hw);
  1164. err_ret:
  1165. return ret;
  1166. }
  1167. static void mrf24j40_remove(struct spi_device *spi)
  1168. {
  1169. struct mrf24j40 *devrec = spi_get_drvdata(spi);
  1170. dev_dbg(printdev(devrec), "remove\n");
  1171. ieee802154_unregister_hw(devrec->hw);
  1172. ieee802154_free_hw(devrec->hw);
  1173. /* TODO: Will ieee802154_free_device() wait until ->xmit() is
  1174. * complete? */
  1175. }
  1176. static const struct of_device_id mrf24j40_of_match[] = {
  1177. { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
  1178. { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
  1179. { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
  1180. { },
  1181. };
  1182. MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
  1183. static const struct spi_device_id mrf24j40_ids[] = {
  1184. { "mrf24j40", MRF24J40 },
  1185. { "mrf24j40ma", MRF24J40MA },
  1186. { "mrf24j40mc", MRF24J40MC },
  1187. { },
  1188. };
  1189. MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
  1190. static struct spi_driver mrf24j40_driver = {
  1191. .driver = {
  1192. .of_match_table = mrf24j40_of_match,
  1193. .name = "mrf24j40",
  1194. },
  1195. .id_table = mrf24j40_ids,
  1196. .probe = mrf24j40_probe,
  1197. .remove = mrf24j40_remove,
  1198. };
  1199. module_spi_driver(mrf24j40_driver);
  1200. MODULE_LICENSE("GPL");
  1201. MODULE_AUTHOR("Alan Ott");
  1202. MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");