gaudi2P.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright 2020-2022 HabanaLabs, Ltd.
  4. * All Rights Reserved.
  5. *
  6. */
  7. #ifndef GAUDI2P_H_
  8. #define GAUDI2P_H_
  9. #include <uapi/misc/habanalabs.h>
  10. #include "../common/habanalabs.h"
  11. #include "../include/common/hl_boot_if.h"
  12. #include "../include/gaudi2/gaudi2.h"
  13. #include "../include/gaudi2/gaudi2_packets.h"
  14. #include "../include/gaudi2/gaudi2_fw_if.h"
  15. #include "../include/gaudi2/gaudi2_async_events.h"
  16. #define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb"
  17. #define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb"
  18. #define MMU_PAGE_TABLES_INITIAL_SIZE 0x10000000 /* 256MB */
  19. #define GAUDI2_CPU_TIMEOUT_USEC 30000000 /* 30s */
  20. #define GAUDI2_FPGA_CPU_TIMEOUT 100000000 /* 100s */
  21. #define NUMBER_OF_PDMA_QUEUES 2
  22. #define NUMBER_OF_EDMA_QUEUES 8
  23. #define NUMBER_OF_MME_QUEUES 4
  24. #define NUMBER_OF_TPC_QUEUES 25
  25. #define NUMBER_OF_NIC_QUEUES 24
  26. #define NUMBER_OF_ROT_QUEUES 2
  27. #define NUMBER_OF_CPU_QUEUES 1
  28. #define NUMBER_OF_HW_QUEUES ((NUMBER_OF_PDMA_QUEUES + \
  29. NUMBER_OF_EDMA_QUEUES + \
  30. NUMBER_OF_MME_QUEUES + \
  31. NUMBER_OF_TPC_QUEUES + \
  32. NUMBER_OF_NIC_QUEUES + \
  33. NUMBER_OF_ROT_QUEUES + \
  34. NUMBER_OF_CPU_QUEUES) * \
  35. NUM_OF_PQ_PER_QMAN)
  36. #define NUMBER_OF_QUEUES (NUMBER_OF_CPU_QUEUES + NUMBER_OF_HW_QUEUES)
  37. #define DCORE_NUM_OF_SOB \
  38. (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
  39. mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
  40. #define DCORE_NUM_OF_MONITORS \
  41. (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
  42. mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
  43. #define NUMBER_OF_DEC ((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC)
  44. /* Map all arcs dccm + arc schedulers acp blocks */
  45. #define NUM_OF_USER_ACP_BLOCKS (NUM_OF_SCHEDULER_ARC + 2)
  46. #define NUM_OF_USER_NIC_UMR_BLOCKS 15
  47. #define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2)
  48. #define NUM_USER_MAPPED_BLOCKS \
  49. (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
  50. NUM_OF_EXPOSED_SM_BLOCKS + \
  51. (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
  52. /* Within the user mapped array, decoder entries start post all the ARC related
  53. * entries
  54. */
  55. #define USR_MAPPED_BLK_DEC_START_IDX \
  56. (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \
  57. (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
  58. #define USR_MAPPED_BLK_SM_START_IDX \
  59. (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
  60. (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
  61. #define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
  62. mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0)
  63. #define GAUDI2_MAX_PENDING_CS 64
  64. #if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS)
  65. #error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1"
  66. #endif
  67. #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
  68. #define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC 25000000 /* 25s */
  69. #define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC 10000000 /* 10s */
  70. #define GAUDI2_NIC_CLK_FREQ 450000000ull /* 450 MHz */
  71. #define DC_POWER_DEFAULT 60000 /* 60W */
  72. #define GAUDI2_HBM_NUM 6
  73. #define DMA_MAX_TRANSFER_SIZE U32_MAX
  74. #define GAUDI2_DEFAULT_CARD_NAME "HL225"
  75. #define QMAN_STREAMS 4
  76. #define PQ_FETCHER_CACHE_SIZE 8
  77. #define NUM_OF_MME_SBTE_PORTS 5
  78. #define NUM_OF_MME_WB_PORTS 2
  79. #define GAUDI2_ENGINE_ID_DCORE_OFFSET \
  80. (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
  81. /* DRAM Memory Map */
  82. #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
  83. /* This define should be used only when working in a debug mode without dram.
  84. * When working with dram, the driver size will be calculated dynamically.
  85. */
  86. #define NIC_DEFAULT_DRV_SIZE 0x20000000 /* 512MB */
  87. #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
  88. #define NIC_NUMBER_OF_PORTS NIC_NUMBER_OF_ENGINES
  89. #define NUMBER_OF_PCIE_DEC 2
  90. #define PCIE_DEC_SHIFT 8
  91. #define SRAM_USER_BASE_OFFSET 0
  92. /* cluster binning */
  93. #define MAX_FAULTY_HBMS 1
  94. #define GAUDI2_XBAR_EDGE_FULL_MASK 0xF
  95. #define GAUDI2_EDMA_FULL_MASK 0xFF
  96. #define GAUDI2_DRAM_FULL_MASK 0x3F
  97. /* Host virtual address space. */
  98. #define VA_HOST_SPACE_PAGE_START 0xFFF0000000000000ull
  99. #define VA_HOST_SPACE_PAGE_END 0xFFF0800000000000ull /* 140TB */
  100. #define VA_HOST_SPACE_HPAGE_START 0xFFF0800000000000ull
  101. #define VA_HOST_SPACE_HPAGE_END 0xFFF1000000000000ull /* 140TB */
  102. /* 140TB */
  103. #define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
  104. /* 140TB */
  105. #define VA_HOST_SPACE_HPAGE_SIZE (VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START)
  106. #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_PAGE_SIZE + VA_HOST_SPACE_HPAGE_SIZE)
  107. #define HOST_SPACE_INTERNAL_CB_SZ SZ_2M
  108. /*
  109. * HBM virtual address space
  110. * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most.
  111. * No core separation is supported so we can have one chunk of virtual address
  112. * space just above the physical ones.
  113. * The virtual address space starts immediately after the end of the physical
  114. * address space which is determined at run-time.
  115. */
  116. #define VA_HBM_SPACE_END 0x1002000000000000ull
  117. #define HW_CAP_PLL BIT_ULL(0)
  118. #define HW_CAP_DRAM BIT_ULL(1)
  119. #define HW_CAP_PMMU BIT_ULL(2)
  120. #define HW_CAP_CPU BIT_ULL(3)
  121. #define HW_CAP_MSIX BIT_ULL(4)
  122. #define HW_CAP_CPU_Q BIT_ULL(5)
  123. #define HW_CAP_CPU_Q_SHIFT 5
  124. #define HW_CAP_CLK_GATE BIT_ULL(6)
  125. #define HW_CAP_KDMA BIT_ULL(7)
  126. #define HW_CAP_SRAM_SCRAMBLER BIT_ULL(8)
  127. #define HW_CAP_DCORE0_DMMU0 BIT_ULL(9)
  128. #define HW_CAP_DCORE0_DMMU1 BIT_ULL(10)
  129. #define HW_CAP_DCORE0_DMMU2 BIT_ULL(11)
  130. #define HW_CAP_DCORE0_DMMU3 BIT_ULL(12)
  131. #define HW_CAP_DCORE1_DMMU0 BIT_ULL(13)
  132. #define HW_CAP_DCORE1_DMMU1 BIT_ULL(14)
  133. #define HW_CAP_DCORE1_DMMU2 BIT_ULL(15)
  134. #define HW_CAP_DCORE1_DMMU3 BIT_ULL(16)
  135. #define HW_CAP_DCORE2_DMMU0 BIT_ULL(17)
  136. #define HW_CAP_DCORE2_DMMU1 BIT_ULL(18)
  137. #define HW_CAP_DCORE2_DMMU2 BIT_ULL(19)
  138. #define HW_CAP_DCORE2_DMMU3 BIT_ULL(20)
  139. #define HW_CAP_DCORE3_DMMU0 BIT_ULL(21)
  140. #define HW_CAP_DCORE3_DMMU1 BIT_ULL(22)
  141. #define HW_CAP_DCORE3_DMMU2 BIT_ULL(23)
  142. #define HW_CAP_DCORE3_DMMU3 BIT_ULL(24)
  143. #define HW_CAP_DMMU_MASK GENMASK_ULL(24, 9)
  144. #define HW_CAP_DMMU_SHIFT 9
  145. #define HW_CAP_PDMA_MASK BIT_ULL(26)
  146. #define HW_CAP_EDMA_MASK GENMASK_ULL(34, 27)
  147. #define HW_CAP_EDMA_SHIFT 27
  148. #define HW_CAP_MME_MASK GENMASK_ULL(38, 35)
  149. #define HW_CAP_MME_SHIFT 35
  150. #define HW_CAP_ROT_MASK GENMASK_ULL(40, 39)
  151. #define HW_CAP_ROT_SHIFT 39
  152. #define HW_CAP_HBM_SCRAMBLER_HW_RESET BIT_ULL(41)
  153. #define HW_CAP_HBM_SCRAMBLER_SW_RESET BIT_ULL(42)
  154. #define HW_CAP_HBM_SCRAMBLER_MASK (HW_CAP_HBM_SCRAMBLER_HW_RESET | \
  155. HW_CAP_HBM_SCRAMBLER_SW_RESET)
  156. #define HW_CAP_HBM_SCRAMBLER_SHIFT 41
  157. #define HW_CAP_RESERVED BIT(43)
  158. #define HW_CAP_MMU_MASK (HW_CAP_PMMU | HW_CAP_DMMU_MASK)
  159. /* Range Registers */
  160. #define RR_TYPE_SHORT 0
  161. #define RR_TYPE_LONG 1
  162. #define RR_TYPE_SHORT_PRIV 2
  163. #define RR_TYPE_LONG_PRIV 3
  164. #define NUM_SHORT_LBW_RR 14
  165. #define NUM_LONG_LBW_RR 4
  166. #define NUM_SHORT_HBW_RR 6
  167. #define NUM_LONG_HBW_RR 4
  168. /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */
  169. #define RAZWI_INITIATOR_X_SHIFT 0
  170. #define RAZWI_INITIATOR_X_MASK 0x1F
  171. #define RAZWI_INITIATOR_Y_SHIFT 5
  172. #define RAZWI_INITIATOR_Y_MASK 0xF
  173. #define RTR_ID_X_Y(x, y) \
  174. ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
  175. (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
  176. /* decoders have separate mask */
  177. #define HW_CAP_DEC_SHIFT 0
  178. #define HW_CAP_DEC_MASK GENMASK_ULL(9, 0)
  179. /* TPCs have separate mask */
  180. #define HW_CAP_TPC_SHIFT 0
  181. #define HW_CAP_TPC_MASK GENMASK_ULL(24, 0)
  182. /* nics have separate mask */
  183. #define HW_CAP_NIC_SHIFT 0
  184. #define HW_CAP_NIC_MASK GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)
  185. #define GAUDI2_ARC_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 28)) >> 28)
  186. #define GAUDI2_SOB_INCREMENT_BY_ONE (FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \
  187. FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1))
  188. enum gaudi2_reserved_sob_id {
  189. GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
  190. GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST =
  191. GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
  192. GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
  193. GAUDI2_RESERVED_SOB_DEC_NRM_FIRST,
  194. GAUDI2_RESERVED_SOB_DEC_NRM_LAST =
  195. GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
  196. GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST,
  197. GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST =
  198. GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
  199. GAUDI2_RESERVED_SOB_NUMBER
  200. };
  201. enum gaudi2_reserved_mon_id {
  202. GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST,
  203. GAUDI2_RESERVED_MON_CS_COMPLETION_LAST =
  204. GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
  205. GAUDI2_RESERVED_MON_KDMA_COMPLETION,
  206. GAUDI2_RESERVED_MON_DEC_NRM_FIRST,
  207. GAUDI2_RESERVED_MON_DEC_NRM_LAST =
  208. GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
  209. GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST,
  210. GAUDI2_RESERVED_MON_DEC_ABNRM_LAST =
  211. GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
  212. GAUDI2_RESERVED_MON_NUMBER
  213. };
  214. enum gaudi2_reserved_cq_id {
  215. GAUDI2_RESERVED_CQ_CS_COMPLETION,
  216. GAUDI2_RESERVED_CQ_KDMA_COMPLETION,
  217. GAUDI2_RESERVED_CQ_NUMBER
  218. };
  219. /*
  220. * Gaudi2 subtitute TPCs Numbering
  221. * At most- two faulty TPCs are allowed
  222. * First replacement to a faulty TPC will be TPC24, second- TPC23
  223. */
  224. enum substitude_tpc {
  225. FAULTY_TPC_SUBTS_1_TPC_24,
  226. FAULTY_TPC_SUBTS_2_TPC_23,
  227. MAX_FAULTY_TPCS
  228. };
  229. enum gaudi2_dma_core_id {
  230. DMA_CORE_ID_PDMA0, /* Dcore 0 */
  231. DMA_CORE_ID_PDMA1, /* Dcore 0 */
  232. DMA_CORE_ID_EDMA0, /* Dcore 0 */
  233. DMA_CORE_ID_EDMA1, /* Dcore 0 */
  234. DMA_CORE_ID_EDMA2, /* Dcore 1 */
  235. DMA_CORE_ID_EDMA3, /* Dcore 1 */
  236. DMA_CORE_ID_EDMA4, /* Dcore 2 */
  237. DMA_CORE_ID_EDMA5, /* Dcore 2 */
  238. DMA_CORE_ID_EDMA6, /* Dcore 3 */
  239. DMA_CORE_ID_EDMA7, /* Dcore 3 */
  240. DMA_CORE_ID_KDMA, /* Dcore 0 */
  241. DMA_CORE_ID_SIZE
  242. };
  243. enum gaudi2_rotator_id {
  244. ROTATOR_ID_0,
  245. ROTATOR_ID_1,
  246. ROTATOR_ID_SIZE,
  247. };
  248. enum gaudi2_mme_id {
  249. MME_ID_DCORE0,
  250. MME_ID_DCORE1,
  251. MME_ID_DCORE2,
  252. MME_ID_DCORE3,
  253. MME_ID_SIZE,
  254. };
  255. enum gaudi2_tpc_id {
  256. TPC_ID_DCORE0_TPC0,
  257. TPC_ID_DCORE0_TPC1,
  258. TPC_ID_DCORE0_TPC2,
  259. TPC_ID_DCORE0_TPC3,
  260. TPC_ID_DCORE0_TPC4,
  261. TPC_ID_DCORE0_TPC5,
  262. TPC_ID_DCORE1_TPC0,
  263. TPC_ID_DCORE1_TPC1,
  264. TPC_ID_DCORE1_TPC2,
  265. TPC_ID_DCORE1_TPC3,
  266. TPC_ID_DCORE1_TPC4,
  267. TPC_ID_DCORE1_TPC5,
  268. TPC_ID_DCORE2_TPC0,
  269. TPC_ID_DCORE2_TPC1,
  270. TPC_ID_DCORE2_TPC2,
  271. TPC_ID_DCORE2_TPC3,
  272. TPC_ID_DCORE2_TPC4,
  273. TPC_ID_DCORE2_TPC5,
  274. TPC_ID_DCORE3_TPC0,
  275. TPC_ID_DCORE3_TPC1,
  276. TPC_ID_DCORE3_TPC2,
  277. TPC_ID_DCORE3_TPC3,
  278. TPC_ID_DCORE3_TPC4,
  279. TPC_ID_DCORE3_TPC5,
  280. /* the PCI TPC is placed last (mapped liked HW) */
  281. TPC_ID_DCORE0_TPC6,
  282. TPC_ID_SIZE,
  283. };
  284. enum gaudi2_dec_id {
  285. DEC_ID_DCORE0_DEC0,
  286. DEC_ID_DCORE0_DEC1,
  287. DEC_ID_DCORE1_DEC0,
  288. DEC_ID_DCORE1_DEC1,
  289. DEC_ID_DCORE2_DEC0,
  290. DEC_ID_DCORE2_DEC1,
  291. DEC_ID_DCORE3_DEC0,
  292. DEC_ID_DCORE3_DEC1,
  293. DEC_ID_PCIE_VDEC0,
  294. DEC_ID_PCIE_VDEC1,
  295. DEC_ID_SIZE,
  296. };
  297. enum gaudi2_hbm_id {
  298. HBM_ID0,
  299. HBM_ID1,
  300. HBM_ID2,
  301. HBM_ID3,
  302. HBM_ID4,
  303. HBM_ID5,
  304. HBM_ID_SIZE,
  305. };
  306. /* specific EDMA enumeration */
  307. enum gaudi2_edma_id {
  308. EDMA_ID_DCORE0_INSTANCE0,
  309. EDMA_ID_DCORE0_INSTANCE1,
  310. EDMA_ID_DCORE1_INSTANCE0,
  311. EDMA_ID_DCORE1_INSTANCE1,
  312. EDMA_ID_DCORE2_INSTANCE0,
  313. EDMA_ID_DCORE2_INSTANCE1,
  314. EDMA_ID_DCORE3_INSTANCE0,
  315. EDMA_ID_DCORE3_INSTANCE1,
  316. EDMA_ID_SIZE,
  317. };
  318. /* User interrupt count is aligned with HW CQ count.
  319. * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode
  320. */
  321. #define GAUDI2_NUM_USER_INTERRUPTS 255
  322. enum gaudi2_irq_num {
  323. GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX,
  324. GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM,
  325. GAUDI2_IRQ_NUM_DCORE0_DEC0_ABNRM,
  326. GAUDI2_IRQ_NUM_DCORE0_DEC1_NRM,
  327. GAUDI2_IRQ_NUM_DCORE0_DEC1_ABNRM,
  328. GAUDI2_IRQ_NUM_DCORE1_DEC0_NRM,
  329. GAUDI2_IRQ_NUM_DCORE1_DEC0_ABNRM,
  330. GAUDI2_IRQ_NUM_DCORE1_DEC1_NRM,
  331. GAUDI2_IRQ_NUM_DCORE1_DEC1_ABNRM,
  332. GAUDI2_IRQ_NUM_DCORE2_DEC0_NRM,
  333. GAUDI2_IRQ_NUM_DCORE2_DEC0_ABNRM,
  334. GAUDI2_IRQ_NUM_DCORE2_DEC1_NRM,
  335. GAUDI2_IRQ_NUM_DCORE2_DEC1_ABNRM,
  336. GAUDI2_IRQ_NUM_DCORE3_DEC0_NRM,
  337. GAUDI2_IRQ_NUM_DCORE3_DEC0_ABNRM,
  338. GAUDI2_IRQ_NUM_DCORE3_DEC1_NRM,
  339. GAUDI2_IRQ_NUM_DCORE3_DEC1_ABNRM,
  340. GAUDI2_IRQ_NUM_SHARED_DEC0_NRM,
  341. GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM,
  342. GAUDI2_IRQ_NUM_SHARED_DEC1_NRM,
  343. GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM,
  344. GAUDI2_IRQ_NUM_COMPLETION,
  345. GAUDI2_IRQ_NUM_NIC_PORT_FIRST,
  346. GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
  347. GAUDI2_IRQ_NUM_RESERVED_FIRST,
  348. GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_USER_INTERRUPTS - 1),
  349. GAUDI2_IRQ_NUM_USER_FIRST,
  350. GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
  351. GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
  352. };
  353. static_assert(GAUDI2_IRQ_NUM_USER_FIRST > GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM);
  354. /**
  355. * struct dup_block_ctx - context to initialize unit instances across multiple
  356. * blocks where block can be either a dcore of duplicated
  357. * common module. this code relies on constant offsets
  358. * of blocks and unit instances in a block.
  359. * @instance_cfg_fn: instance specific configuration function.
  360. * @data: private configuration data.
  361. * @base: base address of the first instance in the first block.
  362. * @block_off: subsequent blocks address spacing.
  363. * @instance_off: subsequent block's instances address spacing.
  364. * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled).
  365. * @blocks: number of blocks.
  366. * @instances: unit instances per block.
  367. */
  368. struct dup_block_ctx {
  369. void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data);
  370. void *data;
  371. u64 base;
  372. u64 block_off;
  373. u64 instance_off;
  374. u64 enabled_mask;
  375. unsigned int blocks;
  376. unsigned int instances;
  377. };
  378. /**
  379. * struct gaudi2_device - ASIC specific manage structure.
  380. * @cpucp_info_get: get information on device from CPU-CP
  381. * @mapped_blocks: array that holds the base address and size of all blocks
  382. * the user can map.
  383. * @lfsr_rand_seeds: array of MME ACC random seeds to set.
  384. * @hw_queues_lock: protects the H/W queues from concurrent access.
  385. * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory,
  386. * this memory region should be write-only.
  387. * currently used for HBW QMAN writes which is
  388. * redundant.
  389. * @scratchpad_bus_address: scratchpad bus address
  390. * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell.
  391. * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell.
  392. * @dram_bar_cur_addr: current address of DRAM PCI bar.
  393. * @hw_cap_initialized: This field contains a bit per H/W engine. When that
  394. * engine is initialized, that bit is set by the driver to
  395. * signal we can use this engine in later code paths.
  396. * Each bit is cleared upon reset of its corresponding H/W
  397. * engine.
  398. * @active_hw_arc: This field contains a bit per ARC of an H/W engine with
  399. * exception of TPC and NIC engines. Once an engine arc is
  400. * initialized, its respective bit is set. Driver can uniquely
  401. * identify each initialized ARC and use this information in
  402. * later code paths. Each respective bit is cleared upon reset
  403. * of its corresponding ARC of the H/W engine.
  404. * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine.
  405. * When that engine is initialized, that bit is set by
  406. * the driver to signal we can use this engine in later
  407. * code paths.
  408. * Each bit is cleared upon reset of its corresponding H/W
  409. * engine.
  410. * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine.
  411. * When that engine is initialized, that bit is set by
  412. * the driver to signal we can use this engine in later
  413. * code paths.
  414. * Each bit is cleared upon reset of its corresponding H/W
  415. * engine.
  416. * @active_tpc_arc: This field contains a bit per ARC of the TPC engines.
  417. * Once an engine arc is initialized, its respective bit is
  418. * set. Each respective bit is cleared upon reset of its
  419. * corresponding ARC of the TPC engine.
  420. * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine.
  421. * @active_nic_arc: This field contains a bit per ARC of the NIC engines.
  422. * Once an engine arc is initialized, its respective bit is
  423. * set. Each respective bit is cleared upon reset of its
  424. * corresponding ARC of the NIC engine.
  425. * @hw_events: array that holds all H/W events that are defined valid.
  426. * @events_stat: array that holds histogram of all received events.
  427. * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset.
  428. * @num_of_valid_hw_events: used to hold the number of valid H/W events.
  429. * @nic_ports: array that holds all NIC ports manage structures.
  430. * @nic_macros: array that holds all NIC macro manage structures.
  431. * @core_info: core info to be used by the Ethernet driver.
  432. * @aux_ops: functions for core <-> aux drivers communication.
  433. * @flush_db_fifo: flag to force flush DB FIFO after a write.
  434. * @hbm_cfg: HBM subsystem settings
  435. * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock.
  436. */
  437. struct gaudi2_device {
  438. int (*cpucp_info_get)(struct hl_device *hdev);
  439. struct user_mapped_block mapped_blocks[NUM_USER_MAPPED_BLOCKS];
  440. int lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS];
  441. spinlock_t hw_queues_lock;
  442. void *scratchpad_kernel_address;
  443. dma_addr_t scratchpad_bus_address;
  444. void *virt_msix_db_cpu_addr;
  445. dma_addr_t virt_msix_db_dma_addr;
  446. u64 dram_bar_cur_addr;
  447. u64 hw_cap_initialized;
  448. u64 active_hw_arc;
  449. u64 dec_hw_cap_initialized;
  450. u64 tpc_hw_cap_initialized;
  451. u64 active_tpc_arc;
  452. u64 nic_hw_cap_initialized;
  453. u64 active_nic_arc;
  454. u32 hw_events[GAUDI2_EVENT_SIZE];
  455. u32 events_stat[GAUDI2_EVENT_SIZE];
  456. u32 events_stat_aggregate[GAUDI2_EVENT_SIZE];
  457. u32 num_of_valid_hw_events;
  458. };
  459. extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE];
  460. extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE];
  461. extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE];
  462. extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE];
  463. extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES];
  464. extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE];
  465. void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx);
  466. int gaudi2_coresight_init(struct hl_device *hdev);
  467. int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
  468. void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
  469. void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx);
  470. bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id);
  471. void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
  472. u64 max_val);
  473. void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
  474. u32 offended_addr);
  475. int gaudi2_init_security(struct hl_device *hdev);
  476. void gaudi2_ack_protection_bits_errors(struct hl_device *hdev);
  477. int gaudi2_send_device_activity(struct hl_device *hdev, bool open);
  478. #endif /* GAUDI2P_H_ */