dw-xdata-pcie.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
  4. * Synopsys DesignWare xData driver
  5. *
  6. * Author: Gustavo Pimentel <[email protected]>
  7. */
  8. #include <linux/miscdevice.h>
  9. #include <linux/bitfield.h>
  10. #include <linux/pci-epf.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/device.h>
  14. #include <linux/bitops.h>
  15. #include <linux/mutex.h>
  16. #include <linux/delay.h>
  17. #include <linux/pci.h>
  18. #define DW_XDATA_DRIVER_NAME "dw-xdata-pcie"
  19. #define DW_XDATA_EP_MEM_OFFSET 0x8000000
  20. static DEFINE_IDA(xdata_ida);
  21. #define STATUS_DONE BIT(0)
  22. #define CONTROL_DOORBELL BIT(0)
  23. #define CONTROL_IS_WRITE BIT(1)
  24. #define CONTROL_LENGTH(a) FIELD_PREP(GENMASK(13, 2), a)
  25. #define CONTROL_PATTERN_INC BIT(16)
  26. #define CONTROL_NO_ADDR_INC BIT(18)
  27. #define XPERF_CONTROL_ENABLE BIT(5)
  28. #define BURST_REPEAT BIT(31)
  29. #define BURST_VALUE 0x1001
  30. #define PATTERN_VALUE 0x0
  31. struct dw_xdata_regs {
  32. u32 addr_lsb; /* 0x000 */
  33. u32 addr_msb; /* 0x004 */
  34. u32 burst_cnt; /* 0x008 */
  35. u32 control; /* 0x00c */
  36. u32 pattern; /* 0x010 */
  37. u32 status; /* 0x014 */
  38. u32 RAM_addr; /* 0x018 */
  39. u32 RAM_port; /* 0x01c */
  40. u32 _reserved0[14]; /* 0x020..0x054 */
  41. u32 perf_control; /* 0x058 */
  42. u32 _reserved1[41]; /* 0x05c..0x0fc */
  43. u32 wr_cnt_lsb; /* 0x100 */
  44. u32 wr_cnt_msb; /* 0x104 */
  45. u32 rd_cnt_lsb; /* 0x108 */
  46. u32 rd_cnt_msb; /* 0x10c */
  47. } __packed;
  48. struct dw_xdata_region {
  49. phys_addr_t paddr; /* physical address */
  50. void __iomem *vaddr; /* virtual address */
  51. };
  52. struct dw_xdata {
  53. struct dw_xdata_region rg_region; /* registers */
  54. size_t max_wr_len; /* max wr xfer len */
  55. size_t max_rd_len; /* max rd xfer len */
  56. struct mutex mutex;
  57. struct pci_dev *pdev;
  58. struct miscdevice misc_dev;
  59. };
  60. static inline struct dw_xdata_regs __iomem *__dw_regs(struct dw_xdata *dw)
  61. {
  62. return dw->rg_region.vaddr;
  63. }
  64. static void dw_xdata_stop(struct dw_xdata *dw)
  65. {
  66. u32 burst;
  67. mutex_lock(&dw->mutex);
  68. burst = readl(&(__dw_regs(dw)->burst_cnt));
  69. if (burst & BURST_REPEAT) {
  70. burst &= ~(u32)BURST_REPEAT;
  71. writel(burst, &(__dw_regs(dw)->burst_cnt));
  72. }
  73. mutex_unlock(&dw->mutex);
  74. }
  75. static void dw_xdata_start(struct dw_xdata *dw, bool write)
  76. {
  77. struct device *dev = &dw->pdev->dev;
  78. u32 control, status;
  79. /* Stop first if xfer in progress */
  80. dw_xdata_stop(dw);
  81. mutex_lock(&dw->mutex);
  82. /* Clear status register */
  83. writel(0x0, &(__dw_regs(dw)->status));
  84. /* Burst count register set for continuous until stopped */
  85. writel(BURST_REPEAT | BURST_VALUE, &(__dw_regs(dw)->burst_cnt));
  86. /* Pattern register */
  87. writel(PATTERN_VALUE, &(__dw_regs(dw)->pattern));
  88. /* Control register */
  89. control = CONTROL_DOORBELL | CONTROL_PATTERN_INC | CONTROL_NO_ADDR_INC;
  90. if (write) {
  91. control |= CONTROL_IS_WRITE;
  92. control |= CONTROL_LENGTH(dw->max_wr_len);
  93. } else {
  94. control |= CONTROL_LENGTH(dw->max_rd_len);
  95. }
  96. writel(control, &(__dw_regs(dw)->control));
  97. /*
  98. * The xData HW block needs about 100 ms to initiate the traffic
  99. * generation according this HW block datasheet.
  100. */
  101. usleep_range(100, 150);
  102. status = readl(&(__dw_regs(dw)->status));
  103. mutex_unlock(&dw->mutex);
  104. if (!(status & STATUS_DONE))
  105. dev_dbg(dev, "xData: started %s direction\n",
  106. write ? "write" : "read");
  107. }
  108. static void dw_xdata_perf_meas(struct dw_xdata *dw, u64 *data, bool write)
  109. {
  110. if (write) {
  111. *data = readl(&(__dw_regs(dw)->wr_cnt_msb));
  112. *data <<= 32;
  113. *data |= readl(&(__dw_regs(dw)->wr_cnt_lsb));
  114. } else {
  115. *data = readl(&(__dw_regs(dw)->rd_cnt_msb));
  116. *data <<= 32;
  117. *data |= readl(&(__dw_regs(dw)->rd_cnt_lsb));
  118. }
  119. }
  120. static u64 dw_xdata_perf_diff(u64 *m1, u64 *m2, u64 time)
  121. {
  122. u64 rate = (*m1 - *m2);
  123. rate *= (1000 * 1000 * 1000);
  124. rate >>= 20;
  125. rate = DIV_ROUND_CLOSEST_ULL(rate, time);
  126. return rate;
  127. }
  128. static void dw_xdata_perf(struct dw_xdata *dw, u64 *rate, bool write)
  129. {
  130. struct device *dev = &dw->pdev->dev;
  131. u64 data[2], time[2], diff;
  132. mutex_lock(&dw->mutex);
  133. /* First acquisition of current count frames */
  134. writel(0x0, &(__dw_regs(dw)->perf_control));
  135. dw_xdata_perf_meas(dw, &data[0], write);
  136. time[0] = jiffies;
  137. writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
  138. /*
  139. * Wait 100ms between the 1st count frame acquisition and the 2nd
  140. * count frame acquisition, in order to calculate the speed later
  141. */
  142. mdelay(100);
  143. /* Second acquisition of current count frames */
  144. writel(0x0, &(__dw_regs(dw)->perf_control));
  145. dw_xdata_perf_meas(dw, &data[1], write);
  146. time[1] = jiffies;
  147. writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
  148. /*
  149. * Speed calculation
  150. *
  151. * rate = (2nd count frames - 1st count frames) / (time elapsed)
  152. */
  153. diff = jiffies_to_nsecs(time[1] - time[0]);
  154. *rate = dw_xdata_perf_diff(&data[1], &data[0], diff);
  155. mutex_unlock(&dw->mutex);
  156. dev_dbg(dev, "xData: time=%llu us, %s=%llu MB/s\n",
  157. diff, write ? "write" : "read", *rate);
  158. }
  159. static struct dw_xdata *misc_dev_to_dw(struct miscdevice *misc_dev)
  160. {
  161. return container_of(misc_dev, struct dw_xdata, misc_dev);
  162. }
  163. static ssize_t write_show(struct device *dev, struct device_attribute *attr,
  164. char *buf)
  165. {
  166. struct miscdevice *misc_dev = dev_get_drvdata(dev);
  167. struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
  168. u64 rate;
  169. dw_xdata_perf(dw, &rate, true);
  170. return sysfs_emit(buf, "%llu\n", rate);
  171. }
  172. static ssize_t write_store(struct device *dev, struct device_attribute *attr,
  173. const char *buf, size_t size)
  174. {
  175. struct miscdevice *misc_dev = dev_get_drvdata(dev);
  176. struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
  177. bool enabled;
  178. int ret;
  179. ret = kstrtobool(buf, &enabled);
  180. if (ret < 0)
  181. return ret;
  182. if (enabled) {
  183. dev_dbg(dev, "xData: requested write transfer\n");
  184. dw_xdata_start(dw, true);
  185. } else {
  186. dev_dbg(dev, "xData: requested stop transfer\n");
  187. dw_xdata_stop(dw);
  188. }
  189. return size;
  190. }
  191. static DEVICE_ATTR_RW(write);
  192. static ssize_t read_show(struct device *dev, struct device_attribute *attr,
  193. char *buf)
  194. {
  195. struct miscdevice *misc_dev = dev_get_drvdata(dev);
  196. struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
  197. u64 rate;
  198. dw_xdata_perf(dw, &rate, false);
  199. return sysfs_emit(buf, "%llu\n", rate);
  200. }
  201. static ssize_t read_store(struct device *dev, struct device_attribute *attr,
  202. const char *buf, size_t size)
  203. {
  204. struct miscdevice *misc_dev = dev_get_drvdata(dev);
  205. struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
  206. bool enabled;
  207. int ret;
  208. ret = kstrtobool(buf, &enabled);
  209. if (ret < 0)
  210. return ret;
  211. if (enabled) {
  212. dev_dbg(dev, "xData: requested read transfer\n");
  213. dw_xdata_start(dw, false);
  214. } else {
  215. dev_dbg(dev, "xData: requested stop transfer\n");
  216. dw_xdata_stop(dw);
  217. }
  218. return size;
  219. }
  220. static DEVICE_ATTR_RW(read);
  221. static struct attribute *xdata_attrs[] = {
  222. &dev_attr_write.attr,
  223. &dev_attr_read.attr,
  224. NULL,
  225. };
  226. ATTRIBUTE_GROUPS(xdata);
  227. static int dw_xdata_pcie_probe(struct pci_dev *pdev,
  228. const struct pci_device_id *pid)
  229. {
  230. struct device *dev = &pdev->dev;
  231. struct dw_xdata *dw;
  232. char name[24];
  233. u64 addr;
  234. int err;
  235. int id;
  236. /* Enable PCI device */
  237. err = pcim_enable_device(pdev);
  238. if (err) {
  239. dev_err(dev, "enabling device failed\n");
  240. return err;
  241. }
  242. /* Mapping PCI BAR regions */
  243. err = pcim_iomap_regions(pdev, BIT(BAR_0), pci_name(pdev));
  244. if (err) {
  245. dev_err(dev, "xData BAR I/O remapping failed\n");
  246. return err;
  247. }
  248. pci_set_master(pdev);
  249. /* Allocate memory */
  250. dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
  251. if (!dw)
  252. return -ENOMEM;
  253. /* Data structure initialization */
  254. mutex_init(&dw->mutex);
  255. dw->rg_region.vaddr = pcim_iomap_table(pdev)[BAR_0];
  256. if (!dw->rg_region.vaddr)
  257. return -ENOMEM;
  258. dw->rg_region.paddr = pdev->resource[BAR_0].start;
  259. dw->max_wr_len = pcie_get_mps(pdev);
  260. dw->max_wr_len >>= 2;
  261. dw->max_rd_len = pcie_get_readrq(pdev);
  262. dw->max_rd_len >>= 2;
  263. dw->pdev = pdev;
  264. id = ida_simple_get(&xdata_ida, 0, 0, GFP_KERNEL);
  265. if (id < 0) {
  266. dev_err(dev, "xData: unable to get id\n");
  267. return id;
  268. }
  269. snprintf(name, sizeof(name), DW_XDATA_DRIVER_NAME ".%d", id);
  270. dw->misc_dev.name = kstrdup(name, GFP_KERNEL);
  271. if (!dw->misc_dev.name) {
  272. err = -ENOMEM;
  273. goto err_ida_remove;
  274. }
  275. dw->misc_dev.minor = MISC_DYNAMIC_MINOR;
  276. dw->misc_dev.parent = dev;
  277. dw->misc_dev.groups = xdata_groups;
  278. writel(0x0, &(__dw_regs(dw)->RAM_addr));
  279. writel(0x0, &(__dw_regs(dw)->RAM_port));
  280. addr = dw->rg_region.paddr + DW_XDATA_EP_MEM_OFFSET;
  281. writel(lower_32_bits(addr), &(__dw_regs(dw)->addr_lsb));
  282. writel(upper_32_bits(addr), &(__dw_regs(dw)->addr_msb));
  283. dev_dbg(dev, "xData: target address = 0x%.16llx\n", addr);
  284. dev_dbg(dev, "xData: wr_len = %zu, rd_len = %zu\n",
  285. dw->max_wr_len * 4, dw->max_rd_len * 4);
  286. /* Saving data structure reference */
  287. pci_set_drvdata(pdev, dw);
  288. /* Register misc device */
  289. err = misc_register(&dw->misc_dev);
  290. if (err) {
  291. dev_err(dev, "xData: failed to register device\n");
  292. goto err_kfree_name;
  293. }
  294. return 0;
  295. err_kfree_name:
  296. kfree(dw->misc_dev.name);
  297. err_ida_remove:
  298. ida_simple_remove(&xdata_ida, id);
  299. return err;
  300. }
  301. static void dw_xdata_pcie_remove(struct pci_dev *pdev)
  302. {
  303. struct dw_xdata *dw = pci_get_drvdata(pdev);
  304. int id;
  305. if (sscanf(dw->misc_dev.name, DW_XDATA_DRIVER_NAME ".%d", &id) != 1)
  306. return;
  307. if (id < 0)
  308. return;
  309. dw_xdata_stop(dw);
  310. misc_deregister(&dw->misc_dev);
  311. kfree(dw->misc_dev.name);
  312. ida_simple_remove(&xdata_ida, id);
  313. }
  314. static const struct pci_device_id dw_xdata_pcie_id_table[] = {
  315. { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
  316. { }
  317. };
  318. MODULE_DEVICE_TABLE(pci, dw_xdata_pcie_id_table);
  319. static struct pci_driver dw_xdata_pcie_driver = {
  320. .name = DW_XDATA_DRIVER_NAME,
  321. .id_table = dw_xdata_pcie_id_table,
  322. .probe = dw_xdata_pcie_probe,
  323. .remove = dw_xdata_pcie_remove,
  324. };
  325. module_pci_driver(dw_xdata_pcie_driver);
  326. MODULE_LICENSE("GPL v2");
  327. MODULE_DESCRIPTION("Synopsys DesignWare xData PCIe driver");
  328. MODULE_AUTHOR("Gustavo Pimentel <[email protected]>");