rts5261.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Rui FENG <[email protected]>
  8. * Wei WANG <[email protected]>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/rtsx_pci.h>
  13. #include "rts5261.h"
  14. #include "rtsx_pcr.h"
  15. static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
  16. {
  17. u8 val;
  18. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  19. return val & IC_VERSION_MASK;
  20. }
  21. static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  22. {
  23. u8 driving_3v3[4][3] = {
  24. {0x96, 0x96, 0x96},
  25. {0x96, 0x96, 0x96},
  26. {0x7F, 0x7F, 0x7F},
  27. {0x13, 0x13, 0x13},
  28. };
  29. u8 driving_1v8[4][3] = {
  30. {0xB3, 0xB3, 0xB3},
  31. {0x3A, 0x3A, 0x3A},
  32. {0xE6, 0xE6, 0xE6},
  33. {0x99, 0x99, 0x99},
  34. };
  35. u8 (*driving)[3], drive_sel;
  36. if (voltage == OUTPUT_3V3) {
  37. driving = driving_3v3;
  38. drive_sel = pcr->sd30_drive_sel_3v3;
  39. } else {
  40. driving = driving_1v8;
  41. drive_sel = pcr->sd30_drive_sel_1v8;
  42. }
  43. rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  44. 0xFF, driving[drive_sel][0]);
  45. rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  46. 0xFF, driving[drive_sel][1]);
  47. rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
  48. 0xFF, driving[drive_sel][2]);
  49. }
  50. static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
  51. {
  52. /* Set relink_time to 0 */
  53. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  54. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  55. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  56. RELINK_TIME_MASK, 0);
  57. if (pm_state == HOST_ENTER_S3)
  58. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  59. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  60. if (!runtime) {
  61. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
  62. CD_RESUME_EN_MASK, 0);
  63. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
  64. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  65. FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
  66. } else {
  67. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  68. FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
  69. rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
  70. RTS5261_INFORM_RTD3_COLD, RTS5261_INFORM_RTD3_COLD);
  71. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
  72. RTS5261_FORCE_PRSNT_LOW, RTS5261_FORCE_PRSNT_LOW);
  73. }
  74. rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
  75. SSC_POWER_DOWN, SSC_POWER_DOWN);
  76. }
  77. static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
  78. {
  79. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  80. LED_SHINE_MASK, LED_SHINE_EN);
  81. }
  82. static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
  83. {
  84. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  85. LED_SHINE_MASK, LED_SHINE_DISABLE);
  86. }
  87. static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
  88. {
  89. return rtsx_pci_write_register(pcr, GPIO_CTL,
  90. 0x02, 0x02);
  91. }
  92. static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
  93. {
  94. return rtsx_pci_write_register(pcr, GPIO_CTL,
  95. 0x02, 0x00);
  96. }
  97. /* SD Pull Control Enable:
  98. * SD_DAT[3:0] ==> pull up
  99. * SD_CD ==> pull up
  100. * SD_WP ==> pull up
  101. * SD_CMD ==> pull up
  102. * SD_CLK ==> pull down
  103. */
  104. static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
  105. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  106. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  107. 0,
  108. };
  109. /* SD Pull Control Disable:
  110. * SD_DAT[3:0] ==> pull down
  111. * SD_CD ==> pull up
  112. * SD_WP ==> pull down
  113. * SD_CMD ==> pull down
  114. * SD_CLK ==> pull down
  115. */
  116. static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
  117. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  118. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  119. 0,
  120. };
  121. static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
  122. {
  123. rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
  124. | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
  125. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
  126. rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
  127. CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
  128. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  129. return 0;
  130. }
  131. static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
  132. {
  133. struct rtsx_cr_option *option = &pcr->option;
  134. if (option->ocp_en)
  135. rtsx_pci_enable_ocp(pcr);
  136. rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
  137. CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
  138. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
  139. RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
  140. rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
  141. RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
  142. rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
  143. RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
  144. msleep(20);
  145. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
  146. /* Initialize SD_CFG1 register */
  147. rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
  148. SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
  149. rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
  150. 0xFF, SD20_RX_POS_EDGE);
  151. rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
  152. rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
  153. SD_STOP | SD_CLR_ERR);
  154. /* Reset SD_CFG3 register */
  155. rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
  156. rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
  157. SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
  158. SD30_CLK_STOP_CFG0, 0);
  159. if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
  160. pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
  161. rts5261_sd_set_sample_push_timing_sd30(pcr);
  162. return 0;
  163. }
  164. static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  165. {
  166. int err;
  167. u16 val = 0;
  168. rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
  169. RTS5261_PUPDC, RTS5261_PUPDC);
  170. switch (voltage) {
  171. case OUTPUT_3V3:
  172. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  173. val |= PHY_TUNE_SDBUS_33;
  174. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  175. if (err < 0)
  176. return err;
  177. rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
  178. RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
  179. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  180. SD_IO_USING_1V8, 0);
  181. break;
  182. case OUTPUT_1V8:
  183. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  184. val &= ~PHY_TUNE_SDBUS_33;
  185. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  186. if (err < 0)
  187. return err;
  188. rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
  189. RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
  190. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  191. SD_IO_USING_1V8, SD_IO_USING_1V8);
  192. break;
  193. default:
  194. return -EINVAL;
  195. }
  196. /* set pad drive */
  197. rts5261_fill_driving(pcr, voltage);
  198. return 0;
  199. }
  200. static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
  201. {
  202. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  203. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  204. rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
  205. RTS5260_DMA_RST | RTS5260_ADMA3_RST,
  206. RTS5260_DMA_RST | RTS5260_ADMA3_RST);
  207. rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
  208. }
  209. static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
  210. {
  211. rts5261_stop_cmd(pcr);
  212. rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
  213. }
  214. static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
  215. {
  216. u8 val = 0;
  217. val = SD_OCP_INT_EN | SD_DETECT_EN;
  218. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  219. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
  220. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
  221. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  222. }
  223. static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
  224. {
  225. u8 mask = 0;
  226. mask = SD_OCP_INT_EN | SD_DETECT_EN;
  227. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  228. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  229. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
  230. }
  231. static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
  232. {
  233. int err = 0;
  234. rts5261_card_before_power_off(pcr);
  235. err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
  236. RTS5261_LDO_POWERON_MASK, 0);
  237. rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
  238. CFG_SD_POW_AUTO_PD, 0);
  239. if (pcr->option.ocp_en)
  240. rtsx_pci_disable_ocp(pcr);
  241. return err;
  242. }
  243. static void rts5261_init_ocp(struct rtsx_pcr *pcr)
  244. {
  245. struct rtsx_cr_option *option = &pcr->option;
  246. if (option->ocp_en) {
  247. u8 mask, val;
  248. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  249. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
  250. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
  251. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  252. RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
  253. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  254. RTS5261_LDO1_OCP_LMT_THD_MASK,
  255. RTS5261_LDO1_LMT_THD_2000);
  256. mask = SD_OCP_GLITCH_MASK;
  257. val = pcr->hw_param.ocp_glitch;
  258. rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
  259. rts5261_enable_ocp(pcr);
  260. } else {
  261. rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
  262. RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
  263. }
  264. }
  265. static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
  266. {
  267. u8 mask = 0;
  268. u8 val = 0;
  269. mask = SD_OCP_INT_CLR | SD_OC_CLR;
  270. val = SD_OCP_INT_CLR | SD_OC_CLR;
  271. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  272. udelay(1000);
  273. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  274. }
  275. static void rts5261_process_ocp(struct rtsx_pcr *pcr)
  276. {
  277. if (!pcr->option.ocp_en)
  278. return;
  279. rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
  280. if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
  281. rts5261_clear_ocpstat(pcr);
  282. rts5261_card_power_off(pcr, RTSX_SD_CARD);
  283. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  284. pcr->ocp_stat = 0;
  285. }
  286. }
  287. static void rts5261_init_from_hw(struct rtsx_pcr *pcr)
  288. {
  289. struct pci_dev *pdev = pcr->pci;
  290. u32 lval1, lval2, i;
  291. u16 setting_reg1, setting_reg2;
  292. u8 valid, efuse_valid, tmp;
  293. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  294. REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
  295. REG_EFUSE_POR | REG_EFUSE_POWERON);
  296. udelay(1);
  297. rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
  298. RTS5261_EFUSE_ADDR_MASK, 0x00);
  299. rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
  300. RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
  301. RTS5261_EFUSE_ENABLE);
  302. /* Wait transfer end */
  303. for (i = 0; i < MAX_RW_REG_CNT; i++) {
  304. rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
  305. if ((tmp & 0x80) == 0)
  306. break;
  307. }
  308. rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
  309. efuse_valid = ((tmp & 0x0C) >> 2);
  310. pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
  311. pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);
  312. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
  313. /* 0x816 */
  314. valid = (u8)((lval2 >> 16) & 0x03);
  315. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  316. REG_EFUSE_POR, 0);
  317. pcr_dbg(pcr, "Disable efuse por!\n");
  318. if (efuse_valid == 2 || efuse_valid == 3) {
  319. if (valid == 3) {
  320. /* Bypass efuse */
  321. setting_reg1 = PCR_SETTING_REG1;
  322. setting_reg2 = PCR_SETTING_REG2;
  323. } else {
  324. /* Use efuse data */
  325. setting_reg1 = PCR_SETTING_REG4;
  326. setting_reg2 = PCR_SETTING_REG5;
  327. }
  328. } else if (efuse_valid == 0) {
  329. // default
  330. setting_reg1 = PCR_SETTING_REG1;
  331. setting_reg2 = PCR_SETTING_REG2;
  332. } else {
  333. return;
  334. }
  335. pci_read_config_dword(pdev, setting_reg2, &lval2);
  336. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
  337. if (!rts5261_vendor_setting_valid(lval2)) {
  338. /* Not support MMC default */
  339. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  340. pcr_dbg(pcr, "skip fetch vendor setting\n");
  341. return;
  342. }
  343. if (!rts5261_reg_check_mmc_support(lval2))
  344. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  345. pcr->rtd3_en = rts5261_reg_to_rtd3(lval2);
  346. if (rts5261_reg_check_reverse_socket(lval2))
  347. pcr->flags |= PCR_REVERSE_SOCKET;
  348. pci_read_config_dword(pdev, setting_reg1, &lval1);
  349. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
  350. pcr->aspm_en = rts5261_reg_to_aspm(lval1);
  351. pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1);
  352. pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1);
  353. if (setting_reg1 == PCR_SETTING_REG1) {
  354. /* store setting */
  355. rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
  356. rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
  357. rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
  358. rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
  359. rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
  360. rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
  361. rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
  362. pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);
  363. lval2 = lval2 & 0x00FFFFFF;
  364. pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);
  365. }
  366. }
  367. static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
  368. {
  369. struct rtsx_cr_option *option = &pcr->option;
  370. if (option->ltr_en) {
  371. if (option->ltr_enabled)
  372. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  373. }
  374. }
  375. static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
  376. {
  377. struct rtsx_cr_option *option = &pcr->option;
  378. u32 val;
  379. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
  380. CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
  381. rts5261_init_from_cfg(pcr);
  382. rts5261_init_from_hw(pcr);
  383. /* power off efuse */
  384. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  385. REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
  386. rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
  387. AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
  388. rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
  389. if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) {
  390. val = rtsx_pci_readl(pcr, RTSX_DUM_REG);
  391. rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
  392. }
  393. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
  394. RTS5261_AUX_CLK_16M_EN, 0);
  395. /* Release PRSNT# */
  396. rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
  397. RTS5261_FORCE_PRSNT_LOW, 0);
  398. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
  399. FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
  400. rtsx_pci_write_register(pcr, PCLK_CTL,
  401. PCLK_MODE_SEL, PCLK_MODE_SEL);
  402. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  403. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
  404. /* LED shine disabled, set initial shine cycle period */
  405. rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
  406. /* Configure driving */
  407. rts5261_fill_driving(pcr, OUTPUT_3V3);
  408. if (pcr->flags & PCR_REVERSE_SOCKET)
  409. rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
  410. else
  411. rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
  412. /*
  413. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  414. * to drive low, and we forcibly request clock.
  415. */
  416. if (option->force_clkreq_0)
  417. rtsx_pci_write_register(pcr, PETXCFG,
  418. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  419. else
  420. rtsx_pci_write_register(pcr, PETXCFG,
  421. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  422. rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
  423. if (pcr->rtd3_en) {
  424. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
  425. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  426. FORCE_PM_CONTROL | FORCE_PM_VALUE,
  427. FORCE_PM_CONTROL | FORCE_PM_VALUE);
  428. } else {
  429. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
  430. rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
  431. FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
  432. }
  433. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
  434. /* Clear Enter RTD3_cold Information*/
  435. rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
  436. RTS5261_INFORM_RTD3_COLD, 0);
  437. return 0;
  438. }
  439. static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
  440. {
  441. u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  442. u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  443. if (pcr->aspm_enabled == enable)
  444. return;
  445. val |= (pcr->aspm_en & 0x02);
  446. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  447. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  448. PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
  449. pcr->aspm_enabled = enable;
  450. }
  451. static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
  452. {
  453. u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  454. u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  455. if (pcr->aspm_enabled == enable)
  456. return;
  457. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  458. PCI_EXP_LNKCTL_ASPMC, 0);
  459. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  460. rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
  461. udelay(10);
  462. pcr->aspm_enabled = enable;
  463. }
  464. static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
  465. {
  466. if (enable)
  467. rts5261_enable_aspm(pcr, true);
  468. else
  469. rts5261_disable_aspm(pcr, false);
  470. }
  471. static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  472. {
  473. struct rtsx_cr_option *option = &pcr->option;
  474. int aspm_L1_1, aspm_L1_2;
  475. u8 val = 0;
  476. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  477. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  478. if (active) {
  479. /* run, latency: 60us */
  480. if (aspm_L1_1)
  481. val = option->ltr_l1off_snooze_sspwrgate;
  482. } else {
  483. /* l1off, latency: 300us */
  484. if (aspm_L1_2)
  485. val = option->ltr_l1off_sspwrgate;
  486. }
  487. rtsx_set_l1off_sub(pcr, val);
  488. }
  489. static const struct pcr_ops rts5261_pcr_ops = {
  490. .turn_on_led = rts5261_turn_on_led,
  491. .turn_off_led = rts5261_turn_off_led,
  492. .extra_init_hw = rts5261_extra_init_hw,
  493. .enable_auto_blink = rts5261_enable_auto_blink,
  494. .disable_auto_blink = rts5261_disable_auto_blink,
  495. .card_power_on = rts5261_card_power_on,
  496. .card_power_off = rts5261_card_power_off,
  497. .switch_output_voltage = rts5261_switch_output_voltage,
  498. .force_power_down = rts5261_force_power_down,
  499. .stop_cmd = rts5261_stop_cmd,
  500. .set_aspm = rts5261_set_aspm,
  501. .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
  502. .enable_ocp = rts5261_enable_ocp,
  503. .disable_ocp = rts5261_disable_ocp,
  504. .init_ocp = rts5261_init_ocp,
  505. .process_ocp = rts5261_process_ocp,
  506. .clear_ocpstat = rts5261_clear_ocpstat,
  507. };
  508. static inline u8 double_ssc_depth(u8 depth)
  509. {
  510. return ((depth > 1) ? (depth - 1) : depth);
  511. }
  512. int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  513. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  514. {
  515. int err, clk;
  516. u16 n;
  517. u8 clk_divider, mcu_cnt, div;
  518. static const u8 depth[] = {
  519. [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
  520. [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
  521. [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
  522. [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
  523. };
  524. if (initial_mode) {
  525. /* We use 250k(around) here, in initial stage */
  526. if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) {
  527. clk_divider = SD_CLK_DIVIDE_256;
  528. card_clock = 60000000;
  529. } else {
  530. clk_divider = SD_CLK_DIVIDE_128;
  531. card_clock = 30000000;
  532. }
  533. } else {
  534. clk_divider = SD_CLK_DIVIDE_0;
  535. }
  536. err = rtsx_pci_write_register(pcr, SD_CFG1,
  537. SD_CLK_DIVIDE_MASK, clk_divider);
  538. if (err < 0)
  539. return err;
  540. card_clock /= 1000000;
  541. pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
  542. clk = card_clock;
  543. if (!initial_mode && double_clk)
  544. clk = card_clock * 2;
  545. pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  546. clk, pcr->cur_clock);
  547. if (clk == pcr->cur_clock)
  548. return 0;
  549. if (pcr->ops->conv_clk_and_div_n)
  550. n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
  551. else
  552. n = clk - 4;
  553. if ((clk <= 4) || (n > 396))
  554. return -EINVAL;
  555. mcu_cnt = 125/clk + 3;
  556. if (mcu_cnt > 15)
  557. mcu_cnt = 15;
  558. div = CLK_DIV_1;
  559. while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
  560. if (pcr->ops->conv_clk_and_div_n) {
  561. int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
  562. DIV_N_TO_CLK) * 2;
  563. n = pcr->ops->conv_clk_and_div_n(dbl_clk,
  564. CLK_TO_DIV_N);
  565. } else {
  566. n = (n + 4) * 2 - 4;
  567. }
  568. div++;
  569. }
  570. n = (n / 2) - 1;
  571. pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
  572. ssc_depth = depth[ssc_depth];
  573. if (double_clk)
  574. ssc_depth = double_ssc_depth(ssc_depth);
  575. if (ssc_depth) {
  576. if (div == CLK_DIV_2) {
  577. if (ssc_depth > 1)
  578. ssc_depth -= 1;
  579. else
  580. ssc_depth = RTS5261_SSC_DEPTH_8M;
  581. } else if (div == CLK_DIV_4) {
  582. if (ssc_depth > 2)
  583. ssc_depth -= 2;
  584. else
  585. ssc_depth = RTS5261_SSC_DEPTH_8M;
  586. } else if (div == CLK_DIV_8) {
  587. if (ssc_depth > 3)
  588. ssc_depth -= 3;
  589. else
  590. ssc_depth = RTS5261_SSC_DEPTH_8M;
  591. }
  592. } else {
  593. ssc_depth = 0;
  594. }
  595. pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
  596. rtsx_pci_init_cmd(pcr);
  597. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  598. CLK_LOW_FREQ, CLK_LOW_FREQ);
  599. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  600. 0xFF, (div << 4) | mcu_cnt);
  601. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  602. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  603. SSC_DEPTH_MASK, ssc_depth);
  604. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
  605. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  606. if (vpclk) {
  607. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  608. PHASE_NOT_RESET, 0);
  609. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  610. PHASE_NOT_RESET, 0);
  611. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  612. PHASE_NOT_RESET, PHASE_NOT_RESET);
  613. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  614. PHASE_NOT_RESET, PHASE_NOT_RESET);
  615. }
  616. err = rtsx_pci_send_cmd(pcr, 2000);
  617. if (err < 0)
  618. return err;
  619. /* Wait SSC clock stable */
  620. udelay(SSC_CLOCK_STABLE_WAIT);
  621. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  622. if (err < 0)
  623. return err;
  624. pcr->cur_clock = clk;
  625. return 0;
  626. }
  627. void rts5261_init_params(struct rtsx_pcr *pcr)
  628. {
  629. struct rtsx_cr_option *option = &pcr->option;
  630. struct rtsx_hw_param *hw_param = &pcr->hw_param;
  631. u8 val;
  632. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  633. rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
  634. if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK))
  635. pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
  636. pcr->num_slots = 1;
  637. pcr->ops = &rts5261_pcr_ops;
  638. pcr->flags = 0;
  639. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  640. pcr->sd30_drive_sel_1v8 = 0x00;
  641. pcr->sd30_drive_sel_3v3 = 0x00;
  642. pcr->aspm_en = ASPM_L1_EN;
  643. pcr->aspm_mode = ASPM_MODE_REG;
  644. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
  645. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  646. pcr->ic_version = rts5261_get_ic_version(pcr);
  647. pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
  648. pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
  649. pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
  650. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  651. | LTR_L1SS_PWR_GATE_EN);
  652. option->ltr_en = true;
  653. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  654. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  655. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  656. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  657. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  658. option->ltr_l1off_sspwrgate = 0x7F;
  659. option->ltr_l1off_snooze_sspwrgate = 0x78;
  660. option->ocp_en = 1;
  661. hw_param->interrupt_en |= SD_OC_INT_EN;
  662. hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
  663. option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040;
  664. }