rts5228.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Ricky WU <[email protected]>
  8. * Rui FENG <[email protected]>
  9. * Wei WANG <[email protected]>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/delay.h>
  13. #include <linux/rtsx_pci.h>
  14. #include "rts5228.h"
  15. #include "rtsx_pcr.h"
  16. static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
  17. {
  18. u8 val;
  19. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  20. return val & IC_VERSION_MASK;
  21. }
  22. static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  23. {
  24. u8 driving_3v3[4][3] = {
  25. {0x13, 0x13, 0x13},
  26. {0x96, 0x96, 0x96},
  27. {0x7F, 0x7F, 0x7F},
  28. {0x96, 0x96, 0x96},
  29. };
  30. u8 driving_1v8[4][3] = {
  31. {0x99, 0x99, 0x99},
  32. {0xB5, 0xB5, 0xB5},
  33. {0xE6, 0x7E, 0xFE},
  34. {0x6B, 0x6B, 0x6B},
  35. };
  36. u8 (*driving)[3], drive_sel;
  37. if (voltage == OUTPUT_3V3) {
  38. driving = driving_3v3;
  39. drive_sel = pcr->sd30_drive_sel_3v3;
  40. } else {
  41. driving = driving_1v8;
  42. drive_sel = pcr->sd30_drive_sel_1v8;
  43. }
  44. rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  45. 0xFF, driving[drive_sel][0]);
  46. rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  47. 0xFF, driving[drive_sel][1]);
  48. rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
  49. 0xFF, driving[drive_sel][2]);
  50. }
  51. static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
  52. {
  53. struct pci_dev *pdev = pcr->pci;
  54. u32 reg;
  55. /* 0x724~0x727 */
  56. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  57. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  58. if (!rtsx_vendor_setting_valid(reg)) {
  59. pcr_dbg(pcr, "skip fetch vendor setting\n");
  60. return;
  61. }
  62. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  63. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  64. /* 0x814~0x817 */
  65. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  66. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  67. pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
  68. if (rtsx_check_mmc_support(reg))
  69. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  70. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  71. if (rtsx_reg_check_reverse_socket(reg))
  72. pcr->flags |= PCR_REVERSE_SOCKET;
  73. }
  74. static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
  75. {
  76. return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
  77. }
  78. static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
  79. {
  80. /* Set relink_time to 0 */
  81. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  82. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  83. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  84. RELINK_TIME_MASK, 0);
  85. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  86. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  87. if (!runtime) {
  88. rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
  89. CD_RESUME_EN_MASK, 0);
  90. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
  91. rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
  92. FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
  93. }
  94. rtsx_pci_write_register(pcr, FPDCTL,
  95. SSC_POWER_DOWN, SSC_POWER_DOWN);
  96. }
  97. static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
  98. {
  99. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  100. LED_SHINE_MASK, LED_SHINE_EN);
  101. }
  102. static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
  103. {
  104. return rtsx_pci_write_register(pcr, OLT_LED_CTL,
  105. LED_SHINE_MASK, LED_SHINE_DISABLE);
  106. }
  107. static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
  108. {
  109. return rtsx_pci_write_register(pcr, GPIO_CTL,
  110. 0x02, 0x02);
  111. }
  112. static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
  113. {
  114. return rtsx_pci_write_register(pcr, GPIO_CTL,
  115. 0x02, 0x00);
  116. }
  117. /* SD Pull Control Enable:
  118. * SD_DAT[3:0] ==> pull up
  119. * SD_CD ==> pull up
  120. * SD_WP ==> pull up
  121. * SD_CMD ==> pull up
  122. * SD_CLK ==> pull down
  123. */
  124. static const u32 rts5228_sd_pull_ctl_enable_tbl[] = {
  125. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  126. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  127. 0,
  128. };
  129. /* SD Pull Control Disable:
  130. * SD_DAT[3:0] ==> pull down
  131. * SD_CD ==> pull up
  132. * SD_WP ==> pull down
  133. * SD_CMD ==> pull down
  134. * SD_CLK ==> pull down
  135. */
  136. static const u32 rts5228_sd_pull_ctl_disable_tbl[] = {
  137. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  138. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  139. 0,
  140. };
  141. static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
  142. {
  143. rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
  144. | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
  145. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
  146. rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
  147. CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
  148. rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  149. return 0;
  150. }
  151. static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
  152. {
  153. struct rtsx_cr_option *option = &pcr->option;
  154. if (option->ocp_en)
  155. rtsx_pci_enable_ocp(pcr);
  156. rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
  157. CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
  158. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
  159. RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33);
  160. rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  161. RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART);
  162. mdelay(2);
  163. rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  164. RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON);
  165. rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  166. RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON);
  167. msleep(20);
  168. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
  169. /* Initialize SD_CFG1 register */
  170. rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
  171. SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
  172. rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
  173. 0xFF, SD20_RX_POS_EDGE);
  174. rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
  175. rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
  176. SD_STOP | SD_CLR_ERR);
  177. /* Reset SD_CFG3 register */
  178. rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
  179. rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
  180. SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
  181. SD30_CLK_STOP_CFG0, 0);
  182. if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
  183. pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
  184. rts5228_sd_set_sample_push_timing_sd30(pcr);
  185. return 0;
  186. }
  187. static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  188. {
  189. int err;
  190. u16 val = 0;
  191. rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
  192. RTS5228_PUPDC, RTS5228_PUPDC);
  193. switch (voltage) {
  194. case OUTPUT_3V3:
  195. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  196. val |= PHY_TUNE_SDBUS_33;
  197. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  198. if (err < 0)
  199. return err;
  200. rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
  201. RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33);
  202. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  203. SD_IO_USING_1V8, 0);
  204. break;
  205. case OUTPUT_1V8:
  206. rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
  207. val &= ~PHY_TUNE_SDBUS_33;
  208. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
  209. if (err < 0)
  210. return err;
  211. rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
  212. RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18);
  213. rtsx_pci_write_register(pcr, SD_PAD_CTL,
  214. SD_IO_USING_1V8, SD_IO_USING_1V8);
  215. break;
  216. default:
  217. return -EINVAL;
  218. }
  219. /* set pad drive */
  220. rts5228_fill_driving(pcr, voltage);
  221. return 0;
  222. }
  223. static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
  224. {
  225. rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
  226. rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
  227. rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
  228. RTS5260_DMA_RST | RTS5260_ADMA3_RST,
  229. RTS5260_DMA_RST | RTS5260_ADMA3_RST);
  230. rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
  231. }
  232. static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
  233. {
  234. rts5228_stop_cmd(pcr);
  235. rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
  236. }
  237. static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
  238. {
  239. u8 val = 0;
  240. val = SD_OCP_INT_EN | SD_DETECT_EN;
  241. rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
  242. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  243. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
  244. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
  245. }
  246. static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
  247. {
  248. u8 mask = 0;
  249. mask = SD_OCP_INT_EN | SD_DETECT_EN;
  250. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  251. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  252. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
  253. }
  254. static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
  255. {
  256. int err = 0;
  257. rts5228_card_before_power_off(pcr);
  258. err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
  259. RTS5228_LDO_POWERON_MASK, 0);
  260. rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
  261. if (pcr->option.ocp_en)
  262. rtsx_pci_disable_ocp(pcr);
  263. return err;
  264. }
  265. static void rts5228_init_ocp(struct rtsx_pcr *pcr)
  266. {
  267. struct rtsx_cr_option *option = &pcr->option;
  268. if (option->ocp_en) {
  269. u8 mask, val;
  270. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  271. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
  272. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
  273. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  274. RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
  275. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  276. RTS5228_LDO1_OCP_LMT_THD_MASK,
  277. RTS5228_LDO1_LMT_THD_1500);
  278. rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
  279. mask = SD_OCP_GLITCH_MASK;
  280. val = pcr->hw_param.ocp_glitch;
  281. rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
  282. rts5228_enable_ocp(pcr);
  283. } else {
  284. rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
  285. RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
  286. }
  287. }
  288. static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
  289. {
  290. u8 mask = 0;
  291. u8 val = 0;
  292. mask = SD_OCP_INT_CLR | SD_OC_CLR;
  293. val = SD_OCP_INT_CLR | SD_OC_CLR;
  294. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
  295. udelay(1000);
  296. rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
  297. }
  298. static void rts5228_process_ocp(struct rtsx_pcr *pcr)
  299. {
  300. if (!pcr->option.ocp_en)
  301. return;
  302. rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
  303. if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
  304. rts5228_clear_ocpstat(pcr);
  305. rts5228_card_power_off(pcr, RTSX_SD_CARD);
  306. rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
  307. pcr->ocp_stat = 0;
  308. }
  309. }
  310. static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
  311. {
  312. struct rtsx_cr_option *option = &pcr->option;
  313. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  314. | PM_L1_1_EN | PM_L1_2_EN))
  315. rtsx_pci_disable_oobs_polling(pcr);
  316. else
  317. rtsx_pci_enable_oobs_polling(pcr);
  318. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
  319. if (option->ltr_en) {
  320. if (option->ltr_enabled)
  321. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  322. }
  323. }
  324. static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
  325. {
  326. struct rtsx_cr_option *option = &pcr->option;
  327. rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
  328. CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
  329. rts5228_init_from_cfg(pcr);
  330. rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
  331. AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
  332. rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
  333. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
  334. FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
  335. rtsx_pci_write_register(pcr, PCLK_CTL,
  336. PCLK_MODE_SEL, PCLK_MODE_SEL);
  337. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  338. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
  339. /* LED shine disabled, set initial shine cycle period */
  340. rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
  341. /* Configure driving */
  342. rts5228_fill_driving(pcr, OUTPUT_3V3);
  343. if (pcr->flags & PCR_REVERSE_SOCKET)
  344. rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
  345. else
  346. rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
  347. /*
  348. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  349. * to drive low, and we forcibly request clock.
  350. */
  351. if (option->force_clkreq_0)
  352. rtsx_pci_write_register(pcr, PETXCFG,
  353. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  354. else
  355. rtsx_pci_write_register(pcr, PETXCFG,
  356. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  357. rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
  358. if (pcr->rtd3_en) {
  359. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
  360. rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
  361. FORCE_PM_CONTROL | FORCE_PM_VALUE,
  362. FORCE_PM_CONTROL | FORCE_PM_VALUE);
  363. } else {
  364. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
  365. rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
  366. FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
  367. }
  368. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
  369. return 0;
  370. }
  371. static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
  372. {
  373. u8 mask, val;
  374. if (pcr->aspm_enabled == enable)
  375. return;
  376. mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  377. val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  378. val |= (pcr->aspm_en & 0x02);
  379. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  380. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  381. PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
  382. pcr->aspm_enabled = enable;
  383. }
  384. static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
  385. {
  386. u8 mask, val;
  387. if (pcr->aspm_enabled == enable)
  388. return;
  389. pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
  390. PCI_EXP_LNKCTL_ASPMC, 0);
  391. mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  392. val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
  393. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  394. rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
  395. mdelay(10);
  396. pcr->aspm_enabled = enable;
  397. }
  398. static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
  399. {
  400. if (enable)
  401. rts5228_enable_aspm(pcr, true);
  402. else
  403. rts5228_disable_aspm(pcr, false);
  404. }
  405. static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  406. {
  407. struct rtsx_cr_option *option = &pcr->option;
  408. int aspm_L1_1, aspm_L1_2;
  409. u8 val = 0;
  410. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  411. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  412. if (active) {
  413. /* run, latency: 60us */
  414. if (aspm_L1_1)
  415. val = option->ltr_l1off_snooze_sspwrgate;
  416. } else {
  417. /* l1off, latency: 300us */
  418. if (aspm_L1_2)
  419. val = option->ltr_l1off_sspwrgate;
  420. }
  421. rtsx_set_l1off_sub(pcr, val);
  422. }
  423. static const struct pcr_ops rts5228_pcr_ops = {
  424. .fetch_vendor_settings = rtsx5228_fetch_vendor_settings,
  425. .turn_on_led = rts5228_turn_on_led,
  426. .turn_off_led = rts5228_turn_off_led,
  427. .extra_init_hw = rts5228_extra_init_hw,
  428. .enable_auto_blink = rts5228_enable_auto_blink,
  429. .disable_auto_blink = rts5228_disable_auto_blink,
  430. .card_power_on = rts5228_card_power_on,
  431. .card_power_off = rts5228_card_power_off,
  432. .switch_output_voltage = rts5228_switch_output_voltage,
  433. .force_power_down = rts5228_force_power_down,
  434. .stop_cmd = rts5228_stop_cmd,
  435. .set_aspm = rts5228_set_aspm,
  436. .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0,
  437. .enable_ocp = rts5228_enable_ocp,
  438. .disable_ocp = rts5228_disable_ocp,
  439. .init_ocp = rts5228_init_ocp,
  440. .process_ocp = rts5228_process_ocp,
  441. .clear_ocpstat = rts5228_clear_ocpstat,
  442. .optimize_phy = rts5228_optimize_phy,
  443. };
  444. static inline u8 double_ssc_depth(u8 depth)
  445. {
  446. return ((depth > 1) ? (depth - 1) : depth);
  447. }
  448. int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  449. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
  450. {
  451. int err, clk;
  452. u16 n;
  453. u8 clk_divider, mcu_cnt, div;
  454. static const u8 depth[] = {
  455. [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M,
  456. [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M,
  457. [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M,
  458. [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K,
  459. };
  460. if (initial_mode) {
  461. /* We use 250k(around) here, in initial stage */
  462. clk_divider = SD_CLK_DIVIDE_128;
  463. card_clock = 30000000;
  464. } else {
  465. clk_divider = SD_CLK_DIVIDE_0;
  466. }
  467. err = rtsx_pci_write_register(pcr, SD_CFG1,
  468. SD_CLK_DIVIDE_MASK, clk_divider);
  469. if (err < 0)
  470. return err;
  471. card_clock /= 1000000;
  472. pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
  473. clk = card_clock;
  474. if (!initial_mode && double_clk)
  475. clk = card_clock * 2;
  476. pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
  477. clk, pcr->cur_clock);
  478. if (clk == pcr->cur_clock)
  479. return 0;
  480. if (pcr->ops->conv_clk_and_div_n)
  481. n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
  482. else
  483. n = clk - 4;
  484. if ((clk <= 4) || (n > 396))
  485. return -EINVAL;
  486. mcu_cnt = 125/clk + 3;
  487. if (mcu_cnt > 15)
  488. mcu_cnt = 15;
  489. div = CLK_DIV_1;
  490. while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
  491. if (pcr->ops->conv_clk_and_div_n) {
  492. int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
  493. DIV_N_TO_CLK) * 2;
  494. n = pcr->ops->conv_clk_and_div_n(dbl_clk,
  495. CLK_TO_DIV_N);
  496. } else {
  497. n = (n + 4) * 2 - 4;
  498. }
  499. div++;
  500. }
  501. n = (n / 2) - 1;
  502. pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
  503. ssc_depth = depth[ssc_depth];
  504. if (double_clk)
  505. ssc_depth = double_ssc_depth(ssc_depth);
  506. if (ssc_depth) {
  507. if (div == CLK_DIV_2) {
  508. if (ssc_depth > 1)
  509. ssc_depth -= 1;
  510. else
  511. ssc_depth = RTS5228_SSC_DEPTH_8M;
  512. } else if (div == CLK_DIV_4) {
  513. if (ssc_depth > 2)
  514. ssc_depth -= 2;
  515. else
  516. ssc_depth = RTS5228_SSC_DEPTH_8M;
  517. } else if (div == CLK_DIV_8) {
  518. if (ssc_depth > 3)
  519. ssc_depth -= 3;
  520. else
  521. ssc_depth = RTS5228_SSC_DEPTH_8M;
  522. }
  523. } else {
  524. ssc_depth = 0;
  525. }
  526. pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
  527. rtsx_pci_init_cmd(pcr);
  528. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
  529. CLK_LOW_FREQ, CLK_LOW_FREQ);
  530. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
  531. 0xFF, (div << 4) | mcu_cnt);
  532. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
  533. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
  534. SSC_DEPTH_MASK, ssc_depth);
  535. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
  536. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
  537. if (vpclk) {
  538. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  539. PHASE_NOT_RESET, 0);
  540. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  541. PHASE_NOT_RESET, 0);
  542. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
  543. PHASE_NOT_RESET, PHASE_NOT_RESET);
  544. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
  545. PHASE_NOT_RESET, PHASE_NOT_RESET);
  546. }
  547. err = rtsx_pci_send_cmd(pcr, 2000);
  548. if (err < 0)
  549. return err;
  550. /* Wait SSC clock stable */
  551. udelay(SSC_CLOCK_STABLE_WAIT);
  552. err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
  553. if (err < 0)
  554. return err;
  555. pcr->cur_clock = clk;
  556. return 0;
  557. }
  558. void rts5228_init_params(struct rtsx_pcr *pcr)
  559. {
  560. struct rtsx_cr_option *option = &pcr->option;
  561. struct rtsx_hw_param *hw_param = &pcr->hw_param;
  562. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  563. pcr->num_slots = 1;
  564. pcr->ops = &rts5228_pcr_ops;
  565. pcr->flags = 0;
  566. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  567. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  568. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  569. pcr->aspm_en = ASPM_L1_EN;
  570. pcr->aspm_mode = ASPM_MODE_REG;
  571. pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
  572. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  573. pcr->ic_version = rts5228_get_ic_version(pcr);
  574. pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
  575. pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
  576. pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;
  577. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  578. | LTR_L1SS_PWR_GATE_EN);
  579. option->ltr_en = true;
  580. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  581. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  582. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  583. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  584. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  585. option->ltr_l1off_sspwrgate = 0x7F;
  586. option->ltr_l1off_snooze_sspwrgate = 0x78;
  587. option->ocp_en = 1;
  588. hw_param->interrupt_en |= SD_OC_INT_EN;
  589. hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
  590. option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930;
  591. }