rts5227.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <[email protected]>
  8. * Roger Tseng <[email protected]>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/rtsx_pci.h>
  13. #include "rtsx_pcr.h"
  14. static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
  15. {
  16. u8 val;
  17. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  18. return val & 0x0F;
  19. }
  20. static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  21. {
  22. u8 driving_3v3[4][3] = {
  23. {0x13, 0x13, 0x13},
  24. {0x96, 0x96, 0x96},
  25. {0x7F, 0x7F, 0x7F},
  26. {0x96, 0x96, 0x96},
  27. };
  28. u8 driving_1v8[4][3] = {
  29. {0x99, 0x99, 0x99},
  30. {0xAA, 0xAA, 0xAA},
  31. {0xFE, 0xFE, 0xFE},
  32. {0xB3, 0xB3, 0xB3},
  33. };
  34. u8 (*driving)[3], drive_sel;
  35. if (voltage == OUTPUT_3V3) {
  36. driving = driving_3v3;
  37. drive_sel = pcr->sd30_drive_sel_3v3;
  38. } else {
  39. driving = driving_1v8;
  40. drive_sel = pcr->sd30_drive_sel_1v8;
  41. }
  42. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  43. 0xFF, driving[drive_sel][0]);
  44. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  45. 0xFF, driving[drive_sel][1]);
  46. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  47. 0xFF, driving[drive_sel][2]);
  48. }
  49. static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  50. {
  51. struct pci_dev *pdev = pcr->pci;
  52. u32 reg;
  53. pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  54. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  55. if (!rtsx_vendor_setting_valid(reg))
  56. return;
  57. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  58. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  59. pcr->card_drive_sel &= 0x3F;
  60. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  61. pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  62. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  63. if (CHK_PCI_PID(pcr, 0x522A))
  64. pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
  65. if (rtsx_check_mmc_support(reg))
  66. pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  67. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  68. if (rtsx_reg_check_reverse_socket(reg))
  69. pcr->flags |= PCR_REVERSE_SOCKET;
  70. }
  71. static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
  72. {
  73. struct rtsx_cr_option *option = &pcr->option;
  74. if (CHK_PCI_PID(pcr, 0x522A)) {
  75. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  76. | PM_L1_1_EN | PM_L1_2_EN))
  77. rtsx_pci_disable_oobs_polling(pcr);
  78. else
  79. rtsx_pci_enable_oobs_polling(pcr);
  80. }
  81. if (option->ltr_en) {
  82. if (option->ltr_enabled)
  83. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  84. }
  85. }
  86. static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
  87. {
  88. u16 cap;
  89. struct rtsx_cr_option *option = &pcr->option;
  90. rts5227_init_from_cfg(pcr);
  91. rtsx_pci_init_cmd(pcr);
  92. /* Configure GPIO as output */
  93. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  94. /* Reset ASPM state to default value */
  95. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  96. /* Switch LDO3318 source from DV33 to card_3v3 */
  97. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  98. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  99. /* LED shine disabled, set initial shine cycle period */
  100. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  101. /* Configure LTR */
  102. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
  103. if (cap & PCI_EXP_DEVCTL2_LTR_EN)
  104. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
  105. /* Configure OBFF */
  106. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
  107. /* Configure driving */
  108. rts5227_fill_driving(pcr, OUTPUT_3V3);
  109. /* Configure force_clock_req */
  110. if (pcr->flags & PCR_REVERSE_SOCKET)
  111. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
  112. else
  113. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
  114. if (CHK_PCI_PID(pcr, 0x522A))
  115. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
  116. CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
  117. if (pcr->rtd3_en) {
  118. if (CHK_PCI_PID(pcr, 0x522A)) {
  119. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x01);
  120. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x30);
  121. } else {
  122. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x01);
  123. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x33);
  124. }
  125. } else {
  126. if (CHK_PCI_PID(pcr, 0x522A)) {
  127. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x00);
  128. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
  129. } else {
  130. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x30);
  131. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x00);
  132. }
  133. }
  134. if (option->force_clkreq_0)
  135. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
  136. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  137. else
  138. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
  139. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  140. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
  141. return rtsx_pci_send_cmd(pcr, 100);
  142. }
  143. static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
  144. {
  145. int err;
  146. err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
  147. if (err < 0)
  148. return err;
  149. /* Optimize RX sensitivity */
  150. return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
  151. }
  152. static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
  153. {
  154. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  155. }
  156. static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
  157. {
  158. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  159. }
  160. static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
  161. {
  162. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  163. }
  164. static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
  165. {
  166. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  167. }
  168. static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
  169. {
  170. int err;
  171. if (pcr->option.ocp_en)
  172. rtsx_pci_enable_ocp(pcr);
  173. rtsx_pci_init_cmd(pcr);
  174. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  175. SD_POWER_MASK, SD_PARTIAL_POWER_ON);
  176. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  177. LDO3318_PWR_MASK, 0x02);
  178. err = rtsx_pci_send_cmd(pcr, 100);
  179. if (err < 0)
  180. return err;
  181. /* To avoid too large in-rush current */
  182. msleep(20);
  183. rtsx_pci_init_cmd(pcr);
  184. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  185. SD_POWER_MASK, SD_POWER_ON);
  186. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  187. LDO3318_PWR_MASK, 0x06);
  188. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
  189. SD_OUTPUT_EN, SD_OUTPUT_EN);
  190. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
  191. MS_OUTPUT_EN, MS_OUTPUT_EN);
  192. return rtsx_pci_send_cmd(pcr, 100);
  193. }
  194. static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
  195. {
  196. if (pcr->option.ocp_en)
  197. rtsx_pci_disable_ocp(pcr);
  198. rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
  199. PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
  200. rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
  201. return 0;
  202. }
  203. static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  204. {
  205. int err;
  206. if (voltage == OUTPUT_3V3) {
  207. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
  208. if (err < 0)
  209. return err;
  210. } else if (voltage == OUTPUT_1V8) {
  211. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  212. if (err < 0)
  213. return err;
  214. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
  215. if (err < 0)
  216. return err;
  217. } else {
  218. return -EINVAL;
  219. }
  220. /* set pad drive */
  221. rtsx_pci_init_cmd(pcr);
  222. rts5227_fill_driving(pcr, voltage);
  223. return rtsx_pci_send_cmd(pcr, 100);
  224. }
  225. static const struct pcr_ops rts5227_pcr_ops = {
  226. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  227. .extra_init_hw = rts5227_extra_init_hw,
  228. .optimize_phy = rts5227_optimize_phy,
  229. .turn_on_led = rts5227_turn_on_led,
  230. .turn_off_led = rts5227_turn_off_led,
  231. .enable_auto_blink = rts5227_enable_auto_blink,
  232. .disable_auto_blink = rts5227_disable_auto_blink,
  233. .card_power_on = rts5227_card_power_on,
  234. .card_power_off = rts5227_card_power_off,
  235. .switch_output_voltage = rts5227_switch_output_voltage,
  236. .cd_deglitch = NULL,
  237. .conv_clk_and_div_n = NULL,
  238. };
  239. /* SD Pull Control Enable:
  240. * SD_DAT[3:0] ==> pull up
  241. * SD_CD ==> pull up
  242. * SD_WP ==> pull up
  243. * SD_CMD ==> pull up
  244. * SD_CLK ==> pull down
  245. */
  246. static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
  247. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  248. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  249. 0,
  250. };
  251. /* SD Pull Control Disable:
  252. * SD_DAT[3:0] ==> pull down
  253. * SD_CD ==> pull up
  254. * SD_WP ==> pull down
  255. * SD_CMD ==> pull down
  256. * SD_CLK ==> pull down
  257. */
  258. static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
  259. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  260. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  261. 0,
  262. };
  263. /* MS Pull Control Enable:
  264. * MS CD ==> pull up
  265. * others ==> pull down
  266. */
  267. static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
  268. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  269. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  270. 0,
  271. };
  272. /* MS Pull Control Disable:
  273. * MS CD ==> pull up
  274. * others ==> pull down
  275. */
  276. static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
  277. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  278. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  279. 0,
  280. };
  281. void rts5227_init_params(struct rtsx_pcr *pcr)
  282. {
  283. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  284. pcr->num_slots = 2;
  285. pcr->ops = &rts5227_pcr_ops;
  286. pcr->flags = 0;
  287. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  288. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  289. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  290. pcr->aspm_en = ASPM_L1_EN;
  291. pcr->aspm_mode = ASPM_MODE_CFG;
  292. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
  293. pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
  294. pcr->ic_version = rts5227_get_ic_version(pcr);
  295. pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
  296. pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
  297. pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
  298. pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
  299. pcr->reg_pm_ctrl3 = PM_CTRL3;
  300. }
  301. static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
  302. {
  303. int err;
  304. err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
  305. 0x00);
  306. if (err < 0)
  307. return err;
  308. if (is_version(pcr, 0x522A, IC_VER_A)) {
  309. err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
  310. PHY_RCR2_INIT_27S);
  311. if (err)
  312. return err;
  313. rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
  314. rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
  315. rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
  316. rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
  317. }
  318. return 0;
  319. }
  320. static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
  321. {
  322. rts5227_extra_init_hw(pcr);
  323. /* Power down OCP for power consumption */
  324. if (!pcr->card_exist)
  325. rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
  326. OC_POWER_DOWN);
  327. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
  328. FUNC_FORCE_UPME_XMT_DBG);
  329. rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
  330. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  331. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
  332. return 0;
  333. }
  334. static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  335. {
  336. int err;
  337. if (voltage == OUTPUT_3V3) {
  338. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
  339. if (err < 0)
  340. return err;
  341. } else if (voltage == OUTPUT_1V8) {
  342. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  343. if (err < 0)
  344. return err;
  345. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
  346. if (err < 0)
  347. return err;
  348. } else {
  349. return -EINVAL;
  350. }
  351. /* set pad drive */
  352. rtsx_pci_init_cmd(pcr);
  353. rts5227_fill_driving(pcr, voltage);
  354. return rtsx_pci_send_cmd(pcr, 100);
  355. }
  356. static void rts522a_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
  357. {
  358. /* Set relink_time to 0 */
  359. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  360. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  361. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  362. RELINK_TIME_MASK, 0);
  363. rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3,
  364. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  365. if (!runtime) {
  366. rtsx_pci_write_register(pcr, RTS522A_AUTOLOAD_CFG1,
  367. CD_RESUME_EN_MASK, 0);
  368. rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, 0x01, 0x00);
  369. rtsx_pci_write_register(pcr, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
  370. }
  371. rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
  372. }
  373. static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  374. {
  375. struct rtsx_cr_option *option = &pcr->option;
  376. int aspm_L1_1, aspm_L1_2;
  377. u8 val = 0;
  378. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  379. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  380. if (active) {
  381. /* run, latency: 60us */
  382. if (aspm_L1_1)
  383. val = option->ltr_l1off_snooze_sspwrgate;
  384. } else {
  385. /* l1off, latency: 300us */
  386. if (aspm_L1_2)
  387. val = option->ltr_l1off_sspwrgate;
  388. }
  389. rtsx_set_l1off_sub(pcr, val);
  390. }
  391. /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
  392. */
  393. static const struct pcr_ops rts522a_pcr_ops = {
  394. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  395. .extra_init_hw = rts522a_extra_init_hw,
  396. .optimize_phy = rts522a_optimize_phy,
  397. .turn_on_led = rts5227_turn_on_led,
  398. .turn_off_led = rts5227_turn_off_led,
  399. .enable_auto_blink = rts5227_enable_auto_blink,
  400. .disable_auto_blink = rts5227_disable_auto_blink,
  401. .card_power_on = rts5227_card_power_on,
  402. .card_power_off = rts5227_card_power_off,
  403. .switch_output_voltage = rts522a_switch_output_voltage,
  404. .force_power_down = rts522a_force_power_down,
  405. .cd_deglitch = NULL,
  406. .conv_clk_and_div_n = NULL,
  407. .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
  408. };
  409. void rts522a_init_params(struct rtsx_pcr *pcr)
  410. {
  411. struct rtsx_cr_option *option = &pcr->option;
  412. rts5227_init_params(pcr);
  413. pcr->ops = &rts522a_pcr_ops;
  414. pcr->aspm_mode = ASPM_MODE_REG;
  415. pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
  416. pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
  417. option->dev_flags = LTR_L1SS_PWR_GATE_EN;
  418. option->ltr_en = true;
  419. /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  420. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  421. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  422. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  423. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  424. option->ltr_l1off_sspwrgate = 0x7F;
  425. option->ltr_l1off_snooze_sspwrgate = 0x78;
  426. pcr->option.ocp_en = 1;
  427. if (pcr->option.ocp_en)
  428. pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
  429. pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
  430. pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
  431. }