pcf50633-irq.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* NXP PCF50633 Power Management Unit (PMU) driver
  3. *
  4. * (C) 2006-2008 by Openmoko, Inc.
  5. * Author: Harald Welte <[email protected]>
  6. * Balaji Rao <[email protected]>
  7. * All rights reserved.
  8. */
  9. #include <linux/interrupt.h>
  10. #include <linux/kernel.h>
  11. #include <linux/mutex.h>
  12. #include <linux/export.h>
  13. #include <linux/slab.h>
  14. #include <linux/mfd/pcf50633/core.h>
  15. #include <linux/mfd/pcf50633/mbc.h>
  16. int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
  17. void (*handler) (int, void *), void *data)
  18. {
  19. if (irq < 0 || irq >= PCF50633_NUM_IRQ || !handler)
  20. return -EINVAL;
  21. if (WARN_ON(pcf->irq_handler[irq].handler))
  22. return -EBUSY;
  23. mutex_lock(&pcf->lock);
  24. pcf->irq_handler[irq].handler = handler;
  25. pcf->irq_handler[irq].data = data;
  26. mutex_unlock(&pcf->lock);
  27. return 0;
  28. }
  29. EXPORT_SYMBOL_GPL(pcf50633_register_irq);
  30. int pcf50633_free_irq(struct pcf50633 *pcf, int irq)
  31. {
  32. if (irq < 0 || irq >= PCF50633_NUM_IRQ)
  33. return -EINVAL;
  34. mutex_lock(&pcf->lock);
  35. pcf->irq_handler[irq].handler = NULL;
  36. mutex_unlock(&pcf->lock);
  37. return 0;
  38. }
  39. EXPORT_SYMBOL_GPL(pcf50633_free_irq);
  40. static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask)
  41. {
  42. u8 reg, bit;
  43. int idx;
  44. idx = irq >> 3;
  45. reg = PCF50633_REG_INT1M + idx;
  46. bit = 1 << (irq & 0x07);
  47. pcf50633_reg_set_bit_mask(pcf, reg, bit, mask ? bit : 0);
  48. mutex_lock(&pcf->lock);
  49. if (mask)
  50. pcf->mask_regs[idx] |= bit;
  51. else
  52. pcf->mask_regs[idx] &= ~bit;
  53. mutex_unlock(&pcf->lock);
  54. return 0;
  55. }
  56. int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
  57. {
  58. dev_dbg(pcf->dev, "Masking IRQ %d\n", irq);
  59. return __pcf50633_irq_mask_set(pcf, irq, 1);
  60. }
  61. EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
  62. int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
  63. {
  64. dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq);
  65. return __pcf50633_irq_mask_set(pcf, irq, 0);
  66. }
  67. EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
  68. int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
  69. {
  70. u8 reg, bits;
  71. reg = irq >> 3;
  72. bits = 1 << (irq & 0x07);
  73. return pcf->mask_regs[reg] & bits;
  74. }
  75. EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
  76. static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq)
  77. {
  78. if (pcf->irq_handler[irq].handler)
  79. pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data);
  80. }
  81. /* Maximum amount of time ONKEY is held before emergency action is taken */
  82. #define PCF50633_ONKEY1S_TIMEOUT 8
  83. static irqreturn_t pcf50633_irq(int irq, void *data)
  84. {
  85. struct pcf50633 *pcf = data;
  86. int ret, i, j;
  87. u8 pcf_int[5], chgstat;
  88. /* Read the 5 INT regs in one transaction */
  89. ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
  90. ARRAY_SIZE(pcf_int), pcf_int);
  91. if (ret != ARRAY_SIZE(pcf_int)) {
  92. dev_err(pcf->dev, "Error reading INT registers\n");
  93. /*
  94. * If this doesn't ACK the interrupt to the chip, we'll be
  95. * called once again as we're level triggered.
  96. */
  97. goto out;
  98. }
  99. /* defeat 8s death from lowsys on A5 */
  100. pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04);
  101. /* We immediately read the usb and adapter status. We thus make sure
  102. * only of USBINS/USBREM IRQ handlers are called */
  103. if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
  104. chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
  105. if (chgstat & (0x3 << 4))
  106. pcf_int[0] &= ~PCF50633_INT1_USBREM;
  107. else
  108. pcf_int[0] &= ~PCF50633_INT1_USBINS;
  109. }
  110. /* Make sure only one of ADPINS or ADPREM is set */
  111. if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
  112. chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
  113. if (chgstat & (0x3 << 4))
  114. pcf_int[0] &= ~PCF50633_INT1_ADPREM;
  115. else
  116. pcf_int[0] &= ~PCF50633_INT1_ADPINS;
  117. }
  118. dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
  119. "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
  120. pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
  121. /* Some revisions of the chip don't have a 8s standby mode on
  122. * ONKEY1S press. We try to manually do it in such cases. */
  123. if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
  124. dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
  125. pcf->onkey1s_held);
  126. if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
  127. if (pcf->pdata->force_shutdown)
  128. pcf->pdata->force_shutdown(pcf);
  129. }
  130. if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
  131. dev_info(pcf->dev, "ONKEY1S held\n");
  132. pcf->onkey1s_held = 1 ;
  133. /* Unmask IRQ_SECOND */
  134. pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
  135. PCF50633_INT1_SECOND);
  136. /* Unmask IRQ_ONKEYR */
  137. pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
  138. PCF50633_INT2_ONKEYR);
  139. }
  140. if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
  141. pcf->onkey1s_held = 0;
  142. /* Mask SECOND and ONKEYR interrupts */
  143. if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
  144. pcf50633_reg_set_bit_mask(pcf,
  145. PCF50633_REG_INT1M,
  146. PCF50633_INT1_SECOND,
  147. PCF50633_INT1_SECOND);
  148. if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
  149. pcf50633_reg_set_bit_mask(pcf,
  150. PCF50633_REG_INT2M,
  151. PCF50633_INT2_ONKEYR,
  152. PCF50633_INT2_ONKEYR);
  153. }
  154. /* Have we just resumed ? */
  155. if (pcf->is_suspended) {
  156. pcf->is_suspended = 0;
  157. /* Set the resume reason filtering out non resumers */
  158. for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
  159. pcf->resume_reason[i] = pcf_int[i] &
  160. pcf->pdata->resumers[i];
  161. /* Make sure we don't pass on any ONKEY events to
  162. * userspace now */
  163. pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
  164. }
  165. for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
  166. /* Unset masked interrupts */
  167. pcf_int[i] &= ~pcf->mask_regs[i];
  168. for (j = 0; j < 8 ; j++)
  169. if (pcf_int[i] & (1 << j))
  170. pcf50633_irq_call_handler(pcf, (i * 8) + j);
  171. }
  172. out:
  173. return IRQ_HANDLED;
  174. }
  175. #ifdef CONFIG_PM
  176. int pcf50633_irq_suspend(struct pcf50633 *pcf)
  177. {
  178. int ret;
  179. int i;
  180. u8 res[5];
  181. /* Make sure our interrupt handlers are not called
  182. * henceforth */
  183. disable_irq(pcf->irq);
  184. /* Save the masks */
  185. ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
  186. ARRAY_SIZE(pcf->suspend_irq_masks),
  187. pcf->suspend_irq_masks);
  188. if (ret < 0) {
  189. dev_err(pcf->dev, "error saving irq masks\n");
  190. goto out;
  191. }
  192. /* Write wakeup irq masks */
  193. for (i = 0; i < ARRAY_SIZE(res); i++)
  194. res[i] = ~pcf->pdata->resumers[i];
  195. ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
  196. ARRAY_SIZE(res), &res[0]);
  197. if (ret < 0) {
  198. dev_err(pcf->dev, "error writing wakeup irq masks\n");
  199. goto out;
  200. }
  201. pcf->is_suspended = 1;
  202. out:
  203. return ret;
  204. }
  205. int pcf50633_irq_resume(struct pcf50633 *pcf)
  206. {
  207. int ret;
  208. /* Write the saved mask registers */
  209. ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
  210. ARRAY_SIZE(pcf->suspend_irq_masks),
  211. pcf->suspend_irq_masks);
  212. if (ret < 0)
  213. dev_err(pcf->dev, "Error restoring saved suspend masks\n");
  214. enable_irq(pcf->irq);
  215. return ret;
  216. }
  217. #endif
  218. int pcf50633_irq_init(struct pcf50633 *pcf, int irq)
  219. {
  220. int ret;
  221. pcf->irq = irq;
  222. /* Enable all interrupts except RTC SECOND */
  223. pcf->mask_regs[0] = 0x80;
  224. pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]);
  225. pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
  226. pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
  227. pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
  228. pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
  229. ret = request_threaded_irq(irq, NULL, pcf50633_irq,
  230. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  231. "pcf50633", pcf);
  232. if (ret)
  233. dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
  234. if (enable_irq_wake(irq) < 0)
  235. dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
  236. "in this hardware revision", irq);
  237. return ret;
  238. }
  239. void pcf50633_irq_free(struct pcf50633 *pcf)
  240. {
  241. free_irq(pcf->irq, pcf);
  242. }