max8925-core.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Base driver for Maxim MAX8925
  4. *
  5. * Copyright (C) 2009-2010 Marvell International Ltd.
  6. * Haojian Zhuang <[email protected]>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/i2c.h>
  11. #include <linux/irq.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regulator/machine.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/mfd/max8925.h>
  18. #include <linux/of.h>
  19. #include <linux/of_platform.h>
  20. static const struct resource bk_resources[] = {
  21. { 0x84, 0x84, "mode control", IORESOURCE_REG, },
  22. { 0x85, 0x85, "control", IORESOURCE_REG, },
  23. };
  24. static struct mfd_cell bk_devs[] = {
  25. {
  26. .name = "max8925-backlight",
  27. .num_resources = ARRAY_SIZE(bk_resources),
  28. .resources = &bk_resources[0],
  29. .id = -1,
  30. },
  31. };
  32. static const struct resource touch_resources[] = {
  33. {
  34. .name = "max8925-tsc",
  35. .start = MAX8925_TSC_IRQ,
  36. .end = MAX8925_ADC_RES_END,
  37. .flags = IORESOURCE_REG,
  38. },
  39. };
  40. static const struct mfd_cell touch_devs[] = {
  41. {
  42. .name = "max8925-touch",
  43. .num_resources = 1,
  44. .resources = &touch_resources[0],
  45. .id = -1,
  46. },
  47. };
  48. static const struct resource power_supply_resources[] = {
  49. {
  50. .name = "max8925-power",
  51. .start = MAX8925_CHG_IRQ1,
  52. .end = MAX8925_CHG_IRQ1_MASK,
  53. .flags = IORESOURCE_REG,
  54. },
  55. };
  56. static const struct mfd_cell power_devs[] = {
  57. {
  58. .name = "max8925-power",
  59. .num_resources = 1,
  60. .resources = &power_supply_resources[0],
  61. .id = -1,
  62. },
  63. };
  64. static const struct resource rtc_resources[] = {
  65. {
  66. .name = "max8925-rtc",
  67. .start = MAX8925_IRQ_RTC_ALARM0,
  68. .end = MAX8925_IRQ_RTC_ALARM0,
  69. .flags = IORESOURCE_IRQ,
  70. },
  71. };
  72. static const struct mfd_cell rtc_devs[] = {
  73. {
  74. .name = "max8925-rtc",
  75. .num_resources = 1,
  76. .resources = &rtc_resources[0],
  77. .id = -1,
  78. },
  79. };
  80. static const struct resource onkey_resources[] = {
  81. {
  82. .name = "max8925-onkey",
  83. .start = MAX8925_IRQ_GPM_SW_R,
  84. .end = MAX8925_IRQ_GPM_SW_R,
  85. .flags = IORESOURCE_IRQ,
  86. }, {
  87. .name = "max8925-onkey",
  88. .start = MAX8925_IRQ_GPM_SW_F,
  89. .end = MAX8925_IRQ_GPM_SW_F,
  90. .flags = IORESOURCE_IRQ,
  91. },
  92. };
  93. static const struct mfd_cell onkey_devs[] = {
  94. {
  95. .name = "max8925-onkey",
  96. .num_resources = 2,
  97. .resources = &onkey_resources[0],
  98. .id = -1,
  99. },
  100. };
  101. static const struct resource sd1_resources[] = {
  102. {0x06, 0x06, "sdv", IORESOURCE_REG, },
  103. };
  104. static const struct resource sd2_resources[] = {
  105. {0x09, 0x09, "sdv", IORESOURCE_REG, },
  106. };
  107. static const struct resource sd3_resources[] = {
  108. {0x0c, 0x0c, "sdv", IORESOURCE_REG, },
  109. };
  110. static const struct resource ldo1_resources[] = {
  111. {0x1a, 0x1a, "ldov", IORESOURCE_REG, },
  112. };
  113. static const struct resource ldo2_resources[] = {
  114. {0x1e, 0x1e, "ldov", IORESOURCE_REG, },
  115. };
  116. static const struct resource ldo3_resources[] = {
  117. {0x22, 0x22, "ldov", IORESOURCE_REG, },
  118. };
  119. static const struct resource ldo4_resources[] = {
  120. {0x26, 0x26, "ldov", IORESOURCE_REG, },
  121. };
  122. static const struct resource ldo5_resources[] = {
  123. {0x2a, 0x2a, "ldov", IORESOURCE_REG, },
  124. };
  125. static const struct resource ldo6_resources[] = {
  126. {0x2e, 0x2e, "ldov", IORESOURCE_REG, },
  127. };
  128. static const struct resource ldo7_resources[] = {
  129. {0x32, 0x32, "ldov", IORESOURCE_REG, },
  130. };
  131. static const struct resource ldo8_resources[] = {
  132. {0x36, 0x36, "ldov", IORESOURCE_REG, },
  133. };
  134. static const struct resource ldo9_resources[] = {
  135. {0x3a, 0x3a, "ldov", IORESOURCE_REG, },
  136. };
  137. static const struct resource ldo10_resources[] = {
  138. {0x3e, 0x3e, "ldov", IORESOURCE_REG, },
  139. };
  140. static const struct resource ldo11_resources[] = {
  141. {0x42, 0x42, "ldov", IORESOURCE_REG, },
  142. };
  143. static const struct resource ldo12_resources[] = {
  144. {0x46, 0x46, "ldov", IORESOURCE_REG, },
  145. };
  146. static const struct resource ldo13_resources[] = {
  147. {0x4a, 0x4a, "ldov", IORESOURCE_REG, },
  148. };
  149. static const struct resource ldo14_resources[] = {
  150. {0x4e, 0x4e, "ldov", IORESOURCE_REG, },
  151. };
  152. static const struct resource ldo15_resources[] = {
  153. {0x52, 0x52, "ldov", IORESOURCE_REG, },
  154. };
  155. static const struct resource ldo16_resources[] = {
  156. {0x12, 0x12, "ldov", IORESOURCE_REG, },
  157. };
  158. static const struct resource ldo17_resources[] = {
  159. {0x16, 0x16, "ldov", IORESOURCE_REG, },
  160. };
  161. static const struct resource ldo18_resources[] = {
  162. {0x74, 0x74, "ldov", IORESOURCE_REG, },
  163. };
  164. static const struct resource ldo19_resources[] = {
  165. {0x5e, 0x5e, "ldov", IORESOURCE_REG, },
  166. };
  167. static const struct resource ldo20_resources[] = {
  168. {0x9e, 0x9e, "ldov", IORESOURCE_REG, },
  169. };
  170. static struct mfd_cell reg_devs[] = {
  171. {
  172. .name = "max8925-regulator",
  173. .id = 0,
  174. .num_resources = ARRAY_SIZE(sd1_resources),
  175. .resources = sd1_resources,
  176. }, {
  177. .name = "max8925-regulator",
  178. .id = 1,
  179. .num_resources = ARRAY_SIZE(sd2_resources),
  180. .resources = sd2_resources,
  181. }, {
  182. .name = "max8925-regulator",
  183. .id = 2,
  184. .num_resources = ARRAY_SIZE(sd3_resources),
  185. .resources = sd3_resources,
  186. }, {
  187. .name = "max8925-regulator",
  188. .id = 3,
  189. .num_resources = ARRAY_SIZE(ldo1_resources),
  190. .resources = ldo1_resources,
  191. }, {
  192. .name = "max8925-regulator",
  193. .id = 4,
  194. .num_resources = ARRAY_SIZE(ldo2_resources),
  195. .resources = ldo2_resources,
  196. }, {
  197. .name = "max8925-regulator",
  198. .id = 5,
  199. .num_resources = ARRAY_SIZE(ldo3_resources),
  200. .resources = ldo3_resources,
  201. }, {
  202. .name = "max8925-regulator",
  203. .id = 6,
  204. .num_resources = ARRAY_SIZE(ldo4_resources),
  205. .resources = ldo4_resources,
  206. }, {
  207. .name = "max8925-regulator",
  208. .id = 7,
  209. .num_resources = ARRAY_SIZE(ldo5_resources),
  210. .resources = ldo5_resources,
  211. }, {
  212. .name = "max8925-regulator",
  213. .id = 8,
  214. .num_resources = ARRAY_SIZE(ldo6_resources),
  215. .resources = ldo6_resources,
  216. }, {
  217. .name = "max8925-regulator",
  218. .id = 9,
  219. .num_resources = ARRAY_SIZE(ldo7_resources),
  220. .resources = ldo7_resources,
  221. }, {
  222. .name = "max8925-regulator",
  223. .id = 10,
  224. .num_resources = ARRAY_SIZE(ldo8_resources),
  225. .resources = ldo8_resources,
  226. }, {
  227. .name = "max8925-regulator",
  228. .id = 11,
  229. .num_resources = ARRAY_SIZE(ldo9_resources),
  230. .resources = ldo9_resources,
  231. }, {
  232. .name = "max8925-regulator",
  233. .id = 12,
  234. .num_resources = ARRAY_SIZE(ldo10_resources),
  235. .resources = ldo10_resources,
  236. }, {
  237. .name = "max8925-regulator",
  238. .id = 13,
  239. .num_resources = ARRAY_SIZE(ldo11_resources),
  240. .resources = ldo11_resources,
  241. }, {
  242. .name = "max8925-regulator",
  243. .id = 14,
  244. .num_resources = ARRAY_SIZE(ldo12_resources),
  245. .resources = ldo12_resources,
  246. }, {
  247. .name = "max8925-regulator",
  248. .id = 15,
  249. .num_resources = ARRAY_SIZE(ldo13_resources),
  250. .resources = ldo13_resources,
  251. }, {
  252. .name = "max8925-regulator",
  253. .id = 16,
  254. .num_resources = ARRAY_SIZE(ldo14_resources),
  255. .resources = ldo14_resources,
  256. }, {
  257. .name = "max8925-regulator",
  258. .id = 17,
  259. .num_resources = ARRAY_SIZE(ldo15_resources),
  260. .resources = ldo15_resources,
  261. }, {
  262. .name = "max8925-regulator",
  263. .id = 18,
  264. .num_resources = ARRAY_SIZE(ldo16_resources),
  265. .resources = ldo16_resources,
  266. }, {
  267. .name = "max8925-regulator",
  268. .id = 19,
  269. .num_resources = ARRAY_SIZE(ldo17_resources),
  270. .resources = ldo17_resources,
  271. }, {
  272. .name = "max8925-regulator",
  273. .id = 20,
  274. .num_resources = ARRAY_SIZE(ldo18_resources),
  275. .resources = ldo18_resources,
  276. }, {
  277. .name = "max8925-regulator",
  278. .id = 21,
  279. .num_resources = ARRAY_SIZE(ldo19_resources),
  280. .resources = ldo19_resources,
  281. }, {
  282. .name = "max8925-regulator",
  283. .id = 22,
  284. .num_resources = ARRAY_SIZE(ldo20_resources),
  285. .resources = ldo20_resources,
  286. },
  287. };
  288. enum {
  289. FLAGS_ADC = 1, /* register in ADC component */
  290. FLAGS_RTC, /* register in RTC component */
  291. };
  292. struct max8925_irq_data {
  293. int reg;
  294. int mask_reg;
  295. int enable; /* enable or not */
  296. int offs; /* bit offset in mask register */
  297. int flags;
  298. int tsc_irq;
  299. };
  300. static struct max8925_irq_data max8925_irqs[] = {
  301. [MAX8925_IRQ_VCHG_DC_OVP] = {
  302. .reg = MAX8925_CHG_IRQ1,
  303. .mask_reg = MAX8925_CHG_IRQ1_MASK,
  304. .offs = 1 << 0,
  305. },
  306. [MAX8925_IRQ_VCHG_DC_F] = {
  307. .reg = MAX8925_CHG_IRQ1,
  308. .mask_reg = MAX8925_CHG_IRQ1_MASK,
  309. .offs = 1 << 1,
  310. },
  311. [MAX8925_IRQ_VCHG_DC_R] = {
  312. .reg = MAX8925_CHG_IRQ1,
  313. .mask_reg = MAX8925_CHG_IRQ1_MASK,
  314. .offs = 1 << 2,
  315. },
  316. [MAX8925_IRQ_VCHG_THM_OK_R] = {
  317. .reg = MAX8925_CHG_IRQ2,
  318. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  319. .offs = 1 << 0,
  320. },
  321. [MAX8925_IRQ_VCHG_THM_OK_F] = {
  322. .reg = MAX8925_CHG_IRQ2,
  323. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  324. .offs = 1 << 1,
  325. },
  326. [MAX8925_IRQ_VCHG_SYSLOW_F] = {
  327. .reg = MAX8925_CHG_IRQ2,
  328. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  329. .offs = 1 << 2,
  330. },
  331. [MAX8925_IRQ_VCHG_SYSLOW_R] = {
  332. .reg = MAX8925_CHG_IRQ2,
  333. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  334. .offs = 1 << 3,
  335. },
  336. [MAX8925_IRQ_VCHG_RST] = {
  337. .reg = MAX8925_CHG_IRQ2,
  338. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  339. .offs = 1 << 4,
  340. },
  341. [MAX8925_IRQ_VCHG_DONE] = {
  342. .reg = MAX8925_CHG_IRQ2,
  343. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  344. .offs = 1 << 5,
  345. },
  346. [MAX8925_IRQ_VCHG_TOPOFF] = {
  347. .reg = MAX8925_CHG_IRQ2,
  348. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  349. .offs = 1 << 6,
  350. },
  351. [MAX8925_IRQ_VCHG_TMR_FAULT] = {
  352. .reg = MAX8925_CHG_IRQ2,
  353. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  354. .offs = 1 << 7,
  355. },
  356. [MAX8925_IRQ_GPM_RSTIN] = {
  357. .reg = MAX8925_ON_OFF_IRQ1,
  358. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  359. .offs = 1 << 0,
  360. },
  361. [MAX8925_IRQ_GPM_MPL] = {
  362. .reg = MAX8925_ON_OFF_IRQ1,
  363. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  364. .offs = 1 << 1,
  365. },
  366. [MAX8925_IRQ_GPM_SW_3SEC] = {
  367. .reg = MAX8925_ON_OFF_IRQ1,
  368. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  369. .offs = 1 << 2,
  370. },
  371. [MAX8925_IRQ_GPM_EXTON_F] = {
  372. .reg = MAX8925_ON_OFF_IRQ1,
  373. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  374. .offs = 1 << 3,
  375. },
  376. [MAX8925_IRQ_GPM_EXTON_R] = {
  377. .reg = MAX8925_ON_OFF_IRQ1,
  378. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  379. .offs = 1 << 4,
  380. },
  381. [MAX8925_IRQ_GPM_SW_1SEC] = {
  382. .reg = MAX8925_ON_OFF_IRQ1,
  383. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  384. .offs = 1 << 5,
  385. },
  386. [MAX8925_IRQ_GPM_SW_F] = {
  387. .reg = MAX8925_ON_OFF_IRQ1,
  388. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  389. .offs = 1 << 6,
  390. },
  391. [MAX8925_IRQ_GPM_SW_R] = {
  392. .reg = MAX8925_ON_OFF_IRQ1,
  393. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  394. .offs = 1 << 7,
  395. },
  396. [MAX8925_IRQ_GPM_SYSCKEN_F] = {
  397. .reg = MAX8925_ON_OFF_IRQ2,
  398. .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
  399. .offs = 1 << 0,
  400. },
  401. [MAX8925_IRQ_GPM_SYSCKEN_R] = {
  402. .reg = MAX8925_ON_OFF_IRQ2,
  403. .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
  404. .offs = 1 << 1,
  405. },
  406. [MAX8925_IRQ_RTC_ALARM1] = {
  407. .reg = MAX8925_RTC_IRQ,
  408. .mask_reg = MAX8925_RTC_IRQ_MASK,
  409. .offs = 1 << 2,
  410. .flags = FLAGS_RTC,
  411. },
  412. [MAX8925_IRQ_RTC_ALARM0] = {
  413. .reg = MAX8925_RTC_IRQ,
  414. .mask_reg = MAX8925_RTC_IRQ_MASK,
  415. .offs = 1 << 3,
  416. .flags = FLAGS_RTC,
  417. },
  418. [MAX8925_IRQ_TSC_STICK] = {
  419. .reg = MAX8925_TSC_IRQ,
  420. .mask_reg = MAX8925_TSC_IRQ_MASK,
  421. .offs = 1 << 0,
  422. .flags = FLAGS_ADC,
  423. .tsc_irq = 1,
  424. },
  425. [MAX8925_IRQ_TSC_NSTICK] = {
  426. .reg = MAX8925_TSC_IRQ,
  427. .mask_reg = MAX8925_TSC_IRQ_MASK,
  428. .offs = 1 << 1,
  429. .flags = FLAGS_ADC,
  430. .tsc_irq = 1,
  431. },
  432. };
  433. static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip,
  434. int irq)
  435. {
  436. return &max8925_irqs[irq - chip->irq_base];
  437. }
  438. static irqreturn_t max8925_irq(int irq, void *data)
  439. {
  440. struct max8925_chip *chip = data;
  441. struct max8925_irq_data *irq_data;
  442. struct i2c_client *i2c;
  443. int read_reg = -1, value = 0;
  444. int i;
  445. for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
  446. irq_data = &max8925_irqs[i];
  447. /* TSC IRQ should be serviced in max8925_tsc_irq() */
  448. if (irq_data->tsc_irq)
  449. continue;
  450. if (irq_data->flags == FLAGS_RTC)
  451. i2c = chip->rtc;
  452. else if (irq_data->flags == FLAGS_ADC)
  453. i2c = chip->adc;
  454. else
  455. i2c = chip->i2c;
  456. if (read_reg != irq_data->reg) {
  457. read_reg = irq_data->reg;
  458. value = max8925_reg_read(i2c, irq_data->reg);
  459. }
  460. if (value & irq_data->enable)
  461. handle_nested_irq(chip->irq_base + i);
  462. }
  463. return IRQ_HANDLED;
  464. }
  465. static irqreturn_t max8925_tsc_irq(int irq, void *data)
  466. {
  467. struct max8925_chip *chip = data;
  468. struct max8925_irq_data *irq_data;
  469. struct i2c_client *i2c;
  470. int read_reg = -1, value = 0;
  471. int i;
  472. for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
  473. irq_data = &max8925_irqs[i];
  474. /* non TSC IRQ should be serviced in max8925_irq() */
  475. if (!irq_data->tsc_irq)
  476. continue;
  477. if (irq_data->flags == FLAGS_RTC)
  478. i2c = chip->rtc;
  479. else if (irq_data->flags == FLAGS_ADC)
  480. i2c = chip->adc;
  481. else
  482. i2c = chip->i2c;
  483. if (read_reg != irq_data->reg) {
  484. read_reg = irq_data->reg;
  485. value = max8925_reg_read(i2c, irq_data->reg);
  486. }
  487. if (value & irq_data->enable)
  488. handle_nested_irq(chip->irq_base + i);
  489. }
  490. return IRQ_HANDLED;
  491. }
  492. static void max8925_irq_lock(struct irq_data *data)
  493. {
  494. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  495. mutex_lock(&chip->irq_lock);
  496. }
  497. static void max8925_irq_sync_unlock(struct irq_data *data)
  498. {
  499. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  500. struct max8925_irq_data *irq_data;
  501. static unsigned char cache_chg[2] = {0xff, 0xff};
  502. static unsigned char cache_on[2] = {0xff, 0xff};
  503. static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
  504. unsigned char irq_chg[2], irq_on[2];
  505. unsigned char irq_rtc, irq_tsc;
  506. int i;
  507. /* Load cached value. In initial, all IRQs are masked */
  508. irq_chg[0] = cache_chg[0];
  509. irq_chg[1] = cache_chg[1];
  510. irq_on[0] = cache_on[0];
  511. irq_on[1] = cache_on[1];
  512. irq_rtc = cache_rtc;
  513. irq_tsc = cache_tsc;
  514. for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
  515. irq_data = &max8925_irqs[i];
  516. /* 1 -- disable, 0 -- enable */
  517. switch (irq_data->mask_reg) {
  518. case MAX8925_CHG_IRQ1_MASK:
  519. irq_chg[0] &= ~irq_data->enable;
  520. break;
  521. case MAX8925_CHG_IRQ2_MASK:
  522. irq_chg[1] &= ~irq_data->enable;
  523. break;
  524. case MAX8925_ON_OFF_IRQ1_MASK:
  525. irq_on[0] &= ~irq_data->enable;
  526. break;
  527. case MAX8925_ON_OFF_IRQ2_MASK:
  528. irq_on[1] &= ~irq_data->enable;
  529. break;
  530. case MAX8925_RTC_IRQ_MASK:
  531. irq_rtc &= ~irq_data->enable;
  532. break;
  533. case MAX8925_TSC_IRQ_MASK:
  534. irq_tsc &= ~irq_data->enable;
  535. break;
  536. default:
  537. dev_err(chip->dev, "wrong IRQ\n");
  538. break;
  539. }
  540. }
  541. /* update mask into registers */
  542. if (cache_chg[0] != irq_chg[0]) {
  543. cache_chg[0] = irq_chg[0];
  544. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
  545. irq_chg[0]);
  546. }
  547. if (cache_chg[1] != irq_chg[1]) {
  548. cache_chg[1] = irq_chg[1];
  549. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
  550. irq_chg[1]);
  551. }
  552. if (cache_on[0] != irq_on[0]) {
  553. cache_on[0] = irq_on[0];
  554. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
  555. irq_on[0]);
  556. }
  557. if (cache_on[1] != irq_on[1]) {
  558. cache_on[1] = irq_on[1];
  559. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
  560. irq_on[1]);
  561. }
  562. if (cache_rtc != irq_rtc) {
  563. cache_rtc = irq_rtc;
  564. max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
  565. }
  566. if (cache_tsc != irq_tsc) {
  567. cache_tsc = irq_tsc;
  568. max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
  569. }
  570. mutex_unlock(&chip->irq_lock);
  571. }
  572. static void max8925_irq_enable(struct irq_data *data)
  573. {
  574. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  575. max8925_irqs[data->irq - chip->irq_base].enable
  576. = max8925_irqs[data->irq - chip->irq_base].offs;
  577. }
  578. static void max8925_irq_disable(struct irq_data *data)
  579. {
  580. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  581. max8925_irqs[data->irq - chip->irq_base].enable = 0;
  582. }
  583. static struct irq_chip max8925_irq_chip = {
  584. .name = "max8925",
  585. .irq_bus_lock = max8925_irq_lock,
  586. .irq_bus_sync_unlock = max8925_irq_sync_unlock,
  587. .irq_enable = max8925_irq_enable,
  588. .irq_disable = max8925_irq_disable,
  589. };
  590. static int max8925_irq_domain_map(struct irq_domain *d, unsigned int virq,
  591. irq_hw_number_t hw)
  592. {
  593. irq_set_chip_data(virq, d->host_data);
  594. irq_set_chip_and_handler(virq, &max8925_irq_chip, handle_edge_irq);
  595. irq_set_nested_thread(virq, 1);
  596. irq_set_noprobe(virq);
  597. return 0;
  598. }
  599. static const struct irq_domain_ops max8925_irq_domain_ops = {
  600. .map = max8925_irq_domain_map,
  601. .xlate = irq_domain_xlate_onetwocell,
  602. };
  603. static int max8925_irq_init(struct max8925_chip *chip, int irq,
  604. struct max8925_platform_data *pdata)
  605. {
  606. unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
  607. int ret;
  608. struct device_node *node = chip->dev->of_node;
  609. /* clear all interrupts */
  610. max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
  611. max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
  612. max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
  613. max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
  614. max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
  615. max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
  616. /* mask all interrupts except for TSC */
  617. max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
  618. max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
  619. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
  620. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
  621. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
  622. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
  623. max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
  624. mutex_init(&chip->irq_lock);
  625. chip->irq_base = irq_alloc_descs(-1, 0, MAX8925_NR_IRQS, 0);
  626. if (chip->irq_base < 0) {
  627. dev_err(chip->dev, "Failed to allocate interrupts, ret:%d\n",
  628. chip->irq_base);
  629. return -EBUSY;
  630. }
  631. irq_domain_add_legacy(node, MAX8925_NR_IRQS, chip->irq_base, 0,
  632. &max8925_irq_domain_ops, chip);
  633. /* request irq handler for pmic main irq*/
  634. chip->core_irq = irq;
  635. if (!chip->core_irq)
  636. return -EBUSY;
  637. ret = request_threaded_irq(irq, NULL, max8925_irq, flags | IRQF_ONESHOT,
  638. "max8925", chip);
  639. if (ret) {
  640. dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
  641. chip->core_irq = 0;
  642. return -EBUSY;
  643. }
  644. /* request irq handler for pmic tsc irq*/
  645. /* mask TSC interrupt */
  646. max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
  647. if (!pdata->tsc_irq) {
  648. dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
  649. return 0;
  650. }
  651. chip->tsc_irq = pdata->tsc_irq;
  652. ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
  653. flags | IRQF_ONESHOT, "max8925-tsc", chip);
  654. if (ret) {
  655. dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
  656. chip->tsc_irq = 0;
  657. }
  658. return 0;
  659. }
  660. static void init_regulator(struct max8925_chip *chip,
  661. struct max8925_platform_data *pdata)
  662. {
  663. int ret;
  664. if (!pdata)
  665. return;
  666. if (pdata->sd1) {
  667. reg_devs[0].platform_data = pdata->sd1;
  668. reg_devs[0].pdata_size = sizeof(struct regulator_init_data);
  669. }
  670. if (pdata->sd2) {
  671. reg_devs[1].platform_data = pdata->sd2;
  672. reg_devs[1].pdata_size = sizeof(struct regulator_init_data);
  673. }
  674. if (pdata->sd3) {
  675. reg_devs[2].platform_data = pdata->sd3;
  676. reg_devs[2].pdata_size = sizeof(struct regulator_init_data);
  677. }
  678. if (pdata->ldo1) {
  679. reg_devs[3].platform_data = pdata->ldo1;
  680. reg_devs[3].pdata_size = sizeof(struct regulator_init_data);
  681. }
  682. if (pdata->ldo2) {
  683. reg_devs[4].platform_data = pdata->ldo2;
  684. reg_devs[4].pdata_size = sizeof(struct regulator_init_data);
  685. }
  686. if (pdata->ldo3) {
  687. reg_devs[5].platform_data = pdata->ldo3;
  688. reg_devs[5].pdata_size = sizeof(struct regulator_init_data);
  689. }
  690. if (pdata->ldo4) {
  691. reg_devs[6].platform_data = pdata->ldo4;
  692. reg_devs[6].pdata_size = sizeof(struct regulator_init_data);
  693. }
  694. if (pdata->ldo5) {
  695. reg_devs[7].platform_data = pdata->ldo5;
  696. reg_devs[7].pdata_size = sizeof(struct regulator_init_data);
  697. }
  698. if (pdata->ldo6) {
  699. reg_devs[8].platform_data = pdata->ldo6;
  700. reg_devs[8].pdata_size = sizeof(struct regulator_init_data);
  701. }
  702. if (pdata->ldo7) {
  703. reg_devs[9].platform_data = pdata->ldo7;
  704. reg_devs[9].pdata_size = sizeof(struct regulator_init_data);
  705. }
  706. if (pdata->ldo8) {
  707. reg_devs[10].platform_data = pdata->ldo8;
  708. reg_devs[10].pdata_size = sizeof(struct regulator_init_data);
  709. }
  710. if (pdata->ldo9) {
  711. reg_devs[11].platform_data = pdata->ldo9;
  712. reg_devs[11].pdata_size = sizeof(struct regulator_init_data);
  713. }
  714. if (pdata->ldo10) {
  715. reg_devs[12].platform_data = pdata->ldo10;
  716. reg_devs[12].pdata_size = sizeof(struct regulator_init_data);
  717. }
  718. if (pdata->ldo11) {
  719. reg_devs[13].platform_data = pdata->ldo11;
  720. reg_devs[13].pdata_size = sizeof(struct regulator_init_data);
  721. }
  722. if (pdata->ldo12) {
  723. reg_devs[14].platform_data = pdata->ldo12;
  724. reg_devs[14].pdata_size = sizeof(struct regulator_init_data);
  725. }
  726. if (pdata->ldo13) {
  727. reg_devs[15].platform_data = pdata->ldo13;
  728. reg_devs[15].pdata_size = sizeof(struct regulator_init_data);
  729. }
  730. if (pdata->ldo14) {
  731. reg_devs[16].platform_data = pdata->ldo14;
  732. reg_devs[16].pdata_size = sizeof(struct regulator_init_data);
  733. }
  734. if (pdata->ldo15) {
  735. reg_devs[17].platform_data = pdata->ldo15;
  736. reg_devs[17].pdata_size = sizeof(struct regulator_init_data);
  737. }
  738. if (pdata->ldo16) {
  739. reg_devs[18].platform_data = pdata->ldo16;
  740. reg_devs[18].pdata_size = sizeof(struct regulator_init_data);
  741. }
  742. if (pdata->ldo17) {
  743. reg_devs[19].platform_data = pdata->ldo17;
  744. reg_devs[19].pdata_size = sizeof(struct regulator_init_data);
  745. }
  746. if (pdata->ldo18) {
  747. reg_devs[20].platform_data = pdata->ldo18;
  748. reg_devs[20].pdata_size = sizeof(struct regulator_init_data);
  749. }
  750. if (pdata->ldo19) {
  751. reg_devs[21].platform_data = pdata->ldo19;
  752. reg_devs[21].pdata_size = sizeof(struct regulator_init_data);
  753. }
  754. if (pdata->ldo20) {
  755. reg_devs[22].platform_data = pdata->ldo20;
  756. reg_devs[22].pdata_size = sizeof(struct regulator_init_data);
  757. }
  758. ret = mfd_add_devices(chip->dev, 0, reg_devs, ARRAY_SIZE(reg_devs),
  759. NULL, 0, NULL);
  760. if (ret < 0) {
  761. dev_err(chip->dev, "Failed to add regulator subdev\n");
  762. return;
  763. }
  764. }
  765. int max8925_device_init(struct max8925_chip *chip,
  766. struct max8925_platform_data *pdata)
  767. {
  768. int ret;
  769. max8925_irq_init(chip, chip->i2c->irq, pdata);
  770. if (pdata && (pdata->power || pdata->touch)) {
  771. /* enable ADC to control internal reference */
  772. max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
  773. /* enable internal reference for ADC */
  774. max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
  775. /* check for internal reference IRQ */
  776. do {
  777. ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
  778. } while (ret & MAX8925_NREF_OK);
  779. /* enaable ADC scheduler, interval is 1 second */
  780. max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
  781. }
  782. /* enable Momentary Power Loss */
  783. max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
  784. ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
  785. ARRAY_SIZE(rtc_devs),
  786. NULL, chip->irq_base, NULL);
  787. if (ret < 0) {
  788. dev_err(chip->dev, "Failed to add rtc subdev\n");
  789. goto out;
  790. }
  791. ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
  792. ARRAY_SIZE(onkey_devs),
  793. NULL, chip->irq_base, NULL);
  794. if (ret < 0) {
  795. dev_err(chip->dev, "Failed to add onkey subdev\n");
  796. goto out_dev;
  797. }
  798. init_regulator(chip, pdata);
  799. if (pdata && pdata->backlight) {
  800. bk_devs[0].platform_data = &pdata->backlight;
  801. bk_devs[0].pdata_size = sizeof(struct max8925_backlight_pdata);
  802. }
  803. ret = mfd_add_devices(chip->dev, 0, bk_devs, ARRAY_SIZE(bk_devs),
  804. NULL, 0, NULL);
  805. if (ret < 0) {
  806. dev_err(chip->dev, "Failed to add backlight subdev\n");
  807. goto out_dev;
  808. }
  809. ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
  810. ARRAY_SIZE(power_devs),
  811. NULL, 0, NULL);
  812. if (ret < 0) {
  813. dev_err(chip->dev,
  814. "Failed to add power supply subdev, err = %d\n", ret);
  815. goto out_dev;
  816. }
  817. if (pdata && pdata->touch) {
  818. ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
  819. ARRAY_SIZE(touch_devs),
  820. NULL, chip->tsc_irq, NULL);
  821. if (ret < 0) {
  822. dev_err(chip->dev, "Failed to add touch subdev\n");
  823. goto out_dev;
  824. }
  825. }
  826. return 0;
  827. out_dev:
  828. mfd_remove_devices(chip->dev);
  829. out:
  830. return ret;
  831. }
  832. void max8925_device_exit(struct max8925_chip *chip)
  833. {
  834. if (chip->core_irq)
  835. free_irq(chip->core_irq, chip);
  836. if (chip->tsc_irq)
  837. free_irq(chip->tsc_irq, chip);
  838. mfd_remove_devices(chip->dev);
  839. }