exynos-lpass.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
  4. *
  5. * Authors: Inha Song <[email protected]>
  6. * Sylwester Nawrocki <[email protected]>
  7. *
  8. * Samsung Exynos SoC series Low Power Audio Subsystem driver.
  9. *
  10. * This module provides regmap for the Top SFR region and instantiates
  11. * devices for IP blocks like DMAC, I2S, UART.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/regmap.h>
  22. #include <linux/soc/samsung/exynos-regs-pmu.h>
  23. #include <linux/types.h>
  24. /* LPASS Top register definitions */
  25. #define SFR_LPASS_CORE_SW_RESET 0x08
  26. #define LPASS_SB_SW_RESET BIT(11)
  27. #define LPASS_UART_SW_RESET BIT(10)
  28. #define LPASS_PCM_SW_RESET BIT(9)
  29. #define LPASS_I2S_SW_RESET BIT(8)
  30. #define LPASS_WDT1_SW_RESET BIT(4)
  31. #define LPASS_WDT0_SW_RESET BIT(3)
  32. #define LPASS_TIMER_SW_RESET BIT(2)
  33. #define LPASS_MEM_SW_RESET BIT(1)
  34. #define LPASS_DMA_SW_RESET BIT(0)
  35. #define SFR_LPASS_INTR_CA5_MASK 0x48
  36. #define SFR_LPASS_INTR_CPU_MASK 0x58
  37. #define LPASS_INTR_APM BIT(9)
  38. #define LPASS_INTR_MIF BIT(8)
  39. #define LPASS_INTR_TIMER BIT(7)
  40. #define LPASS_INTR_DMA BIT(6)
  41. #define LPASS_INTR_GPIO BIT(5)
  42. #define LPASS_INTR_I2S BIT(4)
  43. #define LPASS_INTR_PCM BIT(3)
  44. #define LPASS_INTR_SLIMBUS BIT(2)
  45. #define LPASS_INTR_UART BIT(1)
  46. #define LPASS_INTR_SFR BIT(0)
  47. struct exynos_lpass {
  48. /* pointer to the LPASS TOP regmap */
  49. struct regmap *top;
  50. struct clk *sfr0_clk;
  51. };
  52. static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
  53. {
  54. unsigned int val = 0;
  55. regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
  56. val &= ~mask;
  57. regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
  58. usleep_range(100, 150);
  59. val |= mask;
  60. regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
  61. }
  62. static void exynos_lpass_enable(struct exynos_lpass *lpass)
  63. {
  64. clk_prepare_enable(lpass->sfr0_clk);
  65. /* Unmask SFR, DMA and I2S interrupt */
  66. regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
  67. LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
  68. regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
  69. LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
  70. LPASS_INTR_UART);
  71. exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
  72. exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
  73. exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
  74. exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
  75. }
  76. static void exynos_lpass_disable(struct exynos_lpass *lpass)
  77. {
  78. /* Mask any unmasked IP interrupt sources */
  79. regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
  80. regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
  81. clk_disable_unprepare(lpass->sfr0_clk);
  82. }
  83. static const struct regmap_config exynos_lpass_reg_conf = {
  84. .reg_bits = 32,
  85. .reg_stride = 4,
  86. .val_bits = 32,
  87. .max_register = 0xfc,
  88. .fast_io = true,
  89. };
  90. static int exynos_lpass_probe(struct platform_device *pdev)
  91. {
  92. struct device *dev = &pdev->dev;
  93. struct exynos_lpass *lpass;
  94. void __iomem *base_top;
  95. struct resource *res;
  96. lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
  97. if (!lpass)
  98. return -ENOMEM;
  99. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  100. base_top = devm_ioremap_resource(dev, res);
  101. if (IS_ERR(base_top))
  102. return PTR_ERR(base_top);
  103. lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
  104. if (IS_ERR(lpass->sfr0_clk))
  105. return PTR_ERR(lpass->sfr0_clk);
  106. lpass->top = regmap_init_mmio(dev, base_top,
  107. &exynos_lpass_reg_conf);
  108. if (IS_ERR(lpass->top)) {
  109. dev_err(dev, "LPASS top regmap initialization failed\n");
  110. return PTR_ERR(lpass->top);
  111. }
  112. platform_set_drvdata(pdev, lpass);
  113. pm_runtime_set_active(dev);
  114. pm_runtime_enable(dev);
  115. exynos_lpass_enable(lpass);
  116. return devm_of_platform_populate(dev);
  117. }
  118. static int exynos_lpass_remove(struct platform_device *pdev)
  119. {
  120. struct exynos_lpass *lpass = platform_get_drvdata(pdev);
  121. exynos_lpass_disable(lpass);
  122. pm_runtime_disable(&pdev->dev);
  123. if (!pm_runtime_status_suspended(&pdev->dev))
  124. exynos_lpass_disable(lpass);
  125. regmap_exit(lpass->top);
  126. return 0;
  127. }
  128. static int __maybe_unused exynos_lpass_suspend(struct device *dev)
  129. {
  130. struct exynos_lpass *lpass = dev_get_drvdata(dev);
  131. exynos_lpass_disable(lpass);
  132. return 0;
  133. }
  134. static int __maybe_unused exynos_lpass_resume(struct device *dev)
  135. {
  136. struct exynos_lpass *lpass = dev_get_drvdata(dev);
  137. exynos_lpass_enable(lpass);
  138. return 0;
  139. }
  140. static const struct dev_pm_ops lpass_pm_ops = {
  141. SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
  142. SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  143. pm_runtime_force_resume)
  144. };
  145. static const struct of_device_id exynos_lpass_of_match[] = {
  146. { .compatible = "samsung,exynos5433-lpass" },
  147. { },
  148. };
  149. MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
  150. static struct platform_driver exynos_lpass_driver = {
  151. .driver = {
  152. .name = "exynos-lpass",
  153. .pm = &lpass_pm_ops,
  154. .of_match_table = exynos_lpass_of_match,
  155. },
  156. .probe = exynos_lpass_probe,
  157. .remove = exynos_lpass_remove,
  158. };
  159. module_platform_driver(exynos_lpass_driver);
  160. MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
  161. MODULE_LICENSE("GPL v2");