omap_ssi_regs.h 5.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Hardware definitions for SSI.
  3. *
  4. * Copyright (C) 2010 Nokia Corporation. All rights reserved.
  5. *
  6. * Contact: Carlos Chinea <[email protected]>
  7. */
  8. #ifndef __OMAP_SSI_REGS_H__
  9. #define __OMAP_SSI_REGS_H__
  10. /*
  11. * SSI SYS registers
  12. */
  13. #define SSI_REVISION_REG 0
  14. # define SSI_REV_MAJOR 0xf0
  15. # define SSI_REV_MINOR 0xf
  16. #define SSI_SYSCONFIG_REG 0x10
  17. # define SSI_AUTOIDLE (1 << 0)
  18. # define SSI_SOFTRESET (1 << 1)
  19. # define SSI_SIDLEMODE_FORCE 0
  20. # define SSI_SIDLEMODE_NO (1 << 3)
  21. # define SSI_SIDLEMODE_SMART (1 << 4)
  22. # define SSI_SIDLEMODE_MASK 0x18
  23. # define SSI_MIDLEMODE_FORCE 0
  24. # define SSI_MIDLEMODE_NO (1 << 12)
  25. # define SSI_MIDLEMODE_SMART (1 << 13)
  26. # define SSI_MIDLEMODE_MASK 0x3000
  27. #define SSI_SYSSTATUS_REG 0x14
  28. # define SSI_RESETDONE 1
  29. #define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
  30. #define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
  31. # define SSI_DATAACCEPT(channel) (1 << (channel))
  32. # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8))
  33. # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16))
  34. # define SSI_ERROROCCURED (1 << 24)
  35. # define SSI_BREAKDETECTED (1 << 25)
  36. #define SSI_GDD_MPU_IRQ_STATUS_REG 0x0800
  37. #define SSI_GDD_MPU_IRQ_ENABLE_REG 0x0804
  38. # define SSI_GDD_LCH(channel) (1 << (channel))
  39. #define SSI_WAKE_REG(port) (0xc00 + ((port) * 0x10))
  40. #define SSI_CLEAR_WAKE_REG(port) (0xc04 + ((port) * 0x10))
  41. #define SSI_SET_WAKE_REG(port) (0xc08 + ((port) * 0x10))
  42. # define SSI_WAKE(channel) (1 << (channel))
  43. # define SSI_WAKE_MASK 0xff
  44. /*
  45. * SSI SST registers
  46. */
  47. #define SSI_SST_ID_REG 0
  48. #define SSI_SST_MODE_REG 4
  49. # define SSI_MODE_VAL_MASK 3
  50. # define SSI_MODE_SLEEP 0
  51. # define SSI_MODE_STREAM 1
  52. # define SSI_MODE_FRAME 2
  53. # define SSI_MODE_MULTIPOINTS 3
  54. #define SSI_SST_FRAMESIZE_REG 8
  55. # define SSI_FRAMESIZE_DEFAULT 31
  56. #define SSI_SST_TXSTATE_REG 0xc
  57. # define SSI_TXSTATE_IDLE 0
  58. #define SSI_SST_BUFSTATE_REG 0x10
  59. # define SSI_FULL(channel) (1 << (channel))
  60. #define SSI_SST_DIVISOR_REG 0x18
  61. # define SSI_MAX_DIVISOR 127
  62. #define SSI_SST_BREAK_REG 0x20
  63. #define SSI_SST_CHANNELS_REG 0x24
  64. # define SSI_CHANNELS_DEFAULT 4
  65. #define SSI_SST_ARBMODE_REG 0x28
  66. # define SSI_ARBMODE_ROUNDROBIN 0
  67. # define SSI_ARBMODE_PRIORITY 1
  68. #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
  69. #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
  70. /*
  71. * SSI SSR registers
  72. */
  73. #define SSI_SSR_ID_REG 0
  74. #define SSI_SSR_MODE_REG 4
  75. #define SSI_SSR_FRAMESIZE_REG 8
  76. #define SSI_SSR_RXSTATE_REG 0xc
  77. #define SSI_SSR_BUFSTATE_REG 0x10
  78. # define SSI_NOTEMPTY(channel) (1 << (channel))
  79. #define SSI_SSR_BREAK_REG 0x1c
  80. #define SSI_SSR_ERROR_REG 0x20
  81. #define SSI_SSR_ERRORACK_REG 0x24
  82. #define SSI_SSR_OVERRUN_REG 0x2c
  83. #define SSI_SSR_OVERRUNACK_REG 0x30
  84. #define SSI_SSR_TIMEOUT_REG 0x34
  85. # define SSI_TIMEOUT_DEFAULT 0
  86. #define SSI_SSR_CHANNELS_REG 0x28
  87. #define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
  88. #define SSI_SSR_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
  89. /*
  90. * SSI GDD registers
  91. */
  92. #define SSI_GDD_HW_ID_REG 0
  93. #define SSI_GDD_PPORT_ID_REG 0x10
  94. #define SSI_GDD_MPORT_ID_REG 0x14
  95. #define SSI_GDD_PPORT_SR_REG 0x20
  96. #define SSI_GDD_MPORT_SR_REG 0x24
  97. # define SSI_ACTIVE_LCH_NUM_MASK 0xff
  98. #define SSI_GDD_TEST_REG 0x40
  99. # define SSI_TEST 1
  100. #define SSI_GDD_GCR_REG 0x100
  101. # define SSI_CLK_AUTOGATING_ON (1 << 3)
  102. # define SSI_FREE (1 << 2)
  103. # define SSI_SWITCH_OFF (1 << 0)
  104. #define SSI_GDD_GRST_REG 0x200
  105. # define SSI_SWRESET 1
  106. #define SSI_GDD_CSDP_REG(channel) (0x800 + ((channel) * 0x40))
  107. # define SSI_DST_BURST_EN_MASK 0xc000
  108. # define SSI_DST_SINGLE_ACCESS0 0
  109. # define SSI_DST_SINGLE_ACCESS (1 << 14)
  110. # define SSI_DST_BURST_4x32_BIT (2 << 14)
  111. # define SSI_DST_BURST_8x32_BIT (3 << 14)
  112. # define SSI_DST_MASK 0x1e00
  113. # define SSI_DST_MEMORY_PORT (8 << 9)
  114. # define SSI_DST_PERIPHERAL_PORT (9 << 9)
  115. # define SSI_SRC_BURST_EN_MASK 0x180
  116. # define SSI_SRC_SINGLE_ACCESS0 0
  117. # define SSI_SRC_SINGLE_ACCESS (1 << 7)
  118. # define SSI_SRC_BURST_4x32_BIT (2 << 7)
  119. # define SSI_SRC_BURST_8x32_BIT (3 << 7)
  120. # define SSI_SRC_MASK 0x3c
  121. # define SSI_SRC_MEMORY_PORT (8 << 2)
  122. # define SSI_SRC_PERIPHERAL_PORT (9 << 2)
  123. # define SSI_DATA_TYPE_MASK 3
  124. # define SSI_DATA_TYPE_S32 2
  125. #define SSI_GDD_CCR_REG(channel) (0x802 + ((channel) * 0x40))
  126. # define SSI_DST_AMODE_MASK (3 << 14)
  127. # define SSI_DST_AMODE_CONST 0
  128. # define SSI_DST_AMODE_POSTINC (1 << 12)
  129. # define SSI_SRC_AMODE_MASK (3 << 12)
  130. # define SSI_SRC_AMODE_CONST 0
  131. # define SSI_SRC_AMODE_POSTINC (1 << 12)
  132. # define SSI_CCR_ENABLE (1 << 7)
  133. # define SSI_CCR_SYNC_MASK 0x1f
  134. #define SSI_GDD_CICR_REG(channel) (0x804 + ((channel) * 0x40))
  135. # define SSI_BLOCK_IE (1 << 5)
  136. # define SSI_HALF_IE (1 << 2)
  137. # define SSI_TOUT_IE (1 << 0)
  138. #define SSI_GDD_CSR_REG(channel) (0x806 + ((channel) * 0x40))
  139. # define SSI_CSR_SYNC (1 << 6)
  140. # define SSI_CSR_BLOCK (1 << 5)
  141. # define SSI_CSR_HALF (1 << 2)
  142. # define SSI_CSR_TOUR (1 << 0)
  143. #define SSI_GDD_CSSA_REG(channel) (0x808 + ((channel) * 0x40))
  144. #define SSI_GDD_CDSA_REG(channel) (0x80c + ((channel) * 0x40))
  145. #define SSI_GDD_CEN_REG(channel) (0x810 + ((channel) * 0x40))
  146. #define SSI_GDD_CSAC_REG(channel) (0x818 + ((channel) * 0x40))
  147. #define SSI_GDD_CDAC_REG(channel) (0x81a + ((channel) * 0x40))
  148. #define SSI_GDD_CLNK_CTRL_REG(channel) (0x828 + ((channel) * 0x40))
  149. # define SSI_ENABLE_LNK (1 << 15)
  150. # define SSI_STOP_LNK (1 << 14)
  151. # define SSI_NEXT_CH_ID_MASK 0xf
  152. #endif /* __OMAP_SSI_REGS_H__ */