hw-ish.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * H/W layer of ISHTP provider device (ISH)
  4. *
  5. * Copyright (c) 2014-2016, Intel Corporation.
  6. */
  7. #ifndef _ISHTP_HW_ISH_H_
  8. #define _ISHTP_HW_ISH_H_
  9. #include <linux/pci.h>
  10. #include <linux/interrupt.h>
  11. #include "hw-ish-regs.h"
  12. #include "ishtp-dev.h"
  13. #define CHV_DEVICE_ID 0x22D8
  14. #define BXT_Ax_DEVICE_ID 0x0AA2
  15. #define BXT_Bx_DEVICE_ID 0x1AA2
  16. #define APL_Ax_DEVICE_ID 0x5AA2
  17. #define SPT_Ax_DEVICE_ID 0x9D35
  18. #define CNL_Ax_DEVICE_ID 0x9DFC
  19. #define GLK_Ax_DEVICE_ID 0x31A2
  20. #define CNL_H_DEVICE_ID 0xA37C
  21. #define ICL_MOBILE_DEVICE_ID 0x34FC
  22. #define SPT_H_DEVICE_ID 0xA135
  23. #define CML_LP_DEVICE_ID 0x02FC
  24. #define CMP_H_DEVICE_ID 0x06FC
  25. #define EHL_Ax_DEVICE_ID 0x4BB3
  26. #define TGL_LP_DEVICE_ID 0xA0FC
  27. #define TGL_H_DEVICE_ID 0x43FC
  28. #define ADL_S_DEVICE_ID 0x7AF8
  29. #define ADL_P_DEVICE_ID 0x51FC
  30. #define ADL_N_DEVICE_ID 0x54FC
  31. #define RPL_S_DEVICE_ID 0x7A78
  32. #define MTL_P_DEVICE_ID 0x7E45
  33. #define ARL_H_DEVICE_ID 0x7745
  34. #define REVISION_ID_CHT_A0 0x6
  35. #define REVISION_ID_CHT_Ax_SI 0x0
  36. #define REVISION_ID_CHT_Bx_SI 0x10
  37. #define REVISION_ID_CHT_Kx_SI 0x20
  38. #define REVISION_ID_CHT_Dx_SI 0x30
  39. #define REVISION_ID_CHT_B0 0xB0
  40. #define REVISION_ID_SI_MASK 0x70
  41. struct ipc_rst_payload_type {
  42. uint16_t reset_id;
  43. uint16_t reserved;
  44. };
  45. struct time_sync_format {
  46. uint8_t ts1_source;
  47. uint8_t ts2_source;
  48. uint16_t reserved;
  49. } __packed;
  50. struct ipc_time_update_msg {
  51. uint64_t primary_host_time;
  52. struct time_sync_format sync_info;
  53. uint64_t secondary_host_time;
  54. } __packed;
  55. enum {
  56. HOST_UTC_TIME_USEC = 0,
  57. HOST_SYSTEM_TIME_USEC = 1
  58. };
  59. struct ish_hw {
  60. void __iomem *mem_addr;
  61. };
  62. /*
  63. * ISH FW status type
  64. */
  65. enum {
  66. FWSTS_AFTER_RESET = 0,
  67. FWSTS_WAIT_FOR_HOST = 4,
  68. FWSTS_START_KERNEL_DMA = 5,
  69. FWSTS_FW_IS_RUNNING = 7,
  70. FWSTS_SENSOR_APP_LOADED = 8,
  71. FWSTS_SENSOR_APP_RUNNING = 15
  72. };
  73. #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
  74. irqreturn_t ish_irq_handler(int irq, void *dev_id);
  75. struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
  76. int ish_hw_start(struct ishtp_device *dev);
  77. void ish_device_disable(struct ishtp_device *dev);
  78. int ish_disable_dma(struct ishtp_device *dev);
  79. void ish_set_host_ready(struct ishtp_device *dev);
  80. #endif /* _ISHTP_HW_ISH_H_ */