gpio-zevio.c 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPIO controller in LSI ZEVIO SoCs.
  4. *
  5. * Author: Fabian Vogt <[email protected]>
  6. */
  7. #include <linux/spinlock.h>
  8. #include <linux/errno.h>
  9. #include <linux/init.h>
  10. #include <linux/bitops.h>
  11. #include <linux/io.h>
  12. #include <linux/of_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/gpio/driver.h>
  15. /*
  16. * Memory layout:
  17. * This chip has four gpio sections, each controls 8 GPIOs.
  18. * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
  19. * Disclaimer: Reverse engineered!
  20. * For more information refer to:
  21. * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
  22. *
  23. * 0x00-0x3F: Section 0
  24. * +0x00: Masked interrupt status (read-only)
  25. * +0x04: R: Interrupt status W: Reset interrupt status
  26. * +0x08: R: Interrupt mask W: Mask interrupt
  27. * +0x0C: W: Unmask interrupt (write-only)
  28. * +0x10: Direction: I/O=1/0
  29. * +0x14: Output
  30. * +0x18: Input (read-only)
  31. * +0x20: R: Level interrupt W: Set as level interrupt
  32. * 0x40-0x7F: Section 1
  33. * 0x80-0xBF: Section 2
  34. * 0xC0-0xFF: Section 3
  35. */
  36. #define ZEVIO_GPIO_SECTION_SIZE 0x40
  37. /* Offsets to various registers */
  38. #define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
  39. #define ZEVIO_GPIO_INT_STATUS 0x04
  40. #define ZEVIO_GPIO_INT_UNMASK 0x08
  41. #define ZEVIO_GPIO_INT_MASK 0x0C
  42. #define ZEVIO_GPIO_DIRECTION 0x10
  43. #define ZEVIO_GPIO_OUTPUT 0x14
  44. #define ZEVIO_GPIO_INPUT 0x18
  45. #define ZEVIO_GPIO_INT_STICKY 0x20
  46. /* Bit number of GPIO in its section */
  47. #define ZEVIO_GPIO_BIT(gpio) (gpio&7)
  48. struct zevio_gpio {
  49. struct gpio_chip chip;
  50. spinlock_t lock;
  51. void __iomem *regs;
  52. };
  53. static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
  54. unsigned port_offset)
  55. {
  56. unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
  57. return readl(IOMEM(c->regs + section_offset + port_offset));
  58. }
  59. static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
  60. unsigned port_offset, u32 val)
  61. {
  62. unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
  63. writel(val, IOMEM(c->regs + section_offset + port_offset));
  64. }
  65. /* Functions for struct gpio_chip */
  66. static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
  67. {
  68. struct zevio_gpio *controller = gpiochip_get_data(chip);
  69. u32 val, dir;
  70. spin_lock(&controller->lock);
  71. dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
  72. if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
  73. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
  74. else
  75. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
  76. spin_unlock(&controller->lock);
  77. return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
  78. }
  79. static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
  80. {
  81. struct zevio_gpio *controller = gpiochip_get_data(chip);
  82. u32 val;
  83. spin_lock(&controller->lock);
  84. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
  85. if (value)
  86. val |= BIT(ZEVIO_GPIO_BIT(pin));
  87. else
  88. val &= ~BIT(ZEVIO_GPIO_BIT(pin));
  89. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
  90. spin_unlock(&controller->lock);
  91. }
  92. static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
  93. {
  94. struct zevio_gpio *controller = gpiochip_get_data(chip);
  95. u32 val;
  96. spin_lock(&controller->lock);
  97. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
  98. val |= BIT(ZEVIO_GPIO_BIT(pin));
  99. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
  100. spin_unlock(&controller->lock);
  101. return 0;
  102. }
  103. static int zevio_gpio_direction_output(struct gpio_chip *chip,
  104. unsigned pin, int value)
  105. {
  106. struct zevio_gpio *controller = gpiochip_get_data(chip);
  107. u32 val;
  108. spin_lock(&controller->lock);
  109. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
  110. if (value)
  111. val |= BIT(ZEVIO_GPIO_BIT(pin));
  112. else
  113. val &= ~BIT(ZEVIO_GPIO_BIT(pin));
  114. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
  115. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
  116. val &= ~BIT(ZEVIO_GPIO_BIT(pin));
  117. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
  118. spin_unlock(&controller->lock);
  119. return 0;
  120. }
  121. static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
  122. {
  123. /*
  124. * TODO: Implement IRQs.
  125. * Not implemented yet due to weird lockups
  126. */
  127. return -ENXIO;
  128. }
  129. static const struct gpio_chip zevio_gpio_chip = {
  130. .direction_input = zevio_gpio_direction_input,
  131. .direction_output = zevio_gpio_direction_output,
  132. .set = zevio_gpio_set,
  133. .get = zevio_gpio_get,
  134. .to_irq = zevio_gpio_to_irq,
  135. .base = 0,
  136. .owner = THIS_MODULE,
  137. .ngpio = 32,
  138. .of_gpio_n_cells = 2,
  139. };
  140. /* Initialization */
  141. static int zevio_gpio_probe(struct platform_device *pdev)
  142. {
  143. struct zevio_gpio *controller;
  144. int status, i;
  145. controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
  146. if (!controller)
  147. return -ENOMEM;
  148. platform_set_drvdata(pdev, controller);
  149. /* Copy our reference */
  150. controller->chip = zevio_gpio_chip;
  151. controller->chip.parent = &pdev->dev;
  152. controller->regs = devm_platform_ioremap_resource(pdev, 0);
  153. if (IS_ERR(controller->regs))
  154. return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs),
  155. "failed to ioremap memory resource\n");
  156. status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller);
  157. if (status) {
  158. dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
  159. return status;
  160. }
  161. spin_lock_init(&controller->lock);
  162. /* Disable interrupts, they only cause errors */
  163. for (i = 0; i < controller->chip.ngpio; i += 8)
  164. zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
  165. dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n");
  166. return 0;
  167. }
  168. static const struct of_device_id zevio_gpio_of_match[] = {
  169. { .compatible = "lsi,zevio-gpio", },
  170. { },
  171. };
  172. static struct platform_driver zevio_gpio_driver = {
  173. .driver = {
  174. .name = "gpio-zevio",
  175. .of_match_table = zevio_gpio_of_match,
  176. .suppress_bind_attrs = true,
  177. },
  178. .probe = zevio_gpio_probe,
  179. };
  180. builtin_platform_driver(zevio_gpio_driver);