gpio-tegra186.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2022 NVIDIA Corporation
  4. *
  5. * Author: Thierry Reding <[email protected]>
  6. * Dipen Patel <[email protected]>
  7. */
  8. #include <linux/gpio/driver.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/irq.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/hte.h>
  15. #include <dt-bindings/gpio/tegra186-gpio.h>
  16. #include <dt-bindings/gpio/tegra194-gpio.h>
  17. #include <dt-bindings/gpio/tegra234-gpio.h>
  18. #include <dt-bindings/gpio/tegra241-gpio.h>
  19. /* security registers */
  20. #define TEGRA186_GPIO_CTL_SCR 0x0c
  21. #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
  22. #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
  23. #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
  24. /* control registers */
  25. #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
  26. #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
  27. #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
  28. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
  29. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
  30. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
  31. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
  32. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
  33. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
  34. #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
  35. #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
  36. #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
  37. #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
  38. #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
  39. #define TEGRA186_GPIO_INPUT 0x08
  40. #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
  41. #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
  42. #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
  43. #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
  44. #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
  45. #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
  46. #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
  47. struct tegra_gpio_port {
  48. const char *name;
  49. unsigned int bank;
  50. unsigned int port;
  51. unsigned int pins;
  52. };
  53. struct tegra186_pin_range {
  54. unsigned int offset;
  55. const char *group;
  56. };
  57. struct tegra_gpio_soc {
  58. const struct tegra_gpio_port *ports;
  59. unsigned int num_ports;
  60. const char *name;
  61. unsigned int instance;
  62. unsigned int num_irqs_per_bank;
  63. const struct tegra186_pin_range *pin_ranges;
  64. unsigned int num_pin_ranges;
  65. const char *pinmux;
  66. bool has_gte;
  67. };
  68. struct tegra_gpio {
  69. struct gpio_chip gpio;
  70. unsigned int num_irq;
  71. unsigned int *irq;
  72. const struct tegra_gpio_soc *soc;
  73. unsigned int num_irqs_per_bank;
  74. unsigned int num_banks;
  75. void __iomem *secure;
  76. void __iomem *base;
  77. };
  78. static const struct tegra_gpio_port *
  79. tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
  80. {
  81. unsigned int start = 0, i;
  82. for (i = 0; i < gpio->soc->num_ports; i++) {
  83. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  84. if (*pin >= start && *pin < start + port->pins) {
  85. *pin -= start;
  86. return port;
  87. }
  88. start += port->pins;
  89. }
  90. return NULL;
  91. }
  92. static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
  93. unsigned int pin)
  94. {
  95. const struct tegra_gpio_port *port;
  96. unsigned int offset;
  97. port = tegra186_gpio_get_port(gpio, &pin);
  98. if (!port)
  99. return NULL;
  100. offset = port->bank * 0x1000 + port->port * 0x200;
  101. return gpio->base + offset + pin * 0x20;
  102. }
  103. static int tegra186_gpio_get_direction(struct gpio_chip *chip,
  104. unsigned int offset)
  105. {
  106. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  107. void __iomem *base;
  108. u32 value;
  109. base = tegra186_gpio_get_base(gpio, offset);
  110. if (WARN_ON(base == NULL))
  111. return -ENODEV;
  112. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  113. if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
  114. return GPIO_LINE_DIRECTION_OUT;
  115. return GPIO_LINE_DIRECTION_IN;
  116. }
  117. static int tegra186_gpio_direction_input(struct gpio_chip *chip,
  118. unsigned int offset)
  119. {
  120. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  121. void __iomem *base;
  122. u32 value;
  123. base = tegra186_gpio_get_base(gpio, offset);
  124. if (WARN_ON(base == NULL))
  125. return -ENODEV;
  126. value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
  127. value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
  128. writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
  129. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  130. value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
  131. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
  132. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  133. return 0;
  134. }
  135. static int tegra186_gpio_direction_output(struct gpio_chip *chip,
  136. unsigned int offset, int level)
  137. {
  138. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  139. void __iomem *base;
  140. u32 value;
  141. /* configure output level first */
  142. chip->set(chip, offset, level);
  143. base = tegra186_gpio_get_base(gpio, offset);
  144. if (WARN_ON(base == NULL))
  145. return -EINVAL;
  146. /* set the direction */
  147. value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
  148. value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
  149. writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
  150. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  151. value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
  152. value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
  153. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  154. return 0;
  155. }
  156. #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
  157. static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
  158. unsigned long flags)
  159. {
  160. struct tegra_gpio *gpio;
  161. void __iomem *base;
  162. int value;
  163. if (!gc)
  164. return -EINVAL;
  165. gpio = gpiochip_get_data(gc);
  166. if (!gpio)
  167. return -ENODEV;
  168. base = tegra186_gpio_get_base(gpio, offset);
  169. if (WARN_ON(base == NULL))
  170. return -EINVAL;
  171. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  172. value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
  173. if (flags == HTE_BOTH_EDGES) {
  174. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
  175. } else if (flags == HTE_RISING_EDGE_TS) {
  176. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  177. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  178. } else if (flags == HTE_FALLING_EDGE_TS) {
  179. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  180. }
  181. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  182. return 0;
  183. }
  184. static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
  185. unsigned long flags)
  186. {
  187. struct tegra_gpio *gpio;
  188. void __iomem *base;
  189. int value;
  190. if (!gc)
  191. return -EINVAL;
  192. gpio = gpiochip_get_data(gc);
  193. if (!gpio)
  194. return -ENODEV;
  195. base = tegra186_gpio_get_base(gpio, offset);
  196. if (WARN_ON(base == NULL))
  197. return -EINVAL;
  198. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  199. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
  200. if (flags == HTE_BOTH_EDGES) {
  201. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
  202. } else if (flags == HTE_RISING_EDGE_TS) {
  203. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  204. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  205. } else if (flags == HTE_FALLING_EDGE_TS) {
  206. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  207. }
  208. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  209. return 0;
  210. }
  211. static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
  212. {
  213. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  214. void __iomem *base;
  215. u32 value;
  216. base = tegra186_gpio_get_base(gpio, offset);
  217. if (WARN_ON(base == NULL))
  218. return -ENODEV;
  219. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  220. if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
  221. value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
  222. else
  223. value = readl(base + TEGRA186_GPIO_INPUT);
  224. return value & BIT(0);
  225. }
  226. static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
  227. int level)
  228. {
  229. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  230. void __iomem *base;
  231. u32 value;
  232. base = tegra186_gpio_get_base(gpio, offset);
  233. if (WARN_ON(base == NULL))
  234. return;
  235. value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
  236. if (level == 0)
  237. value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
  238. else
  239. value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
  240. writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
  241. }
  242. static int tegra186_gpio_set_config(struct gpio_chip *chip,
  243. unsigned int offset,
  244. unsigned long config)
  245. {
  246. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  247. u32 debounce, value;
  248. void __iomem *base;
  249. base = tegra186_gpio_get_base(gpio, offset);
  250. if (base == NULL)
  251. return -ENXIO;
  252. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  253. return -ENOTSUPP;
  254. debounce = pinconf_to_config_argument(config);
  255. /*
  256. * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
  257. * time.
  258. */
  259. if (debounce > 255000)
  260. return -EINVAL;
  261. debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
  262. value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
  263. writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
  264. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  265. value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
  266. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  267. return 0;
  268. }
  269. static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
  270. {
  271. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  272. struct pinctrl_dev *pctldev;
  273. struct device_node *np;
  274. unsigned int i, j;
  275. int err;
  276. if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
  277. return 0;
  278. np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
  279. if (!np)
  280. return -ENODEV;
  281. pctldev = of_pinctrl_get(np);
  282. of_node_put(np);
  283. if (!pctldev)
  284. return -EPROBE_DEFER;
  285. for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
  286. unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
  287. const char *group = gpio->soc->pin_ranges[i].group;
  288. port = pin / 8;
  289. pin = pin % 8;
  290. if (port >= gpio->soc->num_ports) {
  291. dev_warn(chip->parent, "invalid port %u for %s\n",
  292. port, group);
  293. continue;
  294. }
  295. for (j = 0; j < port; j++)
  296. pin += gpio->soc->ports[j].pins;
  297. err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
  298. if (err < 0)
  299. return err;
  300. }
  301. return 0;
  302. }
  303. static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
  304. const struct of_phandle_args *spec,
  305. u32 *flags)
  306. {
  307. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  308. unsigned int port, pin, i, offset = 0;
  309. if (WARN_ON(chip->of_gpio_n_cells < 2))
  310. return -EINVAL;
  311. if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
  312. return -EINVAL;
  313. port = spec->args[0] / 8;
  314. pin = spec->args[0] % 8;
  315. if (port >= gpio->soc->num_ports) {
  316. dev_err(chip->parent, "invalid port number: %u\n", port);
  317. return -EINVAL;
  318. }
  319. for (i = 0; i < port; i++)
  320. offset += gpio->soc->ports[i].pins;
  321. if (flags)
  322. *flags = spec->args[1];
  323. return offset + pin;
  324. }
  325. #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
  326. static void tegra186_irq_ack(struct irq_data *data)
  327. {
  328. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  329. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  330. void __iomem *base;
  331. base = tegra186_gpio_get_base(gpio, data->hwirq);
  332. if (WARN_ON(base == NULL))
  333. return;
  334. writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
  335. }
  336. static void tegra186_irq_mask(struct irq_data *data)
  337. {
  338. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  339. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  340. void __iomem *base;
  341. u32 value;
  342. base = tegra186_gpio_get_base(gpio, data->hwirq);
  343. if (WARN_ON(base == NULL))
  344. return;
  345. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  346. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
  347. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  348. gpiochip_disable_irq(&gpio->gpio, data->hwirq);
  349. }
  350. static void tegra186_irq_unmask(struct irq_data *data)
  351. {
  352. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  353. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  354. void __iomem *base;
  355. u32 value;
  356. base = tegra186_gpio_get_base(gpio, data->hwirq);
  357. if (WARN_ON(base == NULL))
  358. return;
  359. gpiochip_enable_irq(&gpio->gpio, data->hwirq);
  360. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  361. value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
  362. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  363. }
  364. static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
  365. {
  366. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  367. struct tegra_gpio *gpio = to_tegra_gpio(gc);
  368. void __iomem *base;
  369. u32 value;
  370. base = tegra186_gpio_get_base(gpio, data->hwirq);
  371. if (WARN_ON(base == NULL))
  372. return -ENODEV;
  373. value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
  374. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
  375. value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  376. switch (type & IRQ_TYPE_SENSE_MASK) {
  377. case IRQ_TYPE_NONE:
  378. break;
  379. case IRQ_TYPE_EDGE_RISING:
  380. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  381. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  382. break;
  383. case IRQ_TYPE_EDGE_FALLING:
  384. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
  385. break;
  386. case IRQ_TYPE_EDGE_BOTH:
  387. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
  388. break;
  389. case IRQ_TYPE_LEVEL_HIGH:
  390. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
  391. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
  392. break;
  393. case IRQ_TYPE_LEVEL_LOW:
  394. value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
  395. break;
  396. default:
  397. return -EINVAL;
  398. }
  399. writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
  400. if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
  401. irq_set_handler_locked(data, handle_level_irq);
  402. else
  403. irq_set_handler_locked(data, handle_edge_irq);
  404. if (data->parent_data)
  405. return irq_chip_set_type_parent(data, type);
  406. return 0;
  407. }
  408. static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
  409. {
  410. if (data->parent_data)
  411. return irq_chip_set_wake_parent(data, on);
  412. return 0;
  413. }
  414. static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
  415. {
  416. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  417. seq_printf(p, dev_name(gc->parent));
  418. }
  419. static const struct irq_chip tegra186_gpio_irq_chip = {
  420. .irq_ack = tegra186_irq_ack,
  421. .irq_mask = tegra186_irq_mask,
  422. .irq_unmask = tegra186_irq_unmask,
  423. .irq_set_type = tegra186_irq_set_type,
  424. .irq_set_wake = tegra186_irq_set_wake,
  425. .irq_print_chip = tegra186_irq_print_chip,
  426. .flags = IRQCHIP_IMMUTABLE,
  427. GPIOCHIP_IRQ_RESOURCE_HELPERS,
  428. };
  429. static void tegra186_gpio_irq(struct irq_desc *desc)
  430. {
  431. struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
  432. struct irq_domain *domain = gpio->gpio.irq.domain;
  433. struct irq_chip *chip = irq_desc_get_chip(desc);
  434. unsigned int parent = irq_desc_get_irq(desc);
  435. unsigned int i, j, offset = 0;
  436. chained_irq_enter(chip, desc);
  437. for (i = 0; i < gpio->soc->num_ports; i++) {
  438. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  439. unsigned int pin;
  440. unsigned long value;
  441. void __iomem *base;
  442. base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
  443. /* skip ports that are not associated with this bank */
  444. for (j = 0; j < gpio->num_irqs_per_bank; j++) {
  445. if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
  446. break;
  447. }
  448. if (j == gpio->num_irqs_per_bank)
  449. goto skip;
  450. value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
  451. for_each_set_bit(pin, &value, port->pins) {
  452. int ret = generic_handle_domain_irq(domain, offset + pin);
  453. WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
  454. }
  455. skip:
  456. offset += port->pins;
  457. }
  458. chained_irq_exit(chip, desc);
  459. }
  460. static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
  461. struct irq_fwspec *fwspec,
  462. unsigned long *hwirq,
  463. unsigned int *type)
  464. {
  465. struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
  466. unsigned int port, pin, i, offset = 0;
  467. if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
  468. return -EINVAL;
  469. if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
  470. return -EINVAL;
  471. port = fwspec->param[0] / 8;
  472. pin = fwspec->param[0] % 8;
  473. if (port >= gpio->soc->num_ports)
  474. return -EINVAL;
  475. for (i = 0; i < port; i++)
  476. offset += gpio->soc->ports[i].pins;
  477. *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  478. *hwirq = offset + pin;
  479. return 0;
  480. }
  481. static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
  482. union gpio_irq_fwspec *gfwspec,
  483. unsigned int parent_hwirq,
  484. unsigned int parent_type)
  485. {
  486. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  487. struct irq_fwspec *fwspec = &gfwspec->fwspec;
  488. fwspec->fwnode = chip->irq.parent_domain->fwnode;
  489. fwspec->param_count = 3;
  490. fwspec->param[0] = gpio->soc->instance;
  491. fwspec->param[1] = parent_hwirq;
  492. fwspec->param[2] = parent_type;
  493. return 0;
  494. }
  495. static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
  496. unsigned int hwirq,
  497. unsigned int type,
  498. unsigned int *parent_hwirq,
  499. unsigned int *parent_type)
  500. {
  501. *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
  502. *parent_type = type;
  503. return 0;
  504. }
  505. static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
  506. unsigned int offset)
  507. {
  508. struct tegra_gpio *gpio = gpiochip_get_data(chip);
  509. unsigned int i;
  510. for (i = 0; i < gpio->soc->num_ports; i++) {
  511. if (offset < gpio->soc->ports[i].pins)
  512. break;
  513. offset -= gpio->soc->ports[i].pins;
  514. }
  515. return offset + i * 8;
  516. }
  517. static const struct of_device_id tegra186_pmc_of_match[] = {
  518. { .compatible = "nvidia,tegra186-pmc" },
  519. { .compatible = "nvidia,tegra194-pmc" },
  520. { /* sentinel */ }
  521. };
  522. static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
  523. {
  524. struct device *dev = gpio->gpio.parent;
  525. unsigned int i, j;
  526. u32 value;
  527. for (i = 0; i < gpio->soc->num_ports; i++) {
  528. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  529. unsigned int offset, p = port->port;
  530. void __iomem *base;
  531. base = gpio->secure + port->bank * 0x1000 + 0x800;
  532. value = readl(base + TEGRA186_GPIO_CTL_SCR);
  533. /*
  534. * For controllers that haven't been locked down yet, make
  535. * sure to program the default interrupt route mapping.
  536. */
  537. if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
  538. (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
  539. /*
  540. * On Tegra194 and later, each pin can be routed to one or more
  541. * interrupts.
  542. */
  543. for (j = 0; j < gpio->num_irqs_per_bank; j++) {
  544. dev_dbg(dev, "programming default interrupt routing for port %s\n",
  545. port->name);
  546. offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
  547. /*
  548. * By default we only want to route GPIO pins to IRQ 0. This works
  549. * only under the assumption that we're running as the host kernel
  550. * and hence all GPIO pins are owned by Linux.
  551. *
  552. * For cases where Linux is the guest OS, the hypervisor will have
  553. * to configure the interrupt routing and pass only the valid
  554. * interrupts via device tree.
  555. */
  556. if (j == 0) {
  557. value = readl(base + offset);
  558. value = BIT(port->pins) - 1;
  559. writel(value, base + offset);
  560. }
  561. }
  562. }
  563. }
  564. }
  565. static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
  566. {
  567. struct device *dev = gpio->gpio.parent;
  568. if (gpio->num_irq > gpio->num_banks) {
  569. if (gpio->num_irq % gpio->num_banks != 0)
  570. goto error;
  571. }
  572. if (gpio->num_irq < gpio->num_banks)
  573. goto error;
  574. gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
  575. if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
  576. goto error;
  577. return 0;
  578. error:
  579. dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
  580. gpio->num_irq, gpio->num_banks);
  581. return -EINVAL;
  582. }
  583. static int tegra186_gpio_probe(struct platform_device *pdev)
  584. {
  585. unsigned int i, j, offset;
  586. struct gpio_irq_chip *irq;
  587. struct tegra_gpio *gpio;
  588. struct device_node *np;
  589. char **names;
  590. int err;
  591. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  592. if (!gpio)
  593. return -ENOMEM;
  594. gpio->soc = device_get_match_data(&pdev->dev);
  595. gpio->gpio.label = gpio->soc->name;
  596. gpio->gpio.parent = &pdev->dev;
  597. /* count the number of banks in the controller */
  598. for (i = 0; i < gpio->soc->num_ports; i++)
  599. if (gpio->soc->ports[i].bank > gpio->num_banks)
  600. gpio->num_banks = gpio->soc->ports[i].bank;
  601. gpio->num_banks++;
  602. /* get register apertures */
  603. gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
  604. if (IS_ERR(gpio->secure)) {
  605. gpio->secure = devm_platform_ioremap_resource(pdev, 0);
  606. if (IS_ERR(gpio->secure))
  607. return PTR_ERR(gpio->secure);
  608. }
  609. gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
  610. if (IS_ERR(gpio->base)) {
  611. gpio->base = devm_platform_ioremap_resource(pdev, 1);
  612. if (IS_ERR(gpio->base))
  613. return PTR_ERR(gpio->base);
  614. }
  615. err = platform_irq_count(pdev);
  616. if (err < 0)
  617. return err;
  618. gpio->num_irq = err;
  619. err = tegra186_gpio_irqs_per_bank(gpio);
  620. if (err < 0)
  621. return err;
  622. gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
  623. GFP_KERNEL);
  624. if (!gpio->irq)
  625. return -ENOMEM;
  626. for (i = 0; i < gpio->num_irq; i++) {
  627. err = platform_get_irq(pdev, i);
  628. if (err < 0)
  629. return err;
  630. gpio->irq[i] = err;
  631. }
  632. gpio->gpio.request = gpiochip_generic_request;
  633. gpio->gpio.free = gpiochip_generic_free;
  634. gpio->gpio.get_direction = tegra186_gpio_get_direction;
  635. gpio->gpio.direction_input = tegra186_gpio_direction_input;
  636. gpio->gpio.direction_output = tegra186_gpio_direction_output;
  637. gpio->gpio.get = tegra186_gpio_get;
  638. gpio->gpio.set = tegra186_gpio_set;
  639. gpio->gpio.set_config = tegra186_gpio_set_config;
  640. gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
  641. if (gpio->soc->has_gte) {
  642. gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
  643. gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
  644. }
  645. gpio->gpio.base = -1;
  646. for (i = 0; i < gpio->soc->num_ports; i++)
  647. gpio->gpio.ngpio += gpio->soc->ports[i].pins;
  648. names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
  649. sizeof(*names), GFP_KERNEL);
  650. if (!names)
  651. return -ENOMEM;
  652. for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
  653. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  654. char *name;
  655. for (j = 0; j < port->pins; j++) {
  656. name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
  657. "P%s.%02x", port->name, j);
  658. if (!name)
  659. return -ENOMEM;
  660. names[offset + j] = name;
  661. }
  662. offset += port->pins;
  663. }
  664. gpio->gpio.names = (const char * const *)names;
  665. #if defined(CONFIG_OF_GPIO)
  666. gpio->gpio.of_gpio_n_cells = 2;
  667. gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
  668. #endif /* CONFIG_OF_GPIO */
  669. irq = &gpio->gpio.irq;
  670. gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
  671. irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
  672. irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
  673. irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
  674. irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
  675. irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
  676. irq->handler = handle_simple_irq;
  677. irq->default_type = IRQ_TYPE_NONE;
  678. irq->parent_handler = tegra186_gpio_irq;
  679. irq->parent_handler_data = gpio;
  680. irq->num_parents = gpio->num_irq;
  681. /*
  682. * To simplify things, use a single interrupt per bank for now. Some
  683. * chips support up to 8 interrupts per bank, which can be useful to
  684. * distribute the load and decrease the processing latency for GPIOs
  685. * but it also requires a more complicated interrupt routing than we
  686. * currently program.
  687. */
  688. if (gpio->num_irqs_per_bank > 1) {
  689. irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
  690. sizeof(*irq->parents), GFP_KERNEL);
  691. if (!irq->parents)
  692. return -ENOMEM;
  693. for (i = 0; i < gpio->num_banks; i++)
  694. irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
  695. irq->num_parents = gpio->num_banks;
  696. } else {
  697. irq->num_parents = gpio->num_irq;
  698. irq->parents = gpio->irq;
  699. }
  700. if (gpio->soc->num_irqs_per_bank > 1)
  701. tegra186_gpio_init_route_mapping(gpio);
  702. np = of_find_matching_node(NULL, tegra186_pmc_of_match);
  703. if (np) {
  704. irq->parent_domain = irq_find_host(np);
  705. of_node_put(np);
  706. if (!irq->parent_domain)
  707. return -EPROBE_DEFER;
  708. }
  709. irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
  710. sizeof(*irq->map), GFP_KERNEL);
  711. if (!irq->map)
  712. return -ENOMEM;
  713. for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
  714. const struct tegra_gpio_port *port = &gpio->soc->ports[i];
  715. for (j = 0; j < port->pins; j++)
  716. irq->map[offset + j] = irq->parents[port->bank];
  717. offset += port->pins;
  718. }
  719. return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
  720. }
  721. #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
  722. [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
  723. .name = #_name, \
  724. .bank = _bank, \
  725. .port = _port, \
  726. .pins = _pins, \
  727. }
  728. static const struct tegra_gpio_port tegra186_main_ports[] = {
  729. TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
  730. TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
  731. TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
  732. TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
  733. TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
  734. TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
  735. TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
  736. TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
  737. TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
  738. TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
  739. TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
  740. TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
  741. TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
  742. TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
  743. TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
  744. TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
  745. TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
  746. TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
  747. TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
  748. TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
  749. TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
  750. TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
  751. TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
  752. };
  753. static const struct tegra_gpio_soc tegra186_main_soc = {
  754. .num_ports = ARRAY_SIZE(tegra186_main_ports),
  755. .ports = tegra186_main_ports,
  756. .name = "tegra186-gpio",
  757. .instance = 0,
  758. .num_irqs_per_bank = 1,
  759. };
  760. #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
  761. [TEGRA186_AON_GPIO_PORT_##_name] = { \
  762. .name = #_name, \
  763. .bank = _bank, \
  764. .port = _port, \
  765. .pins = _pins, \
  766. }
  767. static const struct tegra_gpio_port tegra186_aon_ports[] = {
  768. TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
  769. TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
  770. TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
  771. TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
  772. TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
  773. TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
  774. TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
  775. TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
  776. };
  777. static const struct tegra_gpio_soc tegra186_aon_soc = {
  778. .num_ports = ARRAY_SIZE(tegra186_aon_ports),
  779. .ports = tegra186_aon_ports,
  780. .name = "tegra186-gpio-aon",
  781. .instance = 1,
  782. .num_irqs_per_bank = 1,
  783. };
  784. #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
  785. [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
  786. .name = #_name, \
  787. .bank = _bank, \
  788. .port = _port, \
  789. .pins = _pins, \
  790. }
  791. static const struct tegra_gpio_port tegra194_main_ports[] = {
  792. TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
  793. TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
  794. TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
  795. TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
  796. TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
  797. TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
  798. TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
  799. TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
  800. TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
  801. TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
  802. TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
  803. TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
  804. TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
  805. TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
  806. TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
  807. TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
  808. TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
  809. TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
  810. TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
  811. TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
  812. TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
  813. TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
  814. TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
  815. TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
  816. TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
  817. TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
  818. TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
  819. TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
  820. };
  821. static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
  822. { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
  823. { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
  824. };
  825. static const struct tegra_gpio_soc tegra194_main_soc = {
  826. .num_ports = ARRAY_SIZE(tegra194_main_ports),
  827. .ports = tegra194_main_ports,
  828. .name = "tegra194-gpio",
  829. .instance = 0,
  830. .num_irqs_per_bank = 8,
  831. .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
  832. .pin_ranges = tegra194_main_pin_ranges,
  833. .pinmux = "nvidia,tegra194-pinmux",
  834. };
  835. #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
  836. [TEGRA194_AON_GPIO_PORT_##_name] = { \
  837. .name = #_name, \
  838. .bank = _bank, \
  839. .port = _port, \
  840. .pins = _pins, \
  841. }
  842. static const struct tegra_gpio_port tegra194_aon_ports[] = {
  843. TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
  844. TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
  845. TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
  846. TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
  847. TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
  848. };
  849. static const struct tegra_gpio_soc tegra194_aon_soc = {
  850. .num_ports = ARRAY_SIZE(tegra194_aon_ports),
  851. .ports = tegra194_aon_ports,
  852. .name = "tegra194-gpio-aon",
  853. .instance = 1,
  854. .num_irqs_per_bank = 8,
  855. .has_gte = true,
  856. };
  857. #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
  858. [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
  859. .name = #_name, \
  860. .bank = _bank, \
  861. .port = _port, \
  862. .pins = _pins, \
  863. }
  864. static const struct tegra_gpio_port tegra234_main_ports[] = {
  865. TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
  866. TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
  867. TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
  868. TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
  869. TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
  870. TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
  871. TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
  872. TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
  873. TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
  874. TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
  875. TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
  876. TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
  877. TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
  878. TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
  879. TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
  880. TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
  881. TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
  882. TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
  883. TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
  884. TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
  885. TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
  886. TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
  887. TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
  888. TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
  889. TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
  890. };
  891. static const struct tegra_gpio_soc tegra234_main_soc = {
  892. .num_ports = ARRAY_SIZE(tegra234_main_ports),
  893. .ports = tegra234_main_ports,
  894. .name = "tegra234-gpio",
  895. .instance = 0,
  896. .num_irqs_per_bank = 8,
  897. };
  898. #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
  899. [TEGRA234_AON_GPIO_PORT_##_name] = { \
  900. .name = #_name, \
  901. .bank = _bank, \
  902. .port = _port, \
  903. .pins = _pins, \
  904. }
  905. static const struct tegra_gpio_port tegra234_aon_ports[] = {
  906. TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
  907. TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
  908. TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
  909. TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
  910. TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
  911. TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
  912. };
  913. static const struct tegra_gpio_soc tegra234_aon_soc = {
  914. .num_ports = ARRAY_SIZE(tegra234_aon_ports),
  915. .ports = tegra234_aon_ports,
  916. .name = "tegra234-gpio-aon",
  917. .instance = 1,
  918. .num_irqs_per_bank = 8,
  919. };
  920. #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
  921. [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
  922. .name = #_name, \
  923. .bank = _bank, \
  924. .port = _port, \
  925. .pins = _pins, \
  926. }
  927. static const struct tegra_gpio_port tegra241_main_ports[] = {
  928. TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
  929. TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
  930. TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
  931. TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
  932. TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
  933. TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
  934. TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
  935. TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
  936. TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
  937. TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
  938. TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
  939. };
  940. static const struct tegra_gpio_soc tegra241_main_soc = {
  941. .num_ports = ARRAY_SIZE(tegra241_main_ports),
  942. .ports = tegra241_main_ports,
  943. .name = "tegra241-gpio",
  944. .instance = 0,
  945. .num_irqs_per_bank = 8,
  946. };
  947. #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
  948. [TEGRA241_AON_GPIO_PORT_##_name] = { \
  949. .name = #_name, \
  950. .bank = _bank, \
  951. .port = _port, \
  952. .pins = _pins, \
  953. }
  954. static const struct tegra_gpio_port tegra241_aon_ports[] = {
  955. TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
  956. TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
  957. };
  958. static const struct tegra_gpio_soc tegra241_aon_soc = {
  959. .num_ports = ARRAY_SIZE(tegra241_aon_ports),
  960. .ports = tegra241_aon_ports,
  961. .name = "tegra241-gpio-aon",
  962. .instance = 1,
  963. .num_irqs_per_bank = 8,
  964. };
  965. static const struct of_device_id tegra186_gpio_of_match[] = {
  966. {
  967. .compatible = "nvidia,tegra186-gpio",
  968. .data = &tegra186_main_soc
  969. }, {
  970. .compatible = "nvidia,tegra186-gpio-aon",
  971. .data = &tegra186_aon_soc
  972. }, {
  973. .compatible = "nvidia,tegra194-gpio",
  974. .data = &tegra194_main_soc
  975. }, {
  976. .compatible = "nvidia,tegra194-gpio-aon",
  977. .data = &tegra194_aon_soc
  978. }, {
  979. .compatible = "nvidia,tegra234-gpio",
  980. .data = &tegra234_main_soc
  981. }, {
  982. .compatible = "nvidia,tegra234-gpio-aon",
  983. .data = &tegra234_aon_soc
  984. }, {
  985. /* sentinel */
  986. }
  987. };
  988. MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
  989. static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
  990. { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
  991. { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
  992. { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
  993. { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
  994. { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
  995. { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
  996. {}
  997. };
  998. MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
  999. static struct platform_driver tegra186_gpio_driver = {
  1000. .driver = {
  1001. .name = "tegra186-gpio",
  1002. .of_match_table = tegra186_gpio_of_match,
  1003. .acpi_match_table = tegra186_gpio_acpi_match,
  1004. },
  1005. .probe = tegra186_gpio_probe,
  1006. };
  1007. module_platform_driver(tegra186_gpio_driver);
  1008. MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
  1009. MODULE_AUTHOR("Thierry Reding <[email protected]>");
  1010. MODULE_LICENSE("GPL v2");