gpio-sch.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * GPIO interface for Intel Poulsbo SCH
  4. *
  5. * Copyright (c) 2010 CompuLab Ltd
  6. * Author: Denis Turischev <[email protected]>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/bitops.h>
  10. #include <linux/errno.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/pci_ids.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/types.h>
  19. #define GEN 0x00
  20. #define GIO 0x04
  21. #define GLV 0x08
  22. #define GTPE 0x0c
  23. #define GTNE 0x10
  24. #define GGPE 0x14
  25. #define GSMI 0x18
  26. #define GTS 0x1c
  27. #define CORE_BANK_OFFSET 0x00
  28. #define RESUME_BANK_OFFSET 0x20
  29. /*
  30. * iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
  31. * Document Number: 328195-001
  32. */
  33. #define GPE0E_GPIO 14
  34. struct sch_gpio {
  35. struct gpio_chip chip;
  36. spinlock_t lock;
  37. unsigned short iobase;
  38. unsigned short resume_base;
  39. /* GPE handling */
  40. u32 gpe;
  41. acpi_gpe_handler gpe_handler;
  42. };
  43. static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
  44. unsigned int reg)
  45. {
  46. unsigned int base = CORE_BANK_OFFSET;
  47. if (gpio >= sch->resume_base) {
  48. gpio -= sch->resume_base;
  49. base = RESUME_BANK_OFFSET;
  50. }
  51. return base + reg + gpio / 8;
  52. }
  53. static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
  54. {
  55. if (gpio >= sch->resume_base)
  56. gpio -= sch->resume_base;
  57. return gpio % 8;
  58. }
  59. static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
  60. {
  61. unsigned short offset, bit;
  62. u8 reg_val;
  63. offset = sch_gpio_offset(sch, gpio, reg);
  64. bit = sch_gpio_bit(sch, gpio);
  65. reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
  66. return reg_val;
  67. }
  68. static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
  69. int val)
  70. {
  71. unsigned short offset, bit;
  72. u8 reg_val;
  73. offset = sch_gpio_offset(sch, gpio, reg);
  74. bit = sch_gpio_bit(sch, gpio);
  75. reg_val = inb(sch->iobase + offset);
  76. if (val)
  77. outb(reg_val | BIT(bit), sch->iobase + offset);
  78. else
  79. outb((reg_val & ~BIT(bit)), sch->iobase + offset);
  80. }
  81. static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
  82. {
  83. struct sch_gpio *sch = gpiochip_get_data(gc);
  84. unsigned long flags;
  85. spin_lock_irqsave(&sch->lock, flags);
  86. sch_gpio_reg_set(sch, gpio_num, GIO, 1);
  87. spin_unlock_irqrestore(&sch->lock, flags);
  88. return 0;
  89. }
  90. static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
  91. {
  92. struct sch_gpio *sch = gpiochip_get_data(gc);
  93. return sch_gpio_reg_get(sch, gpio_num, GLV);
  94. }
  95. static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
  96. {
  97. struct sch_gpio *sch = gpiochip_get_data(gc);
  98. unsigned long flags;
  99. spin_lock_irqsave(&sch->lock, flags);
  100. sch_gpio_reg_set(sch, gpio_num, GLV, val);
  101. spin_unlock_irqrestore(&sch->lock, flags);
  102. }
  103. static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
  104. int val)
  105. {
  106. struct sch_gpio *sch = gpiochip_get_data(gc);
  107. unsigned long flags;
  108. spin_lock_irqsave(&sch->lock, flags);
  109. sch_gpio_reg_set(sch, gpio_num, GIO, 0);
  110. spin_unlock_irqrestore(&sch->lock, flags);
  111. /*
  112. * according to the datasheet, writing to the level register has no
  113. * effect when GPIO is programmed as input.
  114. * Actually the level register is read-only when configured as input.
  115. * Thus presetting the output level before switching to output is _NOT_ possible.
  116. * Hence we set the level after configuring the GPIO as output.
  117. * But we cannot prevent a short low pulse if direction is set to high
  118. * and an external pull-up is connected.
  119. */
  120. sch_gpio_set(gc, gpio_num, val);
  121. return 0;
  122. }
  123. static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
  124. {
  125. struct sch_gpio *sch = gpiochip_get_data(gc);
  126. if (sch_gpio_reg_get(sch, gpio_num, GIO))
  127. return GPIO_LINE_DIRECTION_IN;
  128. return GPIO_LINE_DIRECTION_OUT;
  129. }
  130. static const struct gpio_chip sch_gpio_chip = {
  131. .label = "sch_gpio",
  132. .owner = THIS_MODULE,
  133. .direction_input = sch_gpio_direction_in,
  134. .get = sch_gpio_get,
  135. .direction_output = sch_gpio_direction_out,
  136. .set = sch_gpio_set,
  137. .get_direction = sch_gpio_get_direction,
  138. };
  139. static int sch_irq_type(struct irq_data *d, unsigned int type)
  140. {
  141. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  142. struct sch_gpio *sch = gpiochip_get_data(gc);
  143. irq_hw_number_t gpio_num = irqd_to_hwirq(d);
  144. unsigned long flags;
  145. int rising, falling;
  146. switch (type & IRQ_TYPE_SENSE_MASK) {
  147. case IRQ_TYPE_EDGE_RISING:
  148. rising = 1;
  149. falling = 0;
  150. break;
  151. case IRQ_TYPE_EDGE_FALLING:
  152. rising = 0;
  153. falling = 1;
  154. break;
  155. case IRQ_TYPE_EDGE_BOTH:
  156. rising = 1;
  157. falling = 1;
  158. break;
  159. default:
  160. return -EINVAL;
  161. }
  162. spin_lock_irqsave(&sch->lock, flags);
  163. sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
  164. sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
  165. irq_set_handler_locked(d, handle_edge_irq);
  166. spin_unlock_irqrestore(&sch->lock, flags);
  167. return 0;
  168. }
  169. static void sch_irq_ack(struct irq_data *d)
  170. {
  171. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  172. struct sch_gpio *sch = gpiochip_get_data(gc);
  173. irq_hw_number_t gpio_num = irqd_to_hwirq(d);
  174. unsigned long flags;
  175. spin_lock_irqsave(&sch->lock, flags);
  176. sch_gpio_reg_set(sch, gpio_num, GTS, 1);
  177. spin_unlock_irqrestore(&sch->lock, flags);
  178. }
  179. static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
  180. {
  181. struct sch_gpio *sch = gpiochip_get_data(gc);
  182. unsigned long flags;
  183. spin_lock_irqsave(&sch->lock, flags);
  184. sch_gpio_reg_set(sch, gpio_num, GGPE, val);
  185. spin_unlock_irqrestore(&sch->lock, flags);
  186. }
  187. static void sch_irq_mask(struct irq_data *d)
  188. {
  189. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  190. irq_hw_number_t gpio_num = irqd_to_hwirq(d);
  191. sch_irq_mask_unmask(gc, gpio_num, 0);
  192. gpiochip_disable_irq(gc, gpio_num);
  193. }
  194. static void sch_irq_unmask(struct irq_data *d)
  195. {
  196. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  197. irq_hw_number_t gpio_num = irqd_to_hwirq(d);
  198. gpiochip_enable_irq(gc, gpio_num);
  199. sch_irq_mask_unmask(gc, gpio_num, 1);
  200. }
  201. static const struct irq_chip sch_irqchip = {
  202. .name = "sch_gpio",
  203. .irq_ack = sch_irq_ack,
  204. .irq_mask = sch_irq_mask,
  205. .irq_unmask = sch_irq_unmask,
  206. .irq_set_type = sch_irq_type,
  207. .flags = IRQCHIP_IMMUTABLE,
  208. GPIOCHIP_IRQ_RESOURCE_HELPERS,
  209. };
  210. static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
  211. {
  212. struct sch_gpio *sch = context;
  213. struct gpio_chip *gc = &sch->chip;
  214. unsigned long core_status, resume_status;
  215. unsigned long pending;
  216. unsigned long flags;
  217. int offset;
  218. u32 ret;
  219. spin_lock_irqsave(&sch->lock, flags);
  220. core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
  221. resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
  222. spin_unlock_irqrestore(&sch->lock, flags);
  223. pending = (resume_status << sch->resume_base) | core_status;
  224. for_each_set_bit(offset, &pending, sch->chip.ngpio)
  225. generic_handle_domain_irq(gc->irq.domain, offset);
  226. /* Set returning value depending on whether we handled an interrupt */
  227. ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
  228. /* Acknowledge GPE to ACPICA */
  229. ret |= ACPI_REENABLE_GPE;
  230. return ret;
  231. }
  232. static void sch_gpio_remove_gpe_handler(void *data)
  233. {
  234. struct sch_gpio *sch = data;
  235. acpi_disable_gpe(NULL, sch->gpe);
  236. acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
  237. }
  238. static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
  239. {
  240. struct device *dev = sch->chip.parent;
  241. acpi_status status;
  242. status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
  243. sch->gpe_handler, sch);
  244. if (ACPI_FAILURE(status)) {
  245. dev_err(dev, "Failed to install GPE handler for %u: %s\n",
  246. sch->gpe, acpi_format_exception(status));
  247. return -ENODEV;
  248. }
  249. status = acpi_enable_gpe(NULL, sch->gpe);
  250. if (ACPI_FAILURE(status)) {
  251. dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
  252. sch->gpe, acpi_format_exception(status));
  253. acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
  254. return -ENODEV;
  255. }
  256. return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
  257. }
  258. static int sch_gpio_probe(struct platform_device *pdev)
  259. {
  260. struct gpio_irq_chip *girq;
  261. struct sch_gpio *sch;
  262. struct resource *res;
  263. int ret;
  264. sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
  265. if (!sch)
  266. return -ENOMEM;
  267. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  268. if (!res)
  269. return -EBUSY;
  270. if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
  271. pdev->name))
  272. return -EBUSY;
  273. spin_lock_init(&sch->lock);
  274. sch->iobase = res->start;
  275. sch->chip = sch_gpio_chip;
  276. sch->chip.label = dev_name(&pdev->dev);
  277. sch->chip.parent = &pdev->dev;
  278. switch (pdev->id) {
  279. case PCI_DEVICE_ID_INTEL_SCH_LPC:
  280. sch->resume_base = 10;
  281. sch->chip.ngpio = 14;
  282. /*
  283. * GPIO[6:0] enabled by default
  284. * GPIO7 is configured by the CMC as SLPIOVR
  285. * Enable GPIO[9:8] core powered gpios explicitly
  286. */
  287. sch_gpio_reg_set(sch, 8, GEN, 1);
  288. sch_gpio_reg_set(sch, 9, GEN, 1);
  289. /*
  290. * SUS_GPIO[2:0] enabled by default
  291. * Enable SUS_GPIO3 resume powered gpio explicitly
  292. */
  293. sch_gpio_reg_set(sch, 13, GEN, 1);
  294. break;
  295. case PCI_DEVICE_ID_INTEL_ITC_LPC:
  296. sch->resume_base = 5;
  297. sch->chip.ngpio = 14;
  298. break;
  299. case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
  300. sch->resume_base = 21;
  301. sch->chip.ngpio = 30;
  302. break;
  303. case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
  304. sch->resume_base = 2;
  305. sch->chip.ngpio = 8;
  306. break;
  307. default:
  308. return -ENODEV;
  309. }
  310. platform_set_drvdata(pdev, sch);
  311. girq = &sch->chip.irq;
  312. gpio_irq_chip_set_chip(girq, &sch_irqchip);
  313. girq->num_parents = 0;
  314. girq->parents = NULL;
  315. girq->parent_handler = NULL;
  316. girq->default_type = IRQ_TYPE_NONE;
  317. girq->handler = handle_bad_irq;
  318. /* GPE setup is optional */
  319. sch->gpe = GPE0E_GPIO;
  320. sch->gpe_handler = sch_gpio_gpe_handler;
  321. ret = sch_gpio_install_gpe_handler(sch);
  322. if (ret)
  323. dev_warn(&pdev->dev, "Can't setup GPE, no IRQ support\n");
  324. return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
  325. }
  326. static struct platform_driver sch_gpio_driver = {
  327. .driver = {
  328. .name = "sch_gpio",
  329. },
  330. .probe = sch_gpio_probe,
  331. };
  332. module_platform_driver(sch_gpio_driver);
  333. MODULE_AUTHOR("Denis Turischev <[email protected]>");
  334. MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
  335. MODULE_LICENSE("GPL v2");
  336. MODULE_ALIAS("platform:sch_gpio");