gpio-rockchip.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 MundoReader S.L.
  4. * Author: Heiko Stuebner <[email protected]>
  5. *
  6. * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/pinctrl/consumer.h>
  22. #include <linux/pinctrl/pinconf-generic.h>
  23. #include <linux/regmap.h>
  24. #include "../pinctrl/core.h"
  25. #include "../pinctrl/pinctrl-rockchip.h"
  26. #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
  27. #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
  28. #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
  29. static const struct rockchip_gpio_regs gpio_regs_v1 = {
  30. .port_dr = 0x00,
  31. .port_ddr = 0x04,
  32. .int_en = 0x30,
  33. .int_mask = 0x34,
  34. .int_type = 0x38,
  35. .int_polarity = 0x3c,
  36. .int_status = 0x40,
  37. .int_rawstatus = 0x44,
  38. .debounce = 0x48,
  39. .port_eoi = 0x4c,
  40. .ext_port = 0x50,
  41. };
  42. static const struct rockchip_gpio_regs gpio_regs_v2 = {
  43. .port_dr = 0x00,
  44. .port_ddr = 0x08,
  45. .int_en = 0x10,
  46. .int_mask = 0x18,
  47. .int_type = 0x20,
  48. .int_polarity = 0x28,
  49. .int_bothedge = 0x30,
  50. .int_status = 0x50,
  51. .int_rawstatus = 0x58,
  52. .debounce = 0x38,
  53. .dbclk_div_en = 0x40,
  54. .dbclk_div_con = 0x48,
  55. .port_eoi = 0x60,
  56. .ext_port = 0x70,
  57. .version_id = 0x78,
  58. };
  59. static inline void gpio_writel_v2(u32 val, void __iomem *reg)
  60. {
  61. writel((val & 0xffff) | 0xffff0000, reg);
  62. writel((val >> 16) | 0xffff0000, reg + 0x4);
  63. }
  64. static inline u32 gpio_readl_v2(void __iomem *reg)
  65. {
  66. return readl(reg + 0x4) << 16 | readl(reg);
  67. }
  68. static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
  69. u32 value, unsigned int offset)
  70. {
  71. void __iomem *reg = bank->reg_base + offset;
  72. if (bank->gpio_type == GPIO_TYPE_V2)
  73. gpio_writel_v2(value, reg);
  74. else
  75. writel(value, reg);
  76. }
  77. static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
  78. unsigned int offset)
  79. {
  80. void __iomem *reg = bank->reg_base + offset;
  81. u32 value;
  82. if (bank->gpio_type == GPIO_TYPE_V2)
  83. value = gpio_readl_v2(reg);
  84. else
  85. value = readl(reg);
  86. return value;
  87. }
  88. static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
  89. u32 bit, u32 value,
  90. unsigned int offset)
  91. {
  92. void __iomem *reg = bank->reg_base + offset;
  93. u32 data;
  94. if (bank->gpio_type == GPIO_TYPE_V2) {
  95. if (value)
  96. data = BIT(bit % 16) | BIT(bit % 16 + 16);
  97. else
  98. data = BIT(bit % 16 + 16);
  99. writel(data, bit >= 16 ? reg + 0x4 : reg);
  100. } else {
  101. data = readl(reg);
  102. data &= ~BIT(bit);
  103. if (value)
  104. data |= BIT(bit);
  105. writel(data, reg);
  106. }
  107. }
  108. static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
  109. u32 bit, unsigned int offset)
  110. {
  111. void __iomem *reg = bank->reg_base + offset;
  112. u32 data;
  113. if (bank->gpio_type == GPIO_TYPE_V2) {
  114. data = readl(bit >= 16 ? reg + 0x4 : reg);
  115. data >>= bit % 16;
  116. } else {
  117. data = readl(reg);
  118. data >>= bit;
  119. }
  120. return data & (0x1);
  121. }
  122. static int rockchip_gpio_get_direction(struct gpio_chip *chip,
  123. unsigned int offset)
  124. {
  125. struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
  126. u32 data;
  127. data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
  128. if (data)
  129. return GPIO_LINE_DIRECTION_OUT;
  130. return GPIO_LINE_DIRECTION_IN;
  131. }
  132. static int rockchip_gpio_set_direction(struct gpio_chip *chip,
  133. unsigned int offset, bool input)
  134. {
  135. struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
  136. unsigned long flags;
  137. u32 data = input ? 0 : 1;
  138. if (input)
  139. pinctrl_gpio_direction_input(bank->pin_base + offset);
  140. else
  141. pinctrl_gpio_direction_output(bank->pin_base + offset);
  142. raw_spin_lock_irqsave(&bank->slock, flags);
  143. rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
  144. raw_spin_unlock_irqrestore(&bank->slock, flags);
  145. return 0;
  146. }
  147. static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
  148. int value)
  149. {
  150. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  151. unsigned long flags;
  152. raw_spin_lock_irqsave(&bank->slock, flags);
  153. rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
  154. raw_spin_unlock_irqrestore(&bank->slock, flags);
  155. }
  156. static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
  157. {
  158. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  159. u32 data;
  160. data = readl(bank->reg_base + bank->gpio_regs->ext_port);
  161. data >>= offset;
  162. data &= 1;
  163. return data;
  164. }
  165. static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
  166. unsigned int offset,
  167. unsigned int debounce)
  168. {
  169. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  170. const struct rockchip_gpio_regs *reg = bank->gpio_regs;
  171. unsigned long flags, div_reg, freq, max_debounce;
  172. bool div_debounce_support;
  173. unsigned int cur_div_reg;
  174. u64 div;
  175. if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
  176. div_debounce_support = true;
  177. freq = clk_get_rate(bank->db_clk);
  178. max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
  179. if (debounce > max_debounce)
  180. return -EINVAL;
  181. div = debounce * freq;
  182. div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
  183. } else {
  184. div_debounce_support = false;
  185. }
  186. raw_spin_lock_irqsave(&bank->slock, flags);
  187. /* Only the v1 needs to configure div_en and div_con for dbclk */
  188. if (debounce) {
  189. if (div_debounce_support) {
  190. /* Configure the max debounce from consumers */
  191. cur_div_reg = readl(bank->reg_base +
  192. reg->dbclk_div_con);
  193. if (cur_div_reg < div_reg)
  194. writel(div_reg, bank->reg_base +
  195. reg->dbclk_div_con);
  196. rockchip_gpio_writel_bit(bank, offset, 1,
  197. reg->dbclk_div_en);
  198. }
  199. rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
  200. } else {
  201. if (div_debounce_support)
  202. rockchip_gpio_writel_bit(bank, offset, 0,
  203. reg->dbclk_div_en);
  204. rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
  205. }
  206. raw_spin_unlock_irqrestore(&bank->slock, flags);
  207. /* Enable or disable dbclk at last */
  208. if (div_debounce_support) {
  209. if (debounce)
  210. clk_prepare_enable(bank->db_clk);
  211. else
  212. clk_disable_unprepare(bank->db_clk);
  213. }
  214. return 0;
  215. }
  216. static int rockchip_gpio_direction_input(struct gpio_chip *gc,
  217. unsigned int offset)
  218. {
  219. return rockchip_gpio_set_direction(gc, offset, true);
  220. }
  221. static int rockchip_gpio_direction_output(struct gpio_chip *gc,
  222. unsigned int offset, int value)
  223. {
  224. rockchip_gpio_set(gc, offset, value);
  225. return rockchip_gpio_set_direction(gc, offset, false);
  226. }
  227. /*
  228. * gpiolib set_config callback function. The setting of the pin
  229. * mux function as 'gpio output' will be handled by the pinctrl subsystem
  230. * interface.
  231. */
  232. static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
  233. unsigned long config)
  234. {
  235. enum pin_config_param param = pinconf_to_config_param(config);
  236. switch (param) {
  237. case PIN_CONFIG_INPUT_DEBOUNCE:
  238. rockchip_gpio_set_debounce(gc, offset, true);
  239. /*
  240. * Rockchip's gpio could only support up to one period
  241. * of the debounce clock(pclk), which is far away from
  242. * satisftying the requirement, as pclk is usually near
  243. * 100MHz shared by all peripherals. So the fact is it
  244. * has crippled debounce capability could only be useful
  245. * to prevent any spurious glitches from waking up the system
  246. * if the gpio is conguired as wakeup interrupt source. Let's
  247. * still return -ENOTSUPP as before, to make sure the caller
  248. * of gpiod_set_debounce won't change its behaviour.
  249. */
  250. return -ENOTSUPP;
  251. default:
  252. return -ENOTSUPP;
  253. }
  254. }
  255. /*
  256. * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
  257. * and a virtual IRQ, if not already present.
  258. */
  259. static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
  260. {
  261. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  262. unsigned int virq;
  263. if (!bank->domain)
  264. return -ENXIO;
  265. virq = irq_create_mapping(bank->domain, offset);
  266. return (virq) ? : -ENXIO;
  267. }
  268. static const struct gpio_chip rockchip_gpiolib_chip = {
  269. .request = gpiochip_generic_request,
  270. .free = gpiochip_generic_free,
  271. .set = rockchip_gpio_set,
  272. .get = rockchip_gpio_get,
  273. .get_direction = rockchip_gpio_get_direction,
  274. .direction_input = rockchip_gpio_direction_input,
  275. .direction_output = rockchip_gpio_direction_output,
  276. .set_config = rockchip_gpio_set_config,
  277. .to_irq = rockchip_gpio_to_irq,
  278. .owner = THIS_MODULE,
  279. };
  280. static void rockchip_irq_demux(struct irq_desc *desc)
  281. {
  282. struct irq_chip *chip = irq_desc_get_chip(desc);
  283. struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
  284. unsigned long pending;
  285. unsigned int irq;
  286. dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
  287. chained_irq_enter(chip, desc);
  288. pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
  289. for_each_set_bit(irq, &pending, 32) {
  290. dev_dbg(bank->dev, "handling irq %d\n", irq);
  291. /*
  292. * Triggering IRQ on both rising and falling edge
  293. * needs manual intervention.
  294. */
  295. if (bank->toggle_edge_mode & BIT(irq)) {
  296. u32 data, data_old, polarity;
  297. unsigned long flags;
  298. data = readl_relaxed(bank->reg_base +
  299. bank->gpio_regs->ext_port);
  300. do {
  301. raw_spin_lock_irqsave(&bank->slock, flags);
  302. polarity = readl_relaxed(bank->reg_base +
  303. bank->gpio_regs->int_polarity);
  304. if (data & BIT(irq))
  305. polarity &= ~BIT(irq);
  306. else
  307. polarity |= BIT(irq);
  308. writel(polarity,
  309. bank->reg_base +
  310. bank->gpio_regs->int_polarity);
  311. raw_spin_unlock_irqrestore(&bank->slock, flags);
  312. data_old = data;
  313. data = readl_relaxed(bank->reg_base +
  314. bank->gpio_regs->ext_port);
  315. } while ((data & BIT(irq)) != (data_old & BIT(irq)));
  316. }
  317. generic_handle_domain_irq(bank->domain, irq);
  318. }
  319. chained_irq_exit(chip, desc);
  320. }
  321. static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
  322. {
  323. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  324. struct rockchip_pin_bank *bank = gc->private;
  325. u32 mask = BIT(d->hwirq);
  326. u32 polarity;
  327. u32 level;
  328. u32 data;
  329. unsigned long flags;
  330. int ret = 0;
  331. raw_spin_lock_irqsave(&bank->slock, flags);
  332. rockchip_gpio_writel_bit(bank, d->hwirq, 0,
  333. bank->gpio_regs->port_ddr);
  334. raw_spin_unlock_irqrestore(&bank->slock, flags);
  335. if (type & IRQ_TYPE_EDGE_BOTH)
  336. irq_set_handler_locked(d, handle_edge_irq);
  337. else
  338. irq_set_handler_locked(d, handle_level_irq);
  339. raw_spin_lock_irqsave(&bank->slock, flags);
  340. level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
  341. polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
  342. if (type == IRQ_TYPE_EDGE_BOTH) {
  343. if (bank->gpio_type == GPIO_TYPE_V2) {
  344. rockchip_gpio_writel_bit(bank, d->hwirq, 1,
  345. bank->gpio_regs->int_bothedge);
  346. goto out;
  347. } else {
  348. bank->toggle_edge_mode |= mask;
  349. level &= ~mask;
  350. /*
  351. * Determine gpio state. If 1 next interrupt should be
  352. * low otherwise high.
  353. */
  354. data = readl(bank->reg_base + bank->gpio_regs->ext_port);
  355. if (data & mask)
  356. polarity &= ~mask;
  357. else
  358. polarity |= mask;
  359. }
  360. } else {
  361. if (bank->gpio_type == GPIO_TYPE_V2) {
  362. rockchip_gpio_writel_bit(bank, d->hwirq, 0,
  363. bank->gpio_regs->int_bothedge);
  364. } else {
  365. bank->toggle_edge_mode &= ~mask;
  366. }
  367. switch (type) {
  368. case IRQ_TYPE_EDGE_RISING:
  369. level |= mask;
  370. polarity |= mask;
  371. break;
  372. case IRQ_TYPE_EDGE_FALLING:
  373. level |= mask;
  374. polarity &= ~mask;
  375. break;
  376. case IRQ_TYPE_LEVEL_HIGH:
  377. level &= ~mask;
  378. polarity |= mask;
  379. break;
  380. case IRQ_TYPE_LEVEL_LOW:
  381. level &= ~mask;
  382. polarity &= ~mask;
  383. break;
  384. default:
  385. ret = -EINVAL;
  386. goto out;
  387. }
  388. }
  389. rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
  390. rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
  391. out:
  392. raw_spin_unlock_irqrestore(&bank->slock, flags);
  393. return ret;
  394. }
  395. static int rockchip_irq_reqres(struct irq_data *d)
  396. {
  397. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  398. struct rockchip_pin_bank *bank = gc->private;
  399. return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
  400. }
  401. static void rockchip_irq_relres(struct irq_data *d)
  402. {
  403. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  404. struct rockchip_pin_bank *bank = gc->private;
  405. gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
  406. }
  407. static void rockchip_irq_suspend(struct irq_data *d)
  408. {
  409. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  410. struct rockchip_pin_bank *bank = gc->private;
  411. bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
  412. irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
  413. }
  414. static void rockchip_irq_resume(struct irq_data *d)
  415. {
  416. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  417. struct rockchip_pin_bank *bank = gc->private;
  418. irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
  419. }
  420. static void rockchip_irq_enable(struct irq_data *d)
  421. {
  422. irq_gc_mask_clr_bit(d);
  423. }
  424. static void rockchip_irq_disable(struct irq_data *d)
  425. {
  426. irq_gc_mask_set_bit(d);
  427. }
  428. static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
  429. {
  430. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  431. struct irq_chip_generic *gc;
  432. int ret;
  433. bank->domain = irq_domain_add_linear(bank->of_node, 32,
  434. &irq_generic_chip_ops, NULL);
  435. if (!bank->domain) {
  436. dev_warn(bank->dev, "could not init irq domain for bank %s\n",
  437. bank->name);
  438. return -EINVAL;
  439. }
  440. ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
  441. "rockchip_gpio_irq",
  442. handle_level_irq,
  443. clr, 0, 0);
  444. if (ret) {
  445. dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
  446. bank->name);
  447. irq_domain_remove(bank->domain);
  448. return -EINVAL;
  449. }
  450. gc = irq_get_domain_generic_chip(bank->domain, 0);
  451. if (bank->gpio_type == GPIO_TYPE_V2) {
  452. gc->reg_writel = gpio_writel_v2;
  453. gc->reg_readl = gpio_readl_v2;
  454. }
  455. gc->reg_base = bank->reg_base;
  456. gc->private = bank;
  457. gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
  458. gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
  459. gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
  460. gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
  461. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
  462. gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
  463. gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
  464. gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
  465. gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
  466. gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
  467. gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
  468. gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres;
  469. gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres;
  470. gc->wake_enabled = IRQ_MSK(bank->nr_pins);
  471. /*
  472. * Linux assumes that all interrupts start out disabled/masked.
  473. * Our driver only uses the concept of masked and always keeps
  474. * things enabled, so for us that's all masked and all enabled.
  475. */
  476. rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
  477. rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
  478. rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
  479. gc->mask_cache = 0xffffffff;
  480. irq_set_chained_handler_and_data(bank->irq,
  481. rockchip_irq_demux, bank);
  482. return 0;
  483. }
  484. static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
  485. {
  486. struct gpio_chip *gc;
  487. int ret;
  488. bank->gpio_chip = rockchip_gpiolib_chip;
  489. gc = &bank->gpio_chip;
  490. gc->base = bank->pin_base;
  491. gc->ngpio = bank->nr_pins;
  492. gc->label = bank->name;
  493. gc->parent = bank->dev;
  494. ret = gpiochip_add_data(gc, bank);
  495. if (ret) {
  496. dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
  497. gc->label, ret);
  498. return ret;
  499. }
  500. /*
  501. * For DeviceTree-supported systems, the gpio core checks the
  502. * pinctrl's device node for the "gpio-ranges" property.
  503. * If it is present, it takes care of adding the pin ranges
  504. * for the driver. In this case the driver can skip ahead.
  505. *
  506. * In order to remain compatible with older, existing DeviceTree
  507. * files which don't set the "gpio-ranges" property or systems that
  508. * utilize ACPI the driver has to call gpiochip_add_pin_range().
  509. */
  510. if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
  511. struct device_node *pctlnp = of_get_parent(bank->of_node);
  512. struct pinctrl_dev *pctldev = NULL;
  513. if (!pctlnp)
  514. return -ENODATA;
  515. pctldev = of_pinctrl_get(pctlnp);
  516. of_node_put(pctlnp);
  517. if (!pctldev)
  518. return -ENODEV;
  519. ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
  520. gc->base, gc->ngpio);
  521. if (ret) {
  522. dev_err(bank->dev, "Failed to add pin range\n");
  523. goto fail;
  524. }
  525. }
  526. ret = rockchip_interrupts_register(bank);
  527. if (ret) {
  528. dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
  529. goto fail;
  530. }
  531. return 0;
  532. fail:
  533. gpiochip_remove(&bank->gpio_chip);
  534. return ret;
  535. }
  536. static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
  537. {
  538. struct resource res;
  539. int id = 0;
  540. if (of_address_to_resource(bank->of_node, 0, &res)) {
  541. dev_err(bank->dev, "cannot find IO resource for bank\n");
  542. return -ENOENT;
  543. }
  544. bank->reg_base = devm_ioremap_resource(bank->dev, &res);
  545. if (IS_ERR(bank->reg_base))
  546. return PTR_ERR(bank->reg_base);
  547. bank->irq = irq_of_parse_and_map(bank->of_node, 0);
  548. if (!bank->irq)
  549. return -EINVAL;
  550. bank->clk = of_clk_get(bank->of_node, 0);
  551. if (IS_ERR(bank->clk))
  552. return PTR_ERR(bank->clk);
  553. clk_prepare_enable(bank->clk);
  554. id = readl(bank->reg_base + gpio_regs_v2.version_id);
  555. /* If not gpio v2, that is default to v1. */
  556. if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
  557. bank->gpio_regs = &gpio_regs_v2;
  558. bank->gpio_type = GPIO_TYPE_V2;
  559. bank->db_clk = of_clk_get(bank->of_node, 1);
  560. if (IS_ERR(bank->db_clk)) {
  561. dev_err(bank->dev, "cannot find debounce clk\n");
  562. clk_disable_unprepare(bank->clk);
  563. return -EINVAL;
  564. }
  565. } else {
  566. bank->gpio_regs = &gpio_regs_v1;
  567. bank->gpio_type = GPIO_TYPE_V1;
  568. }
  569. return 0;
  570. }
  571. static struct rockchip_pin_bank *
  572. rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
  573. {
  574. struct rockchip_pinctrl *info;
  575. struct rockchip_pin_bank *bank;
  576. int i, found = 0;
  577. info = pinctrl_dev_get_drvdata(pctldev);
  578. bank = info->ctrl->pin_banks;
  579. for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
  580. if (bank->bank_num == id) {
  581. found = 1;
  582. break;
  583. }
  584. }
  585. return found ? bank : NULL;
  586. }
  587. static int rockchip_gpio_probe(struct platform_device *pdev)
  588. {
  589. struct device *dev = &pdev->dev;
  590. struct device_node *np = dev->of_node;
  591. struct device_node *pctlnp = of_get_parent(np);
  592. struct pinctrl_dev *pctldev = NULL;
  593. struct rockchip_pin_bank *bank = NULL;
  594. struct rockchip_pin_deferred *cfg;
  595. static int gpio;
  596. int id, ret;
  597. if (!np || !pctlnp)
  598. return -ENODEV;
  599. pctldev = of_pinctrl_get(pctlnp);
  600. if (!pctldev)
  601. return -EPROBE_DEFER;
  602. id = of_alias_get_id(np, "gpio");
  603. if (id < 0)
  604. id = gpio++;
  605. bank = rockchip_gpio_find_bank(pctldev, id);
  606. if (!bank)
  607. return -EINVAL;
  608. bank->dev = dev;
  609. bank->of_node = np;
  610. raw_spin_lock_init(&bank->slock);
  611. ret = rockchip_get_bank_data(bank);
  612. if (ret)
  613. return ret;
  614. /*
  615. * Prevent clashes with a deferred output setting
  616. * being added right at this moment.
  617. */
  618. mutex_lock(&bank->deferred_lock);
  619. ret = rockchip_gpiolib_register(bank);
  620. if (ret) {
  621. clk_disable_unprepare(bank->clk);
  622. mutex_unlock(&bank->deferred_lock);
  623. return ret;
  624. }
  625. while (!list_empty(&bank->deferred_pins)) {
  626. cfg = list_first_entry(&bank->deferred_pins,
  627. struct rockchip_pin_deferred, head);
  628. list_del(&cfg->head);
  629. switch (cfg->param) {
  630. case PIN_CONFIG_OUTPUT:
  631. ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
  632. if (ret)
  633. dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
  634. cfg->arg);
  635. break;
  636. case PIN_CONFIG_INPUT_ENABLE:
  637. ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);
  638. if (ret)
  639. dev_warn(dev, "setting input pin %u failed\n", cfg->pin);
  640. break;
  641. default:
  642. dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
  643. break;
  644. }
  645. kfree(cfg);
  646. }
  647. mutex_unlock(&bank->deferred_lock);
  648. platform_set_drvdata(pdev, bank);
  649. dev_info(dev, "probed %pOF\n", np);
  650. return 0;
  651. }
  652. static int rockchip_gpio_remove(struct platform_device *pdev)
  653. {
  654. struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
  655. clk_disable_unprepare(bank->clk);
  656. gpiochip_remove(&bank->gpio_chip);
  657. return 0;
  658. }
  659. static const struct of_device_id rockchip_gpio_match[] = {
  660. { .compatible = "rockchip,gpio-bank", },
  661. { .compatible = "rockchip,rk3188-gpio-bank0" },
  662. { },
  663. };
  664. static struct platform_driver rockchip_gpio_driver = {
  665. .probe = rockchip_gpio_probe,
  666. .remove = rockchip_gpio_remove,
  667. .driver = {
  668. .name = "rockchip-gpio",
  669. .of_match_table = rockchip_gpio_match,
  670. },
  671. };
  672. static int __init rockchip_gpio_init(void)
  673. {
  674. return platform_driver_register(&rockchip_gpio_driver);
  675. }
  676. postcore_initcall(rockchip_gpio_init);
  677. static void __exit rockchip_gpio_exit(void)
  678. {
  679. platform_driver_unregister(&rockchip_gpio_driver);
  680. }
  681. module_exit(rockchip_gpio_exit);
  682. MODULE_DESCRIPTION("Rockchip gpio driver");
  683. MODULE_ALIAS("platform:rockchip-gpio");
  684. MODULE_LICENSE("GPL v2");
  685. MODULE_DEVICE_TABLE(of, rockchip_gpio_match);