gpio-reg.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * gpio-reg: single register individually fixed-direction GPIOs
  4. *
  5. * Copyright (C) 2016 Russell King
  6. */
  7. #include <linux/gpio/driver.h>
  8. #include <linux/gpio/gpio-reg.h>
  9. #include <linux/io.h>
  10. #include <linux/slab.h>
  11. #include <linux/spinlock.h>
  12. struct gpio_reg {
  13. struct gpio_chip gc;
  14. spinlock_t lock;
  15. u32 direction;
  16. u32 out;
  17. void __iomem *reg;
  18. struct irq_domain *irqdomain;
  19. const int *irqs;
  20. };
  21. #define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
  22. static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
  23. {
  24. struct gpio_reg *r = to_gpio_reg(gc);
  25. return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN :
  26. GPIO_LINE_DIRECTION_OUT;
  27. }
  28. static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
  29. int value)
  30. {
  31. struct gpio_reg *r = to_gpio_reg(gc);
  32. if (r->direction & BIT(offset))
  33. return -ENOTSUPP;
  34. gc->set(gc, offset, value);
  35. return 0;
  36. }
  37. static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
  38. {
  39. struct gpio_reg *r = to_gpio_reg(gc);
  40. return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
  41. }
  42. static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
  43. {
  44. struct gpio_reg *r = to_gpio_reg(gc);
  45. unsigned long flags;
  46. u32 val, mask = BIT(offset);
  47. spin_lock_irqsave(&r->lock, flags);
  48. val = r->out;
  49. if (value)
  50. val |= mask;
  51. else
  52. val &= ~mask;
  53. r->out = val;
  54. writel_relaxed(val, r->reg);
  55. spin_unlock_irqrestore(&r->lock, flags);
  56. }
  57. static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
  58. {
  59. struct gpio_reg *r = to_gpio_reg(gc);
  60. u32 val, mask = BIT(offset);
  61. if (r->direction & mask) {
  62. /*
  63. * double-read the value, some registers latch after the
  64. * first read.
  65. */
  66. readl_relaxed(r->reg);
  67. val = readl_relaxed(r->reg);
  68. } else {
  69. val = r->out;
  70. }
  71. return !!(val & mask);
  72. }
  73. static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
  74. unsigned long *bits)
  75. {
  76. struct gpio_reg *r = to_gpio_reg(gc);
  77. unsigned long flags;
  78. spin_lock_irqsave(&r->lock, flags);
  79. r->out = (r->out & ~*mask) | (*bits & *mask);
  80. writel_relaxed(r->out, r->reg);
  81. spin_unlock_irqrestore(&r->lock, flags);
  82. }
  83. static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
  84. {
  85. struct gpio_reg *r = to_gpio_reg(gc);
  86. int irq = r->irqs[offset];
  87. if (irq >= 0 && r->irqdomain)
  88. irq = irq_find_mapping(r->irqdomain, irq);
  89. return irq;
  90. }
  91. /**
  92. * gpio_reg_init - add a fixed in/out register as gpio
  93. * @dev: optional struct device associated with this register
  94. * @base: start gpio number, or -1 to allocate
  95. * @num: number of GPIOs, maximum 32
  96. * @label: GPIO chip label
  97. * @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
  98. * @def_out: initial GPIO output value
  99. * @names: array of %num strings describing each GPIO signal or %NULL
  100. * @irqdom: irq domain or %NULL
  101. * @irqs: array of %num ints describing the interrupt mapping for each
  102. * GPIO signal, or %NULL. If @irqdom is %NULL, then this
  103. * describes the Linux interrupt number, otherwise it describes
  104. * the hardware interrupt number in the specified irq domain.
  105. *
  106. * Add a single-register GPIO device containing up to 32 GPIO signals,
  107. * where each GPIO has a fixed input or output configuration. Only
  108. * input GPIOs are assumed to be readable from the register, and only
  109. * then after a double-read. Output values are assumed not to be
  110. * readable.
  111. */
  112. struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
  113. int base, int num, const char *label, u32 direction, u32 def_out,
  114. const char *const *names, struct irq_domain *irqdom, const int *irqs)
  115. {
  116. struct gpio_reg *r;
  117. int ret;
  118. if (dev)
  119. r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
  120. else
  121. r = kzalloc(sizeof(*r), GFP_KERNEL);
  122. if (!r)
  123. return ERR_PTR(-ENOMEM);
  124. spin_lock_init(&r->lock);
  125. r->gc.label = label;
  126. r->gc.get_direction = gpio_reg_get_direction;
  127. r->gc.direction_input = gpio_reg_direction_input;
  128. r->gc.direction_output = gpio_reg_direction_output;
  129. r->gc.set = gpio_reg_set;
  130. r->gc.get = gpio_reg_get;
  131. r->gc.set_multiple = gpio_reg_set_multiple;
  132. if (irqs)
  133. r->gc.to_irq = gpio_reg_to_irq;
  134. r->gc.base = base;
  135. r->gc.ngpio = num;
  136. r->gc.names = names;
  137. r->direction = direction;
  138. r->out = def_out;
  139. r->reg = reg;
  140. r->irqs = irqs;
  141. if (dev)
  142. ret = devm_gpiochip_add_data(dev, &r->gc, r);
  143. else
  144. ret = gpiochip_add_data(&r->gc, r);
  145. return ret ? ERR_PTR(ret) : &r->gc;
  146. }
  147. int gpio_reg_resume(struct gpio_chip *gc)
  148. {
  149. struct gpio_reg *r = to_gpio_reg(gc);
  150. unsigned long flags;
  151. spin_lock_irqsave(&r->lock, flags);
  152. writel_relaxed(r->out, r->reg);
  153. spin_unlock_irqrestore(&r->lock, flags);
  154. return 0;
  155. }