gpio-pch.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  4. */
  5. #include <linux/bits.h>
  6. #include <linux/gpio/driver.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irq.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/pci.h>
  12. #include <linux/slab.h>
  13. #define PCH_EDGE_FALLING 0
  14. #define PCH_EDGE_RISING 1
  15. #define PCH_LEVEL_L 2
  16. #define PCH_LEVEL_H 3
  17. #define PCH_EDGE_BOTH 4
  18. #define PCH_IM_MASK GENMASK(2, 0)
  19. #define PCH_IRQ_BASE 24
  20. struct pch_regs {
  21. u32 ien;
  22. u32 istatus;
  23. u32 idisp;
  24. u32 iclr;
  25. u32 imask;
  26. u32 imaskclr;
  27. u32 po;
  28. u32 pi;
  29. u32 pm;
  30. u32 im0;
  31. u32 im1;
  32. u32 reserved[3];
  33. u32 gpio_use_sel;
  34. u32 reset;
  35. };
  36. #define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803
  37. #define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014
  38. #define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043
  39. #define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803
  40. enum pch_type_t {
  41. INTEL_EG20T_PCH,
  42. OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
  43. OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
  44. };
  45. /* Specifies number of GPIO PINS */
  46. static int gpio_pins[] = {
  47. [INTEL_EG20T_PCH] = 12,
  48. [OKISEMI_ML7223m_IOH] = 8,
  49. [OKISEMI_ML7223n_IOH] = 8,
  50. };
  51. /**
  52. * struct pch_gpio_reg_data - The register store data.
  53. * @ien_reg: To store contents of IEN register.
  54. * @imask_reg: To store contents of IMASK register.
  55. * @po_reg: To store contents of PO register.
  56. * @pm_reg: To store contents of PM register.
  57. * @im0_reg: To store contents of IM0 register.
  58. * @im1_reg: To store contents of IM1 register.
  59. * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
  60. * (Only ML7223 Bus-n)
  61. */
  62. struct pch_gpio_reg_data {
  63. u32 ien_reg;
  64. u32 imask_reg;
  65. u32 po_reg;
  66. u32 pm_reg;
  67. u32 im0_reg;
  68. u32 im1_reg;
  69. u32 gpio_use_sel_reg;
  70. };
  71. /**
  72. * struct pch_gpio - GPIO private data structure.
  73. * @base: PCI base address of Memory mapped I/O register.
  74. * @reg: Memory mapped PCH GPIO register list.
  75. * @dev: Pointer to device structure.
  76. * @gpio: Data for GPIO infrastructure.
  77. * @pch_gpio_reg: Memory mapped Register data is saved here
  78. * when suspend.
  79. * @lock: Used for register access protection
  80. * @irq_base: Save base of IRQ number for interrupt
  81. * @ioh: IOH ID
  82. * @spinlock: Used for register access protection
  83. */
  84. struct pch_gpio {
  85. void __iomem *base;
  86. struct pch_regs __iomem *reg;
  87. struct device *dev;
  88. struct gpio_chip gpio;
  89. struct pch_gpio_reg_data pch_gpio_reg;
  90. int irq_base;
  91. enum pch_type_t ioh;
  92. spinlock_t spinlock;
  93. };
  94. static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
  95. {
  96. u32 reg_val;
  97. struct pch_gpio *chip = gpiochip_get_data(gpio);
  98. unsigned long flags;
  99. spin_lock_irqsave(&chip->spinlock, flags);
  100. reg_val = ioread32(&chip->reg->po);
  101. if (val)
  102. reg_val |= BIT(nr);
  103. else
  104. reg_val &= ~BIT(nr);
  105. iowrite32(reg_val, &chip->reg->po);
  106. spin_unlock_irqrestore(&chip->spinlock, flags);
  107. }
  108. static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
  109. {
  110. struct pch_gpio *chip = gpiochip_get_data(gpio);
  111. return !!(ioread32(&chip->reg->pi) & BIT(nr));
  112. }
  113. static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
  114. int val)
  115. {
  116. struct pch_gpio *chip = gpiochip_get_data(gpio);
  117. u32 pm;
  118. u32 reg_val;
  119. unsigned long flags;
  120. spin_lock_irqsave(&chip->spinlock, flags);
  121. reg_val = ioread32(&chip->reg->po);
  122. if (val)
  123. reg_val |= BIT(nr);
  124. else
  125. reg_val &= ~BIT(nr);
  126. iowrite32(reg_val, &chip->reg->po);
  127. pm = ioread32(&chip->reg->pm);
  128. pm &= BIT(gpio_pins[chip->ioh]) - 1;
  129. pm |= BIT(nr);
  130. iowrite32(pm, &chip->reg->pm);
  131. spin_unlock_irqrestore(&chip->spinlock, flags);
  132. return 0;
  133. }
  134. static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
  135. {
  136. struct pch_gpio *chip = gpiochip_get_data(gpio);
  137. u32 pm;
  138. unsigned long flags;
  139. spin_lock_irqsave(&chip->spinlock, flags);
  140. pm = ioread32(&chip->reg->pm);
  141. pm &= BIT(gpio_pins[chip->ioh]) - 1;
  142. pm &= ~BIT(nr);
  143. iowrite32(pm, &chip->reg->pm);
  144. spin_unlock_irqrestore(&chip->spinlock, flags);
  145. return 0;
  146. }
  147. /*
  148. * Save register configuration and disable interrupts.
  149. */
  150. static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
  151. {
  152. chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
  153. chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
  154. chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
  155. chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
  156. chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
  157. if (chip->ioh == INTEL_EG20T_PCH)
  158. chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
  159. if (chip->ioh == OKISEMI_ML7223n_IOH)
  160. chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
  161. }
  162. /*
  163. * This function restores the register configuration of the GPIO device.
  164. */
  165. static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
  166. {
  167. iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
  168. iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
  169. /* to store contents of PO register */
  170. iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
  171. /* to store contents of PM register */
  172. iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
  173. iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
  174. if (chip->ioh == INTEL_EG20T_PCH)
  175. iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
  176. if (chip->ioh == OKISEMI_ML7223n_IOH)
  177. iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
  178. }
  179. static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
  180. {
  181. struct pch_gpio *chip = gpiochip_get_data(gpio);
  182. return chip->irq_base + offset;
  183. }
  184. static void pch_gpio_setup(struct pch_gpio *chip)
  185. {
  186. struct gpio_chip *gpio = &chip->gpio;
  187. gpio->label = dev_name(chip->dev);
  188. gpio->parent = chip->dev;
  189. gpio->owner = THIS_MODULE;
  190. gpio->direction_input = pch_gpio_direction_input;
  191. gpio->get = pch_gpio_get;
  192. gpio->direction_output = pch_gpio_direction_output;
  193. gpio->set = pch_gpio_set;
  194. gpio->base = -1;
  195. gpio->ngpio = gpio_pins[chip->ioh];
  196. gpio->can_sleep = false;
  197. gpio->to_irq = pch_gpio_to_irq;
  198. }
  199. static int pch_irq_type(struct irq_data *d, unsigned int type)
  200. {
  201. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  202. struct pch_gpio *chip = gc->private;
  203. u32 im, im_pos, val;
  204. u32 __iomem *im_reg;
  205. unsigned long flags;
  206. int ch, irq = d->irq;
  207. ch = irq - chip->irq_base;
  208. if (irq < chip->irq_base + 8) {
  209. im_reg = &chip->reg->im0;
  210. im_pos = ch - 0;
  211. } else {
  212. im_reg = &chip->reg->im1;
  213. im_pos = ch - 8;
  214. }
  215. dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
  216. switch (type) {
  217. case IRQ_TYPE_EDGE_RISING:
  218. val = PCH_EDGE_RISING;
  219. break;
  220. case IRQ_TYPE_EDGE_FALLING:
  221. val = PCH_EDGE_FALLING;
  222. break;
  223. case IRQ_TYPE_EDGE_BOTH:
  224. val = PCH_EDGE_BOTH;
  225. break;
  226. case IRQ_TYPE_LEVEL_HIGH:
  227. val = PCH_LEVEL_H;
  228. break;
  229. case IRQ_TYPE_LEVEL_LOW:
  230. val = PCH_LEVEL_L;
  231. break;
  232. default:
  233. return 0;
  234. }
  235. spin_lock_irqsave(&chip->spinlock, flags);
  236. /* Set interrupt mode */
  237. im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
  238. iowrite32(im | (val << (im_pos * 4)), im_reg);
  239. /* And the handler */
  240. if (type & IRQ_TYPE_LEVEL_MASK)
  241. irq_set_handler_locked(d, handle_level_irq);
  242. else if (type & IRQ_TYPE_EDGE_BOTH)
  243. irq_set_handler_locked(d, handle_edge_irq);
  244. spin_unlock_irqrestore(&chip->spinlock, flags);
  245. return 0;
  246. }
  247. static void pch_irq_unmask(struct irq_data *d)
  248. {
  249. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  250. struct pch_gpio *chip = gc->private;
  251. iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
  252. }
  253. static void pch_irq_mask(struct irq_data *d)
  254. {
  255. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  256. struct pch_gpio *chip = gc->private;
  257. iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
  258. }
  259. static void pch_irq_ack(struct irq_data *d)
  260. {
  261. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  262. struct pch_gpio *chip = gc->private;
  263. iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
  264. }
  265. static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
  266. {
  267. struct pch_gpio *chip = dev_id;
  268. unsigned long reg_val = ioread32(&chip->reg->istatus);
  269. int i;
  270. dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
  271. reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
  272. for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
  273. generic_handle_irq(chip->irq_base + i);
  274. return IRQ_RETVAL(reg_val);
  275. }
  276. static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
  277. unsigned int irq_start,
  278. unsigned int num)
  279. {
  280. struct irq_chip_generic *gc;
  281. struct irq_chip_type *ct;
  282. int rv;
  283. gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
  284. chip->base, handle_simple_irq);
  285. if (!gc)
  286. return -ENOMEM;
  287. gc->private = chip;
  288. ct = gc->chip_types;
  289. ct->chip.irq_ack = pch_irq_ack;
  290. ct->chip.irq_mask = pch_irq_mask;
  291. ct->chip.irq_unmask = pch_irq_unmask;
  292. ct->chip.irq_set_type = pch_irq_type;
  293. rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
  294. IRQ_GC_INIT_MASK_CACHE,
  295. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  296. return rv;
  297. }
  298. static int pch_gpio_probe(struct pci_dev *pdev,
  299. const struct pci_device_id *id)
  300. {
  301. struct device *dev = &pdev->dev;
  302. s32 ret;
  303. struct pch_gpio *chip;
  304. int irq_base;
  305. chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  306. if (chip == NULL)
  307. return -ENOMEM;
  308. chip->dev = dev;
  309. ret = pcim_enable_device(pdev);
  310. if (ret)
  311. return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
  312. ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
  313. if (ret)
  314. return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
  315. chip->base = pcim_iomap_table(pdev)[1];
  316. chip->ioh = id->driver_data;
  317. chip->reg = chip->base;
  318. pci_set_drvdata(pdev, chip);
  319. spin_lock_init(&chip->spinlock);
  320. pch_gpio_setup(chip);
  321. ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
  322. if (ret)
  323. return dev_err_probe(dev, ret, "Failed to register GPIO\n");
  324. irq_base = devm_irq_alloc_descs(dev, -1, 0,
  325. gpio_pins[chip->ioh], NUMA_NO_NODE);
  326. if (irq_base < 0) {
  327. dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
  328. chip->irq_base = -1;
  329. return 0;
  330. }
  331. chip->irq_base = irq_base;
  332. /* Mask all interrupts, but enable them */
  333. iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
  334. iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
  335. ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
  336. IRQF_SHARED, KBUILD_MODNAME, chip);
  337. if (ret)
  338. return dev_err_probe(dev, ret, "Failed to request IRQ\n");
  339. return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
  340. }
  341. static int __maybe_unused pch_gpio_suspend(struct device *dev)
  342. {
  343. struct pch_gpio *chip = dev_get_drvdata(dev);
  344. unsigned long flags;
  345. spin_lock_irqsave(&chip->spinlock, flags);
  346. pch_gpio_save_reg_conf(chip);
  347. spin_unlock_irqrestore(&chip->spinlock, flags);
  348. return 0;
  349. }
  350. static int __maybe_unused pch_gpio_resume(struct device *dev)
  351. {
  352. struct pch_gpio *chip = dev_get_drvdata(dev);
  353. unsigned long flags;
  354. spin_lock_irqsave(&chip->spinlock, flags);
  355. iowrite32(0x01, &chip->reg->reset);
  356. iowrite32(0x00, &chip->reg->reset);
  357. pch_gpio_restore_reg_conf(chip);
  358. spin_unlock_irqrestore(&chip->spinlock, flags);
  359. return 0;
  360. }
  361. static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
  362. static const struct pci_device_id pch_gpio_pcidev_id[] = {
  363. { PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
  364. { PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
  365. { PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
  366. { PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
  367. { }
  368. };
  369. MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
  370. static struct pci_driver pch_gpio_driver = {
  371. .name = "pch_gpio",
  372. .id_table = pch_gpio_pcidev_id,
  373. .probe = pch_gpio_probe,
  374. .driver = {
  375. .pm = &pch_gpio_pm_ops,
  376. },
  377. };
  378. module_pci_driver(pch_gpio_driver);
  379. MODULE_DESCRIPTION("PCH GPIO PCI Driver");
  380. MODULE_LICENSE("GPL v2");