gpio-max77620.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MAXIM MAX77620 GPIO driver
  4. *
  5. * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/gpio/driver.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/mfd/max77620.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
  14. struct max77620_gpio {
  15. struct gpio_chip gpio_chip;
  16. struct regmap *rmap;
  17. struct device *dev;
  18. struct mutex buslock; /* irq_bus_lock */
  19. unsigned int irq_type[MAX77620_GPIO_NR];
  20. bool irq_enabled[MAX77620_GPIO_NR];
  21. };
  22. static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
  23. {
  24. struct max77620_gpio *gpio = data;
  25. unsigned int value, offset;
  26. unsigned long pending;
  27. int err;
  28. err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
  29. if (err < 0) {
  30. dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
  31. return IRQ_NONE;
  32. }
  33. pending = value;
  34. for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
  35. unsigned int virq;
  36. virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
  37. handle_nested_irq(virq);
  38. }
  39. return IRQ_HANDLED;
  40. }
  41. static void max77620_gpio_irq_mask(struct irq_data *data)
  42. {
  43. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  44. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  45. gpio->irq_enabled[data->hwirq] = false;
  46. gpiochip_disable_irq(chip, data->hwirq);
  47. }
  48. static void max77620_gpio_irq_unmask(struct irq_data *data)
  49. {
  50. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  51. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  52. gpiochip_enable_irq(chip, data->hwirq);
  53. gpio->irq_enabled[data->hwirq] = true;
  54. }
  55. static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
  56. {
  57. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  58. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  59. unsigned int irq_type;
  60. switch (type) {
  61. case IRQ_TYPE_EDGE_RISING:
  62. irq_type = MAX77620_CNFG_GPIO_INT_RISING;
  63. break;
  64. case IRQ_TYPE_EDGE_FALLING:
  65. irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
  66. break;
  67. case IRQ_TYPE_EDGE_BOTH:
  68. irq_type = MAX77620_CNFG_GPIO_INT_RISING |
  69. MAX77620_CNFG_GPIO_INT_FALLING;
  70. break;
  71. default:
  72. return -EINVAL;
  73. }
  74. gpio->irq_type[data->hwirq] = irq_type;
  75. return 0;
  76. }
  77. static void max77620_gpio_bus_lock(struct irq_data *data)
  78. {
  79. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  80. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  81. mutex_lock(&gpio->buslock);
  82. }
  83. static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
  84. {
  85. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  86. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  87. unsigned int value, offset = data->hwirq;
  88. int err;
  89. value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
  90. err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
  91. MAX77620_CNFG_GPIO_INT_MASK, value);
  92. if (err < 0)
  93. dev_err(chip->parent, "failed to update interrupt mask: %d\n",
  94. err);
  95. mutex_unlock(&gpio->buslock);
  96. }
  97. static const struct irq_chip max77620_gpio_irqchip = {
  98. .name = "max77620-gpio",
  99. .irq_mask = max77620_gpio_irq_mask,
  100. .irq_unmask = max77620_gpio_irq_unmask,
  101. .irq_set_type = max77620_gpio_set_irq_type,
  102. .irq_bus_lock = max77620_gpio_bus_lock,
  103. .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
  104. .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
  105. GPIOCHIP_IRQ_RESOURCE_HELPERS,
  106. };
  107. static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
  108. {
  109. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  110. int ret;
  111. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  112. MAX77620_CNFG_GPIO_DIR_MASK,
  113. MAX77620_CNFG_GPIO_DIR_INPUT);
  114. if (ret < 0)
  115. dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
  116. return ret;
  117. }
  118. static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
  119. {
  120. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  121. unsigned int val;
  122. int ret;
  123. ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
  124. if (ret < 0) {
  125. dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
  126. return ret;
  127. }
  128. if (val & MAX77620_CNFG_GPIO_DIR_MASK)
  129. return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
  130. else
  131. return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
  132. }
  133. static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
  134. int value)
  135. {
  136. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  137. u8 val;
  138. int ret;
  139. val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
  140. MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
  141. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  142. MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
  143. if (ret < 0) {
  144. dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
  145. return ret;
  146. }
  147. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  148. MAX77620_CNFG_GPIO_DIR_MASK,
  149. MAX77620_CNFG_GPIO_DIR_OUTPUT);
  150. if (ret < 0)
  151. dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
  152. return ret;
  153. }
  154. static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
  155. unsigned int offset,
  156. unsigned int debounce)
  157. {
  158. u8 val;
  159. int ret;
  160. switch (debounce) {
  161. case 0:
  162. val = MAX77620_CNFG_GPIO_DBNC_None;
  163. break;
  164. case 1 ... 8000:
  165. val = MAX77620_CNFG_GPIO_DBNC_8ms;
  166. break;
  167. case 8001 ... 16000:
  168. val = MAX77620_CNFG_GPIO_DBNC_16ms;
  169. break;
  170. case 16001 ... 32000:
  171. val = MAX77620_CNFG_GPIO_DBNC_32ms;
  172. break;
  173. default:
  174. dev_err(mgpio->dev, "Illegal value %u\n", debounce);
  175. return -EINVAL;
  176. }
  177. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  178. MAX77620_CNFG_GPIO_DBNC_MASK, val);
  179. if (ret < 0)
  180. dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
  181. return ret;
  182. }
  183. static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
  184. int value)
  185. {
  186. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  187. u8 val;
  188. int ret;
  189. val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
  190. MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
  191. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  192. MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
  193. if (ret < 0)
  194. dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
  195. }
  196. static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
  197. unsigned long config)
  198. {
  199. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  200. switch (pinconf_to_config_param(config)) {
  201. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  202. return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  203. MAX77620_CNFG_GPIO_DRV_MASK,
  204. MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
  205. case PIN_CONFIG_DRIVE_PUSH_PULL:
  206. return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  207. MAX77620_CNFG_GPIO_DRV_MASK,
  208. MAX77620_CNFG_GPIO_DRV_PUSHPULL);
  209. case PIN_CONFIG_INPUT_DEBOUNCE:
  210. return max77620_gpio_set_debounce(mgpio, offset,
  211. pinconf_to_config_argument(config));
  212. default:
  213. break;
  214. }
  215. return -ENOTSUPP;
  216. }
  217. static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
  218. {
  219. struct max77620_gpio *gpio = gpiochip_get_data(gc);
  220. unsigned int i;
  221. int err;
  222. /*
  223. * GPIO interrupts may be left ON after bootloader, hence let's
  224. * pre-initialize hardware to the expected state by disabling all
  225. * the interrupts.
  226. */
  227. for (i = 0; i < MAX77620_GPIO_NR; i++) {
  228. err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
  229. MAX77620_CNFG_GPIO_INT_MASK, 0);
  230. if (err < 0) {
  231. dev_err(gpio->dev,
  232. "failed to disable interrupt: %d\n", err);
  233. return err;
  234. }
  235. }
  236. return 0;
  237. }
  238. static int max77620_gpio_probe(struct platform_device *pdev)
  239. {
  240. struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
  241. struct max77620_gpio *mgpio;
  242. struct gpio_irq_chip *girq;
  243. unsigned int gpio_irq;
  244. int ret;
  245. ret = platform_get_irq(pdev, 0);
  246. if (ret < 0)
  247. return ret;
  248. gpio_irq = ret;
  249. mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
  250. if (!mgpio)
  251. return -ENOMEM;
  252. mutex_init(&mgpio->buslock);
  253. mgpio->rmap = chip->rmap;
  254. mgpio->dev = &pdev->dev;
  255. mgpio->gpio_chip.label = pdev->name;
  256. mgpio->gpio_chip.parent = pdev->dev.parent;
  257. mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
  258. mgpio->gpio_chip.get = max77620_gpio_get;
  259. mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
  260. mgpio->gpio_chip.set = max77620_gpio_set;
  261. mgpio->gpio_chip.set_config = max77620_gpio_set_config;
  262. mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
  263. mgpio->gpio_chip.can_sleep = 1;
  264. mgpio->gpio_chip.base = -1;
  265. girq = &mgpio->gpio_chip.irq;
  266. gpio_irq_chip_set_chip(girq, &max77620_gpio_irqchip);
  267. /* This will let us handle the parent IRQ in the driver */
  268. girq->parent_handler = NULL;
  269. girq->num_parents = 0;
  270. girq->parents = NULL;
  271. girq->default_type = IRQ_TYPE_NONE;
  272. girq->handler = handle_edge_irq;
  273. girq->init_hw = max77620_gpio_irq_init_hw;
  274. girq->threaded = true;
  275. platform_set_drvdata(pdev, mgpio);
  276. ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
  277. if (ret < 0) {
  278. dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
  279. return ret;
  280. }
  281. ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
  282. max77620_gpio_irqhandler, IRQF_ONESHOT,
  283. "max77620-gpio", mgpio);
  284. if (ret < 0) {
  285. dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
  286. return ret;
  287. }
  288. return 0;
  289. }
  290. static const struct platform_device_id max77620_gpio_devtype[] = {
  291. { .name = "max77620-gpio", },
  292. { .name = "max20024-gpio", },
  293. {},
  294. };
  295. MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
  296. static struct platform_driver max77620_gpio_driver = {
  297. .driver.name = "max77620-gpio",
  298. .probe = max77620_gpio_probe,
  299. .id_table = max77620_gpio_devtype,
  300. };
  301. module_platform_driver(max77620_gpio_driver);
  302. MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
  303. MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
  304. MODULE_AUTHOR("Chaitanya Bandi <[email protected]>");
  305. MODULE_LICENSE("GPL v2");