gpio-hlwd.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (C) 2008-2009 The GameCube Linux Team
  3. // Copyright (C) 2008,2009 Albert Herranz
  4. // Copyright (C) 2017-2018 Jonathan Neuschäfer
  5. //
  6. // Nintendo Wii (Hollywood) GPIO driver
  7. #include <linux/gpio/driver.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/slab.h>
  14. /*
  15. * Register names and offsets courtesy of WiiBrew:
  16. * https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
  17. *
  18. * Note that for most registers, there are two versions:
  19. * - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
  20. * always give access to all GPIO lines
  21. * - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
  22. * firewall (AHBPROT) in the Hollywood chipset has been configured to allow
  23. * such access.
  24. *
  25. * The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
  26. * register: A one bit configures the line for access via the HW_GPIOB_*
  27. * registers, a zero bit indicates access via HW_GPIO_*. This driver uses
  28. * HW_GPIOB_*.
  29. */
  30. #define HW_GPIOB_OUT 0x00
  31. #define HW_GPIOB_DIR 0x04
  32. #define HW_GPIOB_IN 0x08
  33. #define HW_GPIOB_INTLVL 0x0c
  34. #define HW_GPIOB_INTFLAG 0x10
  35. #define HW_GPIOB_INTMASK 0x14
  36. #define HW_GPIOB_INMIR 0x18
  37. #define HW_GPIO_ENABLE 0x1c
  38. #define HW_GPIO_OUT 0x20
  39. #define HW_GPIO_DIR 0x24
  40. #define HW_GPIO_IN 0x28
  41. #define HW_GPIO_INTLVL 0x2c
  42. #define HW_GPIO_INTFLAG 0x30
  43. #define HW_GPIO_INTMASK 0x34
  44. #define HW_GPIO_INMIR 0x38
  45. #define HW_GPIO_OWNER 0x3c
  46. struct hlwd_gpio {
  47. struct gpio_chip gpioc;
  48. struct irq_chip irqc;
  49. void __iomem *regs;
  50. int irq;
  51. u32 edge_emulation;
  52. u32 rising_edge, falling_edge;
  53. };
  54. static void hlwd_gpio_irqhandler(struct irq_desc *desc)
  55. {
  56. struct hlwd_gpio *hlwd =
  57. gpiochip_get_data(irq_desc_get_handler_data(desc));
  58. struct irq_chip *chip = irq_desc_get_chip(desc);
  59. unsigned long flags;
  60. unsigned long pending;
  61. int hwirq;
  62. u32 emulated_pending;
  63. raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
  64. pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
  65. pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
  66. /* Treat interrupts due to edge trigger emulation separately */
  67. emulated_pending = hlwd->edge_emulation & pending;
  68. pending &= ~emulated_pending;
  69. if (emulated_pending) {
  70. u32 level, rising, falling;
  71. level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
  72. rising = level & emulated_pending;
  73. falling = ~level & emulated_pending;
  74. /* Invert the levels */
  75. iowrite32be(level ^ emulated_pending,
  76. hlwd->regs + HW_GPIOB_INTLVL);
  77. /* Ack all emulated-edge interrupts */
  78. iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
  79. /* Signal interrupts only on the correct edge */
  80. rising &= hlwd->rising_edge;
  81. falling &= hlwd->falling_edge;
  82. /* Mark emulated interrupts as pending */
  83. pending |= rising | falling;
  84. }
  85. raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
  86. chained_irq_enter(chip, desc);
  87. for_each_set_bit(hwirq, &pending, 32)
  88. generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
  89. chained_irq_exit(chip, desc);
  90. }
  91. static void hlwd_gpio_irq_ack(struct irq_data *data)
  92. {
  93. struct hlwd_gpio *hlwd =
  94. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  95. iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
  96. }
  97. static void hlwd_gpio_irq_mask(struct irq_data *data)
  98. {
  99. struct hlwd_gpio *hlwd =
  100. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  101. unsigned long flags;
  102. u32 mask;
  103. raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
  104. mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
  105. mask &= ~BIT(data->hwirq);
  106. iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
  107. raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
  108. }
  109. static void hlwd_gpio_irq_unmask(struct irq_data *data)
  110. {
  111. struct hlwd_gpio *hlwd =
  112. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  113. unsigned long flags;
  114. u32 mask;
  115. raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
  116. mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
  117. mask |= BIT(data->hwirq);
  118. iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
  119. raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
  120. }
  121. static void hlwd_gpio_irq_enable(struct irq_data *data)
  122. {
  123. hlwd_gpio_irq_ack(data);
  124. hlwd_gpio_irq_unmask(data);
  125. }
  126. static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
  127. unsigned int flow_type)
  128. {
  129. u32 level, state;
  130. /* Set the trigger level to the inactive level */
  131. level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
  132. state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
  133. level &= ~BIT(hwirq);
  134. level |= state ^ BIT(hwirq);
  135. iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
  136. hlwd->edge_emulation |= BIT(hwirq);
  137. hlwd->rising_edge &= ~BIT(hwirq);
  138. hlwd->falling_edge &= ~BIT(hwirq);
  139. if (flow_type & IRQ_TYPE_EDGE_RISING)
  140. hlwd->rising_edge |= BIT(hwirq);
  141. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  142. hlwd->falling_edge |= BIT(hwirq);
  143. }
  144. static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
  145. {
  146. struct hlwd_gpio *hlwd =
  147. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  148. unsigned long flags;
  149. u32 level;
  150. raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
  151. hlwd->edge_emulation &= ~BIT(data->hwirq);
  152. switch (flow_type) {
  153. case IRQ_TYPE_LEVEL_HIGH:
  154. level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
  155. level |= BIT(data->hwirq);
  156. iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
  157. break;
  158. case IRQ_TYPE_LEVEL_LOW:
  159. level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
  160. level &= ~BIT(data->hwirq);
  161. iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
  162. break;
  163. case IRQ_TYPE_EDGE_RISING:
  164. case IRQ_TYPE_EDGE_FALLING:
  165. case IRQ_TYPE_EDGE_BOTH:
  166. hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
  167. break;
  168. default:
  169. raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
  170. return -EINVAL;
  171. }
  172. raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
  173. return 0;
  174. }
  175. static int hlwd_gpio_probe(struct platform_device *pdev)
  176. {
  177. struct hlwd_gpio *hlwd;
  178. u32 ngpios;
  179. int res;
  180. hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
  181. if (!hlwd)
  182. return -ENOMEM;
  183. hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
  184. if (IS_ERR(hlwd->regs))
  185. return PTR_ERR(hlwd->regs);
  186. /*
  187. * Claim all GPIOs using the OWNER register. This will not work on
  188. * systems where the AHBPROT memory firewall hasn't been configured to
  189. * permit PPC access to HW_GPIO_*.
  190. *
  191. * Note that this has to happen before bgpio_init reads the
  192. * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
  193. * values.
  194. */
  195. iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
  196. res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
  197. hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
  198. NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
  199. BGPIOF_BIG_ENDIAN_BYTE_ORDER);
  200. if (res < 0) {
  201. dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
  202. return res;
  203. }
  204. res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
  205. if (res)
  206. ngpios = 32;
  207. hlwd->gpioc.ngpio = ngpios;
  208. /* Mask and ack all interrupts */
  209. iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
  210. iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
  211. /*
  212. * If this GPIO controller is not marked as an interrupt controller in
  213. * the DT, skip interrupt support.
  214. */
  215. if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
  216. struct gpio_irq_chip *girq;
  217. hlwd->irq = platform_get_irq(pdev, 0);
  218. if (hlwd->irq < 0) {
  219. dev_info(&pdev->dev, "platform_get_irq returned %d\n",
  220. hlwd->irq);
  221. return hlwd->irq;
  222. }
  223. hlwd->irqc.name = dev_name(&pdev->dev);
  224. hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
  225. hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
  226. hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
  227. hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
  228. girq = &hlwd->gpioc.irq;
  229. girq->chip = &hlwd->irqc;
  230. girq->parent_handler = hlwd_gpio_irqhandler;
  231. girq->num_parents = 1;
  232. girq->parents = devm_kcalloc(&pdev->dev, 1,
  233. sizeof(*girq->parents),
  234. GFP_KERNEL);
  235. if (!girq->parents)
  236. return -ENOMEM;
  237. girq->parents[0] = hlwd->irq;
  238. girq->default_type = IRQ_TYPE_NONE;
  239. girq->handler = handle_level_irq;
  240. }
  241. return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
  242. }
  243. static const struct of_device_id hlwd_gpio_match[] = {
  244. { .compatible = "nintendo,hollywood-gpio", },
  245. {},
  246. };
  247. MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
  248. static struct platform_driver hlwd_gpio_driver = {
  249. .driver = {
  250. .name = "gpio-hlwd",
  251. .of_match_table = hlwd_gpio_match,
  252. },
  253. .probe = hlwd_gpio_probe,
  254. };
  255. module_platform_driver(hlwd_gpio_driver);
  256. MODULE_AUTHOR("Jonathan Neuschäfer <[email protected]>");
  257. MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
  258. MODULE_LICENSE("GPL");