gpio-bcm-kona.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Broadcom Kona GPIO Driver
  4. *
  5. * Author: Broadcom Corporation <[email protected]>
  6. * Copyright (C) 2012-2014 Broadcom Corporation
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/of_device.h>
  13. #include <linux/init.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/irqchip/chained_irq.h>
  16. #define BCM_GPIO_PASSWD 0x00a5a501
  17. #define GPIO_PER_BANK 32
  18. #define GPIO_MAX_BANK_NUM 8
  19. #define GPIO_BANK(gpio) ((gpio) >> 5)
  20. #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
  21. /* There is a GPIO control register for each GPIO */
  22. #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
  23. /* The remaining registers are per GPIO bank */
  24. #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
  25. #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
  26. #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
  27. #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
  28. #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
  29. #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
  30. #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
  31. #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
  32. #define GPIO_GPPWR_OFFSET 0x00000520
  33. #define GPIO_GPCTR0_DBR_SHIFT 5
  34. #define GPIO_GPCTR0_DBR_MASK 0x000001e0
  35. #define GPIO_GPCTR0_ITR_SHIFT 3
  36. #define GPIO_GPCTR0_ITR_MASK 0x00000018
  37. #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
  38. #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
  39. #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
  40. #define GPIO_GPCTR0_IOTR_MASK 0x00000001
  41. #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
  42. #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
  43. #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
  44. #define LOCK_CODE 0xffffffff
  45. #define UNLOCK_CODE 0x00000000
  46. struct bcm_kona_gpio {
  47. void __iomem *reg_base;
  48. int num_bank;
  49. raw_spinlock_t lock;
  50. struct gpio_chip gpio_chip;
  51. struct irq_domain *irq_domain;
  52. struct bcm_kona_gpio_bank *banks;
  53. struct platform_device *pdev;
  54. };
  55. struct bcm_kona_gpio_bank {
  56. int id;
  57. int irq;
  58. /* Used in the interrupt handler */
  59. struct bcm_kona_gpio *kona_gpio;
  60. };
  61. static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
  62. int bank_id, u32 lockcode)
  63. {
  64. writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
  65. writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
  66. }
  67. static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
  68. unsigned gpio)
  69. {
  70. u32 val;
  71. unsigned long flags;
  72. int bank_id = GPIO_BANK(gpio);
  73. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  74. val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
  75. val |= BIT(gpio);
  76. bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
  77. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  78. }
  79. static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
  80. unsigned gpio)
  81. {
  82. u32 val;
  83. unsigned long flags;
  84. int bank_id = GPIO_BANK(gpio);
  85. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  86. val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
  87. val &= ~BIT(gpio);
  88. bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
  89. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  90. }
  91. static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
  92. {
  93. struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
  94. void __iomem *reg_base = kona_gpio->reg_base;
  95. u32 val;
  96. val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
  97. return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
  98. }
  99. static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
  100. {
  101. struct bcm_kona_gpio *kona_gpio;
  102. void __iomem *reg_base;
  103. int bank_id = GPIO_BANK(gpio);
  104. int bit = GPIO_BIT(gpio);
  105. u32 val, reg_offset;
  106. unsigned long flags;
  107. kona_gpio = gpiochip_get_data(chip);
  108. reg_base = kona_gpio->reg_base;
  109. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  110. /* this function only applies to output pin */
  111. if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
  112. goto out;
  113. reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
  114. val = readl(reg_base + reg_offset);
  115. val |= BIT(bit);
  116. writel(val, reg_base + reg_offset);
  117. out:
  118. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  119. }
  120. static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
  121. {
  122. struct bcm_kona_gpio *kona_gpio;
  123. void __iomem *reg_base;
  124. int bank_id = GPIO_BANK(gpio);
  125. int bit = GPIO_BIT(gpio);
  126. u32 val, reg_offset;
  127. unsigned long flags;
  128. kona_gpio = gpiochip_get_data(chip);
  129. reg_base = kona_gpio->reg_base;
  130. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  131. if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
  132. reg_offset = GPIO_IN_STATUS(bank_id);
  133. else
  134. reg_offset = GPIO_OUT_STATUS(bank_id);
  135. /* read the GPIO bank status */
  136. val = readl(reg_base + reg_offset);
  137. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  138. /* return the specified bit status */
  139. return !!(val & BIT(bit));
  140. }
  141. static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
  142. {
  143. struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
  144. bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
  145. return 0;
  146. }
  147. static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
  148. {
  149. struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
  150. bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
  151. }
  152. static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  153. {
  154. struct bcm_kona_gpio *kona_gpio;
  155. void __iomem *reg_base;
  156. u32 val;
  157. unsigned long flags;
  158. kona_gpio = gpiochip_get_data(chip);
  159. reg_base = kona_gpio->reg_base;
  160. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  161. val = readl(reg_base + GPIO_CONTROL(gpio));
  162. val &= ~GPIO_GPCTR0_IOTR_MASK;
  163. val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
  164. writel(val, reg_base + GPIO_CONTROL(gpio));
  165. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  166. return 0;
  167. }
  168. static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
  169. unsigned gpio, int value)
  170. {
  171. struct bcm_kona_gpio *kona_gpio;
  172. void __iomem *reg_base;
  173. int bank_id = GPIO_BANK(gpio);
  174. int bit = GPIO_BIT(gpio);
  175. u32 val, reg_offset;
  176. unsigned long flags;
  177. kona_gpio = gpiochip_get_data(chip);
  178. reg_base = kona_gpio->reg_base;
  179. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  180. val = readl(reg_base + GPIO_CONTROL(gpio));
  181. val &= ~GPIO_GPCTR0_IOTR_MASK;
  182. val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
  183. writel(val, reg_base + GPIO_CONTROL(gpio));
  184. reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
  185. val = readl(reg_base + reg_offset);
  186. val |= BIT(bit);
  187. writel(val, reg_base + reg_offset);
  188. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  189. return 0;
  190. }
  191. static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
  192. {
  193. struct bcm_kona_gpio *kona_gpio;
  194. kona_gpio = gpiochip_get_data(chip);
  195. if (gpio >= kona_gpio->gpio_chip.ngpio)
  196. return -ENXIO;
  197. return irq_create_mapping(kona_gpio->irq_domain, gpio);
  198. }
  199. static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
  200. unsigned debounce)
  201. {
  202. struct bcm_kona_gpio *kona_gpio;
  203. void __iomem *reg_base;
  204. u32 val, res;
  205. unsigned long flags;
  206. kona_gpio = gpiochip_get_data(chip);
  207. reg_base = kona_gpio->reg_base;
  208. /* debounce must be 1-128ms (or 0) */
  209. if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
  210. dev_err(chip->parent, "Debounce value %u not in range\n",
  211. debounce);
  212. return -EINVAL;
  213. }
  214. /* calculate debounce bit value */
  215. if (debounce != 0) {
  216. /* Convert to ms */
  217. debounce /= 1000;
  218. /* find the MSB */
  219. res = fls(debounce) - 1;
  220. /* Check if MSB-1 is set (round up or down) */
  221. if (res > 0 && (debounce & BIT(res - 1)))
  222. res++;
  223. }
  224. /* spin lock for read-modify-write of the GPIO register */
  225. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  226. val = readl(reg_base + GPIO_CONTROL(gpio));
  227. val &= ~GPIO_GPCTR0_DBR_MASK;
  228. if (debounce == 0) {
  229. /* disable debounce */
  230. val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
  231. } else {
  232. val |= GPIO_GPCTR0_DB_ENABLE_MASK |
  233. (res << GPIO_GPCTR0_DBR_SHIFT);
  234. }
  235. writel(val, reg_base + GPIO_CONTROL(gpio));
  236. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  237. return 0;
  238. }
  239. static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
  240. unsigned long config)
  241. {
  242. u32 debounce;
  243. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  244. return -ENOTSUPP;
  245. debounce = pinconf_to_config_argument(config);
  246. return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
  247. }
  248. static const struct gpio_chip template_chip = {
  249. .label = "bcm-kona-gpio",
  250. .owner = THIS_MODULE,
  251. .request = bcm_kona_gpio_request,
  252. .free = bcm_kona_gpio_free,
  253. .get_direction = bcm_kona_gpio_get_dir,
  254. .direction_input = bcm_kona_gpio_direction_input,
  255. .get = bcm_kona_gpio_get,
  256. .direction_output = bcm_kona_gpio_direction_output,
  257. .set = bcm_kona_gpio_set,
  258. .set_config = bcm_kona_gpio_set_config,
  259. .to_irq = bcm_kona_gpio_to_irq,
  260. .base = 0,
  261. };
  262. static void bcm_kona_gpio_irq_ack(struct irq_data *d)
  263. {
  264. struct bcm_kona_gpio *kona_gpio;
  265. void __iomem *reg_base;
  266. unsigned gpio = d->hwirq;
  267. int bank_id = GPIO_BANK(gpio);
  268. int bit = GPIO_BIT(gpio);
  269. u32 val;
  270. unsigned long flags;
  271. kona_gpio = irq_data_get_irq_chip_data(d);
  272. reg_base = kona_gpio->reg_base;
  273. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  274. val = readl(reg_base + GPIO_INT_STATUS(bank_id));
  275. val |= BIT(bit);
  276. writel(val, reg_base + GPIO_INT_STATUS(bank_id));
  277. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  278. }
  279. static void bcm_kona_gpio_irq_mask(struct irq_data *d)
  280. {
  281. struct bcm_kona_gpio *kona_gpio;
  282. void __iomem *reg_base;
  283. unsigned gpio = d->hwirq;
  284. int bank_id = GPIO_BANK(gpio);
  285. int bit = GPIO_BIT(gpio);
  286. u32 val;
  287. unsigned long flags;
  288. kona_gpio = irq_data_get_irq_chip_data(d);
  289. reg_base = kona_gpio->reg_base;
  290. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  291. val = readl(reg_base + GPIO_INT_MASK(bank_id));
  292. val |= BIT(bit);
  293. writel(val, reg_base + GPIO_INT_MASK(bank_id));
  294. gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
  295. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  296. }
  297. static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
  298. {
  299. struct bcm_kona_gpio *kona_gpio;
  300. void __iomem *reg_base;
  301. unsigned gpio = d->hwirq;
  302. int bank_id = GPIO_BANK(gpio);
  303. int bit = GPIO_BIT(gpio);
  304. u32 val;
  305. unsigned long flags;
  306. kona_gpio = irq_data_get_irq_chip_data(d);
  307. reg_base = kona_gpio->reg_base;
  308. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  309. val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
  310. val |= BIT(bit);
  311. writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
  312. gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
  313. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  314. }
  315. static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  316. {
  317. struct bcm_kona_gpio *kona_gpio;
  318. void __iomem *reg_base;
  319. unsigned gpio = d->hwirq;
  320. u32 lvl_type;
  321. u32 val;
  322. unsigned long flags;
  323. kona_gpio = irq_data_get_irq_chip_data(d);
  324. reg_base = kona_gpio->reg_base;
  325. switch (type & IRQ_TYPE_SENSE_MASK) {
  326. case IRQ_TYPE_EDGE_RISING:
  327. lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
  328. break;
  329. case IRQ_TYPE_EDGE_FALLING:
  330. lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
  331. break;
  332. case IRQ_TYPE_EDGE_BOTH:
  333. lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
  334. break;
  335. case IRQ_TYPE_LEVEL_HIGH:
  336. case IRQ_TYPE_LEVEL_LOW:
  337. /* BCM GPIO doesn't support level triggering */
  338. default:
  339. dev_err(kona_gpio->gpio_chip.parent,
  340. "Invalid BCM GPIO irq type 0x%x\n", type);
  341. return -EINVAL;
  342. }
  343. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  344. val = readl(reg_base + GPIO_CONTROL(gpio));
  345. val &= ~GPIO_GPCTR0_ITR_MASK;
  346. val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
  347. writel(val, reg_base + GPIO_CONTROL(gpio));
  348. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  349. return 0;
  350. }
  351. static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
  352. {
  353. void __iomem *reg_base;
  354. int bit, bank_id;
  355. unsigned long sta;
  356. struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
  357. struct irq_chip *chip = irq_desc_get_chip(desc);
  358. chained_irq_enter(chip, desc);
  359. /*
  360. * For bank interrupts, we can't use chip_data to store the kona_gpio
  361. * pointer, since GIC needs it for its own purposes. Therefore, we get
  362. * our pointer from the bank structure.
  363. */
  364. reg_base = bank->kona_gpio->reg_base;
  365. bank_id = bank->id;
  366. while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
  367. (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
  368. for_each_set_bit(bit, &sta, 32) {
  369. int hwirq = GPIO_PER_BANK * bank_id + bit;
  370. /*
  371. * Clear interrupt before handler is called so we don't
  372. * miss any interrupt occurred during executing them.
  373. */
  374. writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
  375. BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
  376. /* Invoke interrupt handler */
  377. generic_handle_domain_irq(bank->kona_gpio->irq_domain,
  378. hwirq);
  379. }
  380. }
  381. chained_irq_exit(chip, desc);
  382. }
  383. static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
  384. {
  385. struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
  386. return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
  387. }
  388. static void bcm_kona_gpio_irq_relres(struct irq_data *d)
  389. {
  390. struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
  391. gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
  392. }
  393. static struct irq_chip bcm_gpio_irq_chip = {
  394. .name = "bcm-kona-gpio",
  395. .irq_ack = bcm_kona_gpio_irq_ack,
  396. .irq_mask = bcm_kona_gpio_irq_mask,
  397. .irq_unmask = bcm_kona_gpio_irq_unmask,
  398. .irq_set_type = bcm_kona_gpio_irq_set_type,
  399. .irq_request_resources = bcm_kona_gpio_irq_reqres,
  400. .irq_release_resources = bcm_kona_gpio_irq_relres,
  401. };
  402. static struct of_device_id const bcm_kona_gpio_of_match[] = {
  403. { .compatible = "brcm,kona-gpio" },
  404. {}
  405. };
  406. /*
  407. * This lock class tells lockdep that GPIO irqs are in a different
  408. * category than their parents, so it won't report false recursion.
  409. */
  410. static struct lock_class_key gpio_lock_class;
  411. static struct lock_class_key gpio_request_class;
  412. static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  413. irq_hw_number_t hwirq)
  414. {
  415. int ret;
  416. ret = irq_set_chip_data(irq, d->host_data);
  417. if (ret < 0)
  418. return ret;
  419. irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
  420. irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
  421. irq_set_noprobe(irq);
  422. return 0;
  423. }
  424. static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
  425. {
  426. irq_set_chip_and_handler(irq, NULL, NULL);
  427. irq_set_chip_data(irq, NULL);
  428. }
  429. static const struct irq_domain_ops bcm_kona_irq_ops = {
  430. .map = bcm_kona_gpio_irq_map,
  431. .unmap = bcm_kona_gpio_irq_unmap,
  432. .xlate = irq_domain_xlate_twocell,
  433. };
  434. static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
  435. {
  436. void __iomem *reg_base;
  437. int i;
  438. reg_base = kona_gpio->reg_base;
  439. /* disable interrupts and clear status */
  440. for (i = 0; i < kona_gpio->num_bank; i++) {
  441. /* Unlock the entire bank first */
  442. bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
  443. writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
  444. writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
  445. /* Now re-lock the bank */
  446. bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
  447. }
  448. }
  449. static int bcm_kona_gpio_probe(struct platform_device *pdev)
  450. {
  451. struct device *dev = &pdev->dev;
  452. const struct of_device_id *match;
  453. struct bcm_kona_gpio_bank *bank;
  454. struct bcm_kona_gpio *kona_gpio;
  455. struct gpio_chip *chip;
  456. int ret;
  457. int i;
  458. match = of_match_device(bcm_kona_gpio_of_match, dev);
  459. if (!match) {
  460. dev_err(dev, "Failed to find gpio controller\n");
  461. return -ENODEV;
  462. }
  463. kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
  464. if (!kona_gpio)
  465. return -ENOMEM;
  466. kona_gpio->gpio_chip = template_chip;
  467. chip = &kona_gpio->gpio_chip;
  468. ret = platform_irq_count(pdev);
  469. if (!ret) {
  470. dev_err(dev, "Couldn't determine # GPIO banks\n");
  471. return -ENOENT;
  472. } else if (ret < 0) {
  473. return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
  474. }
  475. kona_gpio->num_bank = ret;
  476. if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
  477. dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
  478. GPIO_MAX_BANK_NUM);
  479. return -ENXIO;
  480. }
  481. kona_gpio->banks = devm_kcalloc(dev,
  482. kona_gpio->num_bank,
  483. sizeof(*kona_gpio->banks),
  484. GFP_KERNEL);
  485. if (!kona_gpio->banks)
  486. return -ENOMEM;
  487. kona_gpio->pdev = pdev;
  488. platform_set_drvdata(pdev, kona_gpio);
  489. chip->parent = dev;
  490. chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
  491. kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
  492. chip->ngpio,
  493. &bcm_kona_irq_ops,
  494. kona_gpio);
  495. if (!kona_gpio->irq_domain) {
  496. dev_err(dev, "Couldn't allocate IRQ domain\n");
  497. return -ENXIO;
  498. }
  499. kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
  500. if (IS_ERR(kona_gpio->reg_base)) {
  501. ret = PTR_ERR(kona_gpio->reg_base);
  502. goto err_irq_domain;
  503. }
  504. for (i = 0; i < kona_gpio->num_bank; i++) {
  505. bank = &kona_gpio->banks[i];
  506. bank->id = i;
  507. bank->irq = platform_get_irq(pdev, i);
  508. bank->kona_gpio = kona_gpio;
  509. if (bank->irq < 0) {
  510. dev_err(dev, "Couldn't get IRQ for bank %d", i);
  511. ret = -ENOENT;
  512. goto err_irq_domain;
  513. }
  514. }
  515. dev_info(&pdev->dev, "Setting up Kona GPIO\n");
  516. bcm_kona_gpio_reset(kona_gpio);
  517. ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
  518. if (ret < 0) {
  519. dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
  520. goto err_irq_domain;
  521. }
  522. for (i = 0; i < kona_gpio->num_bank; i++) {
  523. bank = &kona_gpio->banks[i];
  524. irq_set_chained_handler_and_data(bank->irq,
  525. bcm_kona_gpio_irq_handler,
  526. bank);
  527. }
  528. raw_spin_lock_init(&kona_gpio->lock);
  529. return 0;
  530. err_irq_domain:
  531. irq_domain_remove(kona_gpio->irq_domain);
  532. return ret;
  533. }
  534. static struct platform_driver bcm_kona_gpio_driver = {
  535. .driver = {
  536. .name = "bcm-kona-gpio",
  537. .of_match_table = bcm_kona_gpio_of_match,
  538. },
  539. .probe = bcm_kona_gpio_probe,
  540. };
  541. builtin_platform_driver(bcm_kona_gpio_driver);